2-3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
407-727-9207
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Copyright
Intersil Corporation 1999
Block Diagram
TRUTH TABLE
ENABLE
IN
OUT
H
H
L
H
L
H
L
X
H
CA3242
Quad-Gated Inverting Power Driver For
Interfacing Low-Level Logic to High Current Load
Description
The CA3242 quad-gated inverting power driver contains four
gate switches for interfacing low-level logic to inductive and
resistive loads such as: relays, solenoids, AC and DC
motors, heaters, incandescent displays, and vacuum fluo-
rescent displays.
Output overload protection is provided when the load current
(approximately 1.2A) causes the output V
CE
(sat) to rise
above 1.3V. A built-in time delay, nominally 25
s, is provided
during output turn-on as output drops from V
DD
to V
SAT
. That
output will be shut down by its protection network without
affecting the other outputs. The corresponding Input or
Enable must be toggled to reset the output protection circuit.
Steering diodes in the outputs in conjunction with external
zener diodes protect the IC against voltage transients due to
switching inductive loads.
To allow for maximum heat transfer from the chip, the four
center leads are directly connected to the die mounting pad.
In free air, junction-to-air thermal resistance (R
JA
) is 60
o
C/W
(typical). This coefficient can be lowered by suitable design
of the PC board to which the CA3242 is soldered.
Features
Driven Outputs Capable of Switching 600mA Load
Currents Without Spurious Changes in Output State
Inputs Compatible with TTL or 5V CMOS Logic
Suitable for Resistive or Inductive Loads
Output Overload Protection
Power-Frame Construction for Good Heat Dissipation
Applications
Relays
Solenoids
AC and DC Motors
Heaters
Incandescent Displays
Vacuum Fluorescent Displays
Ordering Information
PART NUMBER
TEMPERATURE
RANGE
PACKAGE
CA3242E
-40
o
C to +105
o
C
16 Lead Plastic DIP
File Number
1561.2
August 1998
Pinout
CA3242 (PDIP)
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
IN A
ENABLE
GND
GND
INC
IND
IN B
V
CC
OUT A
CLAMP
OUT B
GND
GND
OUT C
OUT D
CLAMP
P
P
P
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
OUT D
CLAMP
OUT C
GND
GND
OUT B
CLAMP
OUT A
IN A
IN B
ENABLE
GND
GND
VCC
IN C
IN D
P
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