CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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Intersil Corporation 2000

CA1524, CA2524

CA3524

Regulating Pulse Width Modulator

Description

The CA1524 and CA3524 are silicon monolithic integrated
circuits designed to provide all the control circuitry for use in
a broad range of switching regulator circuits.

The CA1524 and CA3524 have all the features of the indus-
try types SG1524, SG2524, and SG3524, respectively. A
block diagram of the CA1524 series is shown in Figure 1.
The circuit includes a zener voltage reference, transconduc-
tance error amplifier, precision R-C oscillator, pulse-width
modulator, pulse-steering flip-flop, dual alternating output
switches, and current-limiting and shutdown circuitry. This
device can be used for switching regulators of either polarity,
transformer-coupled dc-dc converter, transformerless volt-
age doublers, dc-ac power inverters, highly efficient variable
power supplies, and polarity converter, as well as other
power-control applications.

Ordering Information

PART

NUMBER

TEMPERATURE

RANGE

PACKAGE

CA1524E

-55

C to +125

16 Lead Plastic DIP

CA1524F

-55

C to +125

16 Lead CerDIP

CA2524E

C to +70

16 Lead Plastic DIP

CA2524F

C to +70

16 Lead CerDIP

CA3524E

C to +70

16 Lead Plastic DIP

CA3524F

C to +70

16 Lead CerDIP

Features

· Complete PWM Power Control Circuitry

· Separate Outputs for Single-Ended or Push-Pull

Operation

· Line and Load Regulation . . . . . . . . . . . . . . . 0.2% (Typ)

· Internal Reference Supply with 1% (Max) Oscillator

and Reference Voltage Variation Over Full
Temperature Range

· Standby Current of Less Than 10mA

· Frequency of Operation Beyond 100kHz

· Variable-Output Dead Time of 0.5

s to 5

· Low V

CE(sat)

Over the Temperature Range

Applications

· Positive and Negative Regulated Supplies

· Dual-Output Regulators

· Flyback Converters

· DC-DC Transformer-Coupled Regulating Converters

· Single-Ended DC-DC Converters

· Variable Power Supplies

File Number

1239.4

Pinout

CA1524, CA3524

(PDIP, CERDIP)

TOP VIEW

REF

EMITTER B

COLLECTOR B

COLLECTOR A

EMITTER A

SHUTDOWN

INV. INPUT

OSC OUT

GND

(-) C.L.

SENSE

(+) C.L.
SENSE

V+

COMPENSATION
AND COMPARATOR

NON-

INV. INPUT

October 2000

CA2524 IS AN OBSOLETE

PRODUCT

Specifications CA1524, CA2524, CA3524

Absolute Maximum Ratings

Thermal Information

Input Voltage (Between V

and GND Terminals). . . . . . . . . . . . 40V

Operating Voltage Range (V

to GND) . . . . . . . . . . . . . . . . 8 to 40V

Output Current Each Output:

(Terminal 11, 12 or 13, 14) . . . . . . . . . . . . . . . . . . . . . . . . . 100mA

Output Current (Reference Regulator) . . . . . . . . . . . . . . . . . . . 50mA
Oscillator Charging Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA

Thermal Resistance

Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . .

100

C/W

Device Dissipation

Up to T

= +25

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25W

Above T

= +25

C . . . . . . . . . . . . . . .Derate Linearly at 10mW/

Operating Temperature Range . . . . . . . . . . . . . . . . -55

C to +125

Storage Temperature Range . . . . . . . . . . . . . . . . . . -65

C to +150

Lead Temperature (During Soldering)

At distance 1/16

in. (1.59mm

0.79mm)

from case for 10s Max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Electrical Specifications

= -55

C to +125

C for CA1524, 0

C to +70

C for the CA2524 and CA3524; V+ = 20V and

f = 20kHz, Unless Otherwise Stated.

PARAMETER

TEST CONDITIONS

CA1524, CA2524

CA3524

UNITS

MIN

TYP

MAX

MIN

TYP

MAX

REFERENCE SECTION

Output Voltage

4.8

5.2

4.6

5.4

Line Regulation

V+ = 8 to 40V

Load Regulation

= 0 to 20mA

Ripple Rejection

f = 120Hz, T

= 25

Short Circuit Current Limit

REF

= 0, T

= 25

100

Temperature Stability

Over Operating Temperature
Range

0.3

Long Term Stability

= 25

mV/khr

OSCILLATOR SECTION

Maximum Frequency

= 0.001

F, R

= 2K

300

kHz

Initial Accuracy

and C

Constant

Voltage Stability

V+ = 8 to 40V, T

= 25

Temperature Stability

Over Operating Temperature
Range

Output Amplitude

Terminal 3, T

= 25

3.5

Output Pulse Width (Pin 3)

= 0.01

F, T

= 25

0.5

Ramp Voltage Low (Note 1)

Pin 7

0.6

Ramp Voltage High (Note 1)

Pin 7

3.5

Capacitor Charging Current Range

Pin 7 (5-2 V

)/R

0.03

Timing Resistance Range

Pin 6

1.8

120

1.8

120

Charging Capacitor Range

Pin 7

0.001

0.1

0.001

0.1

Dead Time Expansion Capacitor on
Pin 3 (when a small osc. cap is used)

Pin 3

100

1000

100

1000

ERROR AMPLIFIER SECTION

Input Offset Voltage

= 2.5V

0.5

Input Bias Current

= 2.5V

Open Loop Voltage Gain

Common Mode Voltage

= 25

1.8

3.4

1.8

3.4

Common Mode Rejection Ratio

= 25

Small Signal Bandwidth

= 0dB, T

= 25

MHz

Specifications CA1524, CA2524, CA3524

Output Voltage

= 25

0.5

3.8

0.5

3.8

Amplifier Pole

250

Pin 9 Shutdown Current

External Sink

200

COMPARATOR SECTION

Duty Cycle

% Each Output On

Input Threshold

Zero Duty Cycle

Input Threshold

Max. Duty Cycle

3.5

Input Bias Current

CURRENT LIMITING SECTION

Sense Voltage for 25% Output Duty
Cycle

Terminal 9 = 2V with Error
Amplifier Set for Max Out,
T

= 25

190

200

210

180

200

220

Sense Voltage T.C.

0.2

mV/

Common Mode Voltage

-1

Rolloff Pole of R51 C3 + Q64

300

OUTPUT SECTION (EACH OUTUT)

Collector-Emitter Voltage

Collector Leakage Current

= 40V

0.1

Saturation Voltage

V+ = 40V, I

= 50mA

0.8

Emitter Output Voltage

V+ = 20V

Rise Time

= 2K

, T

= 25

0.2

Fall Time

= 2K

, T

= 25

0.1

Total Standby Current: (Note 2) I

V+ = 40V

NOTES:

1. Ramp voltage at Pin 7

where

t = OSC period in microseconds
t

with C

in microfarads and R

in ohms.

Output frequency at each output transistor is half OSC frequency when each output is used separately and is equal to the OSC frequency
when each output is connected in parallel.

2. Excluding oscillator charging current, error and current limit dividers, and with outputs open.

Electrical Specifications

= -55

C to +125

C for CA1524, 0

C to +70

C for the CA2524 and CA3524; V+ = 20V and

f = 20kHz, Unless Otherwise Stated. (Continued)

PARAMETER

TEST CONDITIONS

CA1524, CA2524

CA3524

UNITS

MIN

TYP

MAX

MIN

TYP

MAX

High

Low

CA1524, CA2524, CA3524

Schematic Diagram

500

R5
1K

R7
1K

Q13

Q3 Q4

2.7K

10K

6.3K

Q10

Q11

20pF

500

Q12

4.8K

5.3K

OSC SECTION

Q42

Q43

Q44

Q47

Q48

Q49

Q50

Q45

Q46

R39
1K

R41
24K

R40

560

R42

19.8K

Q51

Q52

R45
25K

R44
1.8K

R43
7.4K

Q53

Q54

Q55

R46
3.3K

OSC.

OUT

Q59

Q60

Q61

Q56 Q57

INV.

ERROR

AMP

NON-INV.
INPUT

Q58

Q62

R47
1K

R48

K
L

F
G
H
I

D
E

Q24

Q22

Q20

R15
25K

20pF

10K

1.9K

Q19

R14
450

Q14

Q15

R8
8.4K

R9
500

R10
1K

Q17

Q18

R11

500

R12
10K

Q16

R13

15 V

PULSE

STEERING
FLIP-FLOP

R16
16.2K

R19
18.7
K

R17
18.7
K

R18

18.7

R18

18.7

Q21

Q23

REF

+5V

GND

CA1524, CA2524, CA3524

Schematic Diagram

(Continued)

COLL. A

EMIT A

COLL. B

EMIT B

OUTPUT A

Q34

Q36

Q35

R33

200

R32
1K

R34

500

1pF

R31
4.7

500

Q33

OUTPUT B

Q40

Q37

Q38

Q39

RF
500

R38

4.7

Q41

R35

500

R37

R36

200

1pF

R21
43.3K

R25

R24

Q26

Q27

R23
8.7K

R26

Q29

R27

Q30

Q31

R30
43.3K

R28
8.7K

NOR

R52
1.96K

R54
1.96K

Q65

Q67

COMP

R49
1K

R50
10K

Q63

Q64

Q66

CURRENT

LIMIT

SECTION

R51
10K

R53

1.8K

45pF

(-) C.L.

SENSE

Q68

Q71

Q70

Q68

Q73

Q72

COMPARATOR

(+) C.L.
SENSE

CA1524, CA2524, CA3524

Circuit Description

Voltage Reference Section

The CAl524 series contains an internal series voltage regu-
lator employing a zener reference to provide a nominal 5-volt
output, which is used to bias all internal timing and control
circuitry. The output of this regulator is available at terminal
l6 and is capable of supplying up to 50mA output current.

Figure 1 shows the temperature variation of the reference
voltage with supply voltages of 8V to 40V and load currents
up to 20mA. Load regulation and line regulation curves are
shown in Figures 2 and 3, respectively.

FIGURE 1. TYPICAL REFERENCE VOLTAGE AS A FUNCTION

OF AMBIENT TEMPERATURE

FIGURE 2. TYPICAL REFERENCE VOLTAGE AS A FUNCTION

OF REFERENCE OUTPUT CURRENT

FIGURE 3. TYPICAL REFERENCE VOLTAGE AS A FUNCTION

OF SUPPLY VOLTAGE

5.02

5.00

4.98

4.96

REFERENCE V

GE (V)

-60 -40 -20

80 100 120 140

AMBIENT TEMPERATURE (

V+ = 40V, I

= 0mA

V+ = 20V, I

= 0mA

V+ = 40V, I

= 20mA

V+ = 8V, I

= 0mA

V+ = 20V, I

= 20mA

V+ = 8V, I

= 20mA

REFERENCE V

GE (V)

5.1

4.9

4.7

4.5

4.3

4.1

3.9

3.7

3.5

REFERENCE OUTPUT CURRENT (mA)

TA = +25oC

V+ = 20V

V+ = 40V

V+ = 20V

V+ = 8V

REFERENCE V

GE (V)

SUPPLY VOLTAGE, V+ (V)

TA = +25oC

Osclllator Section

Transistors Q42, Q43 and Q44, in conjunction with an
external resistor R

, establishes a constant charging current

into an external capacitor C

to provide a linear ramp voltage

at terminal 7. The ramp voltage has a value that ranges from
0.6V to 3.5V and is used as the reference for the comparator
in the device. The charging current is equal to (5-2V

)/R

approximately 3.6/R

and should be kept within the range of

30pA to 2mA by varying R

. The discharge time of C

deter-

mines the pulse width of the oscillator output pulse at termi-
nal 3. This pulse has a practical range of 0.5

s to 5

s for a

capacitor range of 0.001 to 0.1

F. The pulse has two internal

uses: as a dead-time control of blanking pulse to the output
stages to assure that both outputs cannot be on simulta-
neously and as a trigger pulse to the internal flip-flop which
controls the switching of the output between the two output
channels. The output dead-time relationship is shown in Fig-
ure 4. Pulse widths less than 0.5

s may allow false trigger-

ing of one output by removing the blanking pulse prior to a
stable state in the flip-flop.

FIGURE 4. TYPICAL OUTPUT STAGE DEAD TIME AS A

FUNCTION OF TIMING CAPACITOR VALUE

If a small value of C

must be used, the pulse width can be

further expanded by the addition of a shunt capacitor in the
order of 100pF but no greater than 1000pF, from terminal 3
to ground. When the oscillator output pulse is used as a sync
input to an oscilloscope, the cable and input capacitances
may increase the pulse width slightly. A 2-K

resistor at

terminal 3 will usually provide sufficient decoupling of the
cable. The upper limit of the pulse width is determined by the
maximum duty cycle acceptable.

The oscillator period is determined by R

and C

, with an

approximate value of t = R

, where R

is in ohms, C

is in

F, and t is in

s. Excess lead lengths, which produce stray

capacitances, should be avoided in connecting R

and C

their respective terminals. Figure 5 provides curves for
selecting these values for a wide range of oscillator periods.
For series regulator applications, the two outputs can be
connected in parallel for an effective 0-90% duty cycle with
the output stage frequency the same as the oscillator
frequency. Since the outputs are separate, push-pull and
flyback applications are possible. The flip-flop divides the
frequency such that the duty cycle of each output is 0-45%
and the overall frequency is half that of the oscillator. Curves

OUTPUT DEAD TIME (

100

1.0

0.1

0.0001

0.001

0.01

0.1

1.0

TIMING CAPACITOR, C

(

= +25

V+ = 8V - 40V

CA1524, CA2524, CA3524

of the output duty cycle as a function of the voltage at
terminal 9 are shown in Figure 7. To synchronize two or
more CAl524's, one must be designated as master, with R

set for the correct period. Each of the remaining units

(slaves) must have a C

of 1/2 the value used in the master

and approximately a 1010 longer R

period than the mas-

ter. Connecting terminal 3 together on all units assures that
the master output pulse, which occurs first and has a wider
pulse width, will reset the slave units.

FIGURE 5. TYPICAL OSCILLATOR PERIOD AS A FUNCTION

OF R

AND C

Error AmplIfIer Section

The error amplifier consists of a differential pair (Q56,Q57)
with an active load (Q61 and Q62) forming a differential
transconductance amplifier. Since Q61 is driven by a
constant current source, Q62, the output impedance R

OUT

terminal 9, is very high (

The gain is:

= g

R = 8 l

R/2KT = 10

Since R

OUT

is extremely high, the gain can be easily

reduced from a nominal 10

(80dB) by the addition of an

external shunt resistor from terminal 9 to ground as shown in
Figure 6.

FIGURE 6. OPEN-LOOP ERROR AMPLIFIER RESPONSE

CHARACTERISTICS.

where R =

OUT

, R

, A

OUT

TIMING RESIST

ANCE, R

(

)

OSCILLATOR PERIOD, t (

= +25

V+ = 8V - 40V

= 0.01

= 0.002

= 0.005

= 0.001

= 0.02

= 0.05

= 0.1

GE GAIN (dB)

PHASE ANGLE (DEGREES)

= 3M

= 1M

= 300k

=100k

OPEN LOOP PHASE

OPEN LOOP GAIN

FREQUENCY (Hz)

The output amplifier terminal is also used to compensate the
system for ac stability. The frequency response and phase
shift curves are shown in Figure 7. The uncompensated
amplifier has a single pole at approximately 250Hz and a
unity gain cross-over at 3MHz.

Since most output filter designs introduce one or more
additional poles at a lower frequency, the best network to
stabilize the system is a series RC combination at terminal9
to ground. This network should be designed to introduce a
zero to cancel out one of the output filter poles. A good start-
ing point to determine the external poles is a 1000-pF
capacitor and a variable series 50-K

potentiometer from

terminal 9 to ground. The compensation point is also a
convenient place to insert any programming signal to
override the error amplifier. internal shutdown and current
limiting are also connected at terminal 9. Any external circuit
that can sink 200

A can pull this point to ground and shut off

both output drivers.

While feedback is normally applied around the entire regula-
tor, the error amplifier can be used with conventional
operational amplifier feedback and will be stable in either the
inverting or non-inverting mode. Input common-mode limits
must be observed; if not, output signal inversion may result.
The internal 5V reference can be used for conventional regu-
lator applications if divided as shown in Figure 8. If the error
amplifier is connected as a unity gain amplifier, a fixed duty
cycle application results.

FIGURE 7. TYPICAL DUTY CYCLE AS A FUNCTION OF

COMPARATOR VOLTAGE (AT TERMINAL 9).

FIGURE 8. TYPICAL OUTPUT SATURATION VOLTAGE AS A

FUNCTION OF AMBIENT TEMPERATURE.

OUTPUT DUTY CYCLE (%)

COMPARATOR VOLTAGE (V)

0.4 0.8 1.2 1.6

2.4 2.8 3.2 3.6

= +25

V+ = 20V

= 2700pF

= 6.19k

OSC

= 60kHz

=1000pF

= 5k

OSC

= 20kHz

1.1

1.0

0.9

0.8

0.7

-75 -50 -25

75 100 125 150 175

OUTPUT SA

TURA

TION V

GE (V)

AMBIENT TEMPERATURE (

CA1524, CA2524, CA3524

Output Section

The CA1524 series outputs are two identical n-p-n
transistors with both collectors and emitters uncommitted.
Each output transistor has antisaturation circuitry that
enables a fast transient response for the wide range of
oscillator frequencies. Current limiting of the output section
is set at 100mA for each output and 100mA total if both
outputs are paralleled. Having both emitters and collectors
available provides the versatility to drive either n-p-n or p-n-p
external transistors. Curves of the output saturation voltage
as a function of temperature and output current are shown in
Figures 8 and 9, respectively. There are a number of output
configurations possible in the application of the CA1524 to
voltage regulator circuits which fall into three basic
classifications:

1. Capacitor-diode coupled voltage multipliers

2. Inductor-capacitor single-ended circuits

3. Transformer-coupled circuits

FIGURE 9. TYPICAL OUTPUT SATURATION VOLTAGE AS A

FUNCTION OF OUTPUT CURRENT

Device Application Suggestions

For higher currents, the circuit of Figure 10 may be used with
an external p-n-p transistor and bias resistor. The internal
regulator may be bypassed for operation from a fixed 5V
supply by connecting both terminals 15 and 16 to the input
voltage, which must not exceed 6V.

FIGURE 10. CIRCUIT FOR EXPANDING THE REFERENCE

CURRENT CAPABILITY

The internal 5V reference can be used for conventional regu-
lator applications if divided as shown in Figure 11. If the error
amplifier is connected as a unity gain amplifier, a fixed duty
cycle application results.

FIGURE 11. ERROR AMPLIFIER BIASING CIRCUITS

FIGURE 12. CIRCUIT TO ALLOW EXTERNAL BYPASS OF THE

REFERENCE REGULATION

To provide an expansion of the dead time without loading the
oscillator, the circuit of Figure 13 may be used.

FIGURE 13. CIRCUIT FOR EXPANSION OF DEAD TIME, WITH-

OUT USING A CAPACITOR ON PIN 3 OR WHEN A
LOW VALUE OSCILLATOR CAPACITOR IS USED

OUTPUT SA

TURA

TION V

GE (V)

2.0

1.5

1.0

0.5

100

OUTPUT CURRENT, I

(mA)

= +25

V+ = 8V to 40V

CA1524

REFERENCE

SECTION

V+

TO I

DEPENDING
ON CHOICE
FOR Q1

GND

100

REF

GND

NEGATIVE
OUTPUT
VOLTAGES

POSITIVE
OUTPUT
VOLTAGES

2.5V (R1 + R2)

R1R2

R1 + R2

= 2.5KW

CA1524

REFERENCE

SECTION

V+ CANNOT
EXCEED 6V

REF

NOTE: V+ Should Be in the 5V Range

And Must Not Exceed 6V

CA1524, CA2524, CA3524

FIGURE 14. FOLDBACK CURRENT-LIMITING CIRCUIT USED

REDUCE

POWER

DISSIPATION

UNDER

SHORTED OUTPUT CONDITIONS

FIGURE 15. CAPACITOR-DIODE COUPLED VOLTAGE

MULTIPLIER OUTPUT STAGES

FIGURE 16. SINGLE-ENDED INDUCTOR CIRCUITS WHERE THE

TWO OUTPUTS OF THE 1524 ARE CONNECTED IN
PARALLEL

FIGURE 17. TRANSFORMER-COUPLED OUTPUTS

//S

SENSE

= 5V

MAX

R1 + R2

(

)

WHERE

= 200mV

V+

V+ > V

V+ < V

| V+ | > | V

-V

NOTE: Diode D1 Is Necessary To Prevent Reverse

Emitter-Base Breakdown of Transistor Switch S

V+

-V

| V+ | < | V

V+ < V

V+ > V

TABLE 1. INPUT vs. OUTPUT VOLTAGE, AND FEEDBACK

RESISTOR VALUES FOR I

= 40mA (FOR CAPACI-

TOR-DIODE OUTPUT CIRCUIT IN FIGURE 18)

(V)

)

V+ (Min.) (V)

-0.5

-2.5

-3

-4

-5

-6

-7

-8

-9

-10

-11

-12

-13

-14

-15

-16

-17

-18

-19

-20

A-B

V+

PUSH-PULL

FLYBACK

FULL BRIDGE

V+

CAN BE S

CAN DRIVEQ1

CAN BE S

CAN DRIVEQ2

CA1524, CA2524, CA3524

Applications

(Note 1)

A capacitor-diode output filter is used in Figure 19 to convert
+15V

to -5V

at output currents up to 50mA. Since the

output transistors have built-in current limiting, no additional
current limiting is needed. Table 1 gives the required
minimum input voltage and feedback resistor values, R2, for
an output voltage.

Capacitor-Diode Output Circuit

A capacitor-diode output filter is used in Figure18 to convert
+15V

to -5V

at output currents up to 50mA. Since the

output transistors have built-in current limiting, no additional
current limiting is needed. Table 1 gives the required
minimum input voltage and feedback resistor values, R2, for
an output voltage range of -0.5V to -20V with an output
current of 40mA.

Single-Ended Switching Regulator

The CA1524 in the circuit of Figure 19 has both output
stages connected in parallel to produce an effective 0% -
90% duty cycle. Transistor Q1 is pulsed on and off by these
output stages. Regulation is achieved from the feedback
provided by R1 and R2 to the error amplifier which adjusts
the on-time of the output transistors according to the load
current being drawn. Various output voltages can be
obtained by adjusting R1 and R2. The use of an output
inductor requires an R-C phase compensation network to
stabilize the system. Current limiting is set at 1.9 amperes by
the sense resistor R3.

NOTE:

1. For additional information on the application of this device and a

further explanation of the circuits below, see Intersil Application
Note AN6915 "Application of the CA1524 series PWM lC".

FIGURE 18. CAPACITOR-DIODE OUTPUT CIRCUIT

FIGURE 19. SINGLE-ENDED LC SWITCHING REGULATOR CIRCUIT

CA3524

+15V

V+

0.1

R1
5K

0.01

R2
15K

IN4001

-5V
20mA

R1 = 5K

R2 =

R1 ( | V

| + 2.5)

REF

- 2.5)

CA3524

+28V

V+

0.1

0.02

0.001

RURD410

V-

50K

0.1

500

0.9mH

2N6388

+5V IA

R1
5K

CA1524, CA2524, CA3524

Flyback Converter

Figure 20 shows a flyback converter circuit for generating a
dual 15V output at 20mA from a 5V regulated line.
Reference voltage is provided by the input and the internal
reference generator is unused. Current limiting in this circuit
is accomplished by sensing current in the primary line and
resetting the soft-start circuit.

Push-Pull Converter

The output stages of the CA1524 provide the drive for
transistors Q1 and Q2 in the push-pull application of Figure
21. Since the internal flip-flop divides the oscillator frequency
by two, the oscillator must be set at twice the output
frequency. Current limiting for this circuit is done in the
primary of transformer T1 so that the pulse width will be
reduced if transformer saturation should occur.

Low-Frequency Pulse Generator

Figure 22 shows the CA1524 being used as a low-frequency
pulse generator. Since all components (error amplifier,
oscillator, oscillator reference regulator, output transistor
drivers) are on the lC, a regulated 5-V (or 2.5-V) pulse of 0%
- 45% (or 0% - 90%) on time is possible over a frequency
range of 150 to 500Hz. Switch S1 is used to go from a 5-V
output pulse (S1 closed) to a 2.5-V output pulse (S1 open)
with a duty cycle range of 0% to 45%. The output frequency
will be roughly half of the oscillator frequency when the
output transistors are not connected in parallel (75Hz to
250Hz, respectively). Switch S2 will allow both output stages
to be paralleled for an effective duty cycle of 0%-90% with
the output frequency range from 150 to 500Hz. The
frequency is adjusted by R1; R2 controls duty cycle.

FIGURE 20. FLYBACK CONVERTER CIRCUIT

FIGURE 21. PUSH-PULL TRANSFORMER-COUPLED CONVERTER

CA3524

+5V

V+

25K

100

0.02

0.001

620

300

RURD620

4.7

510

+15V

-15V

50T

20T

200

0.1

2N6290

CORE: FEROX CUBE
2213P - A250 - 387
OR EQUIVALENT

2N2102

IN914

RURD620

+28V

V+

0.1

20K

1500

0.01

0.001

100

0.1

20T

5V
5A

1mH

2N6292

RURD620

CA1524, CA2524, CA3524

The Variable Switcher

The circuit diagram of the CA1524, used as a variable output
voltage power supply is shown in Figure 23. By connecting
the two output transistors in parallel, the duty cycle is
doubled, i.e., 0% - 90%. As the reference voltage level is

varied, the feedback voltage will track that level and cause
the output voltage to change according to the change in
reference voltage.

FIGURE 22. LOW-FREQUENCY PULSE GENERATOR

TO PIN 9

REFERENCE

R1
50K

20K

FREQUENCY

ADJUSTMENT

0.1

SILVER

MICA

10K

DUTY CYCLE
ADJUSTMENT

= 9V

1.5K

CA3524

OUTPUT 1A

OUTPUT 2A

1.1K

TO PIN 12

OUTPUT 1

TO PIN 1

TO PIN 13

OUTPUT 2

SWITCH

OUTPUT

PULSES

DUTY

CYCLE

0V - 5V

0% - 45%

0% - 90%

FIGURE 23. THE CA1524 USED AS A 0-5A, 7-30 V LABORATORY SUPPLY

20mH

5100

100V

D1-D4 - A15A

R1
1K

2N6385

(PNP DARLINGTON)

R2
1.5
10W

0.01

10000

100V

BIFILAR

WINDING

50mH

OUT

0.1

7V - 30V
0A - 3A

RETURN

C5
25

NON-POLAR

C6
25

NON-POLAR

R10
16K

C11

0.01

C10
1100pF

SILVER
MICA

C9
3300
pF
1%

15K

C8
0.1

R8
2K

10K

R6
2K

R4
5K

R5
2K

10K

0.1

CA1524

VOLTAGE
CONTROL

OSC

= 20KHz

RURD410

CA1524, CA2524, CA3524

Digital Readout Scale

The CA1524 can be used as the driving source for an
electronic scale application. The circuit shown in Figures 24
and 25 uses half (Q2) of the CA1524 output in a low-voltage
switching regulator (2.2V) application to drive the LED's
displaying the weight. The remaining output stage (Q1) is
used as a driver for the sampling plates PL1 and PL2. Since
the CA1524 contains a 5V internal regulator and a wide
operating range of 8V to 40V, a single 9V battery can power
the total system. The two plates, PL1 and PL2, are driven
with opposite phase signals (frequency held constant but
duty cycle may change) from the pulse-width modulator lC
(CA1524). The sensor, S, is located between the two plates.
Plates PL1, S and PL2 form an effective capacitance bridge-
type divider network. As plate S is moved according to the

object's weight, a change in capacitance is noted between
PL1, S and PL2. This change is reflected as a voltage to the
ac amplifier (CA3160). At the null position the signals from
PL1 and PL2 as detected by S are equal in amplitude, but
opposite in phase. As S is driven by the scale mechanism
down toward PL2, the signal at S becomes greater. The
CA3160 ac amplifier provides a buffer for the small signal
change noted at S. The output of the CA3160 is converted to
a dc voltage by a peak-to-peak detector. A peak-to-peak
detector is needed, since the duty cycle of the sampled
waveform is subject to change. The detector output is filtered
further and displayed via the CA3161E and CA3162E digital
readout system, indicating the weight on the scale.

FIGURE 24. BASIC DIGITAL READOUT SCALE

FIGURE 25. SCHEMATIC DIAGRAM OF DIGITAL READOUT SCALE (CONT'D)

OSCILLATOR

20KHz

(PART OF CA1524)

PL1

PL2

AC
AMP

CA3130

COUPLED TO
MECHANICAL

SCALE MECHANISM

PEAK TO PEAK

DETECTOR

LOW PASS

FILTER

DISPLAY DRIVE

(PART OF CA1524)

DIGITAL METER

AND DISPLAY

FULL SCALE

NO WEIGHT

VOLTAGE

CA3161E

CA3162E

MSD

NSD

LSD

+5V

COMMON-
ANODE LED
DISPLAYS

POWER 2N2907
OR EQUIVALENT

BCD

OUTPUTS

DIGIT

DRIVERS

12 14

0.1

10K

0.27

ZERO

ADJUSTMENT

50K

2.5V

HIGH

LOW

INPUTS:

GAIN

ADJUSTMENT

(NOTE 1)

NOTE:

1. FAIRCHILD FND507 OR EQUIVALENT

CA1524, CA2524, CA3524

FIGURE 26. SCHEMATIC DIAGRAM OF DIGITAL READOUT SCALE

DIMENSIONS AND PAD LAYOUT FOR CA3524RH CHIP

PL1

PL2

30K

39K

430K

100
M

22M

CA3160

200pF

10K

100

68K

6.2K

10K

0.1

910K

0.47

300K

2.5V

22M

13 12 11 10

4.7K

200

2N4037

TO SCALE

MECHANISM

125

470

CA1524

24K

0.01

4.7K

6.2K

4700pF

4.7K

NOTE: Dimensions in parentheses are in millimeters and are de-
rived from the basic inch dimensions as indicated. Grid graduations
are in mils (10

-3

inch). The layout represents a chip when it is part of

the wafer. When the wafer is cut into chips, the cleavage angles are
57

instead of 90

with respect to the face of the chip. Therefore, the

isolated chip is actually 7 mils (0.17mm) larger in both dimensions.

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli-
able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

File Number

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