7-798
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
CD4029BMS
CMOS Presettable Up/Down Counter
Description
CD4029BMS consists of a four-stage binary or BCD-decade up/
down counter with provisions for look-ahead carry in both count-
ing modes. The inputs consist of a single CLOCK, CARRY-IN
(CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET
ENABLE, and four individual JAM signals. Q1, Q2, Q3, Q4 and a
CARRY OUT signal are provided as outputs.
A high PRESET ENABLE signal allows information on the JAM
INPUTS to preset the counter to any state asynchronously with
the clock. A low on each JAM line, when the PRESET-ENABLE
signal is high, resets the counter to its zero count. The counter is
advanced one count at the positive transition of the clock when
the CARRY-IN and PRE-SET ENABLE signals are low.
Advancement is inhibited when the CARRY-IN or PRESET
ENABLE signals are high. The CARRY-OUT signal is normally
high and goes low when the counter reaches its maximum count
in the UP mode or the minimum count in the DOWN mode pro-
vided the CARRY-IN signal is low. The CARRY-IN signal in the
low state can thus be considered a CLOCK ENABLE. The
CARRY-IN terminal must be connected to VSS when not in use.
Binary counting is accomplished when the BINARY/DECADE
input is high; the counter counts in the decade mode when the
BINARY/DECADE input is low. The counter counts up when the
UP/DOWN input is high, and down when the UP/DOWN input is
low. Multiple packages can be connected in either a parallel-
clocking or a ripple-clocking arrangement as shown in Figure 17.
Parallel clocking provides synchronous control and hence faster
response from all counting outputs. Ripple-clocking allows for
longer clock input rise and fall times.
The CD4029BMS is supplied in these 16-lead outline packages:
Braze Seal DIP
H4X
Frit Seal DIP
H1F
Ceramic Flatpack H6W
Features
High-Voltage Type (20V Rating)
Medium Speed Operation: 8MHz (Typ.) at CL = 50pF
and VDD - VSS = 10V
Multi-Package Parallel Clocking for Synchronous High
Speed Output Response or Ripple Clocking for Slow
Clock Input Rise and Fall Times
"Preset Enable" and Individual "Jam" Inputs Provided
Binary or Decade Up/Down Counting
BCD Outputs in Decade Mode
100% Tested for Maximum Quiescent Current at 20V
5V, 10V and 15V Parametric Ratings
Standardized Symmetrical Output Characteristics
Maximum Input Current of 1
A at 18V Over Full Pack-
age-Temperature Range; 100nA at 18V and +25
o
C
Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
Meets All Requirements of JEDEC Tentative Stan-
dards No. 13B, "Standard Specifications for Descrip-
tion of "B" Series CMOS Device's
Applications
Programmable Binary and Decade Counting/Fre-
quency Synthesizers-BCD Output
Analog to Digital and Digital to Analog Conversion
Up/Down Binary Counting
Difference Counting
Magnitude and Sign Generation
Up/Down Decade Counting
December 1992
File Number
3304
Pinout
CD4029BMS
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
PRESET ENABLE
Q4
JAM 4
JAM 1
CARRY IN
Q1
VSS
CARRY OUT
VDD
Q3
JAM 3
JAM 2
Q2
UP/DOWN
BINARY/DECADE
CLOCK
Functional Diagram
13
12
16
PRESET
ENABLE
1
4
3
1
2
3
4
JAM INPUTS
VDD
CARRY IN
(CLOCK
ENABLE)
5
9
10
15
BINARY/
DECADE
UP/DOWN
CLOCK
8
VSS
7
2
14
11
6 Q1
Q2
Q3
Q4
CARRY
OUT
BUFFERED
OUTPUTS
7-799
Specifications CD4029BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input
. . . . . . . . . . . . . . . . . . . . . . . .
10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265
o
C
At Distance 1/16
1/32 Inch (1.59mm
0.79mm) from case for
10s Maximum
Thermal Resistance . . . . . . . . . . . . . . . .
ja
jc
Ceramic DIP and FRIT Package . . . . .
80
o
C/W
20
o
C/W
Flatpack Package . . . . . . . . . . . . . . . .
70
o
C/W
20
o
C/W
Maximum Package Power Dissipation (PD) at +125
o
C
For TA = -55
o
C to +100
o
C (Package Type D, F, K) . . . . . . 500mW
For TA = +100
o
C to +125
o
C (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/
o
C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS (NOTE 1)
GROUP A
SUBGROUPS
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Supply Current
IDD
VDD = 20V, VIN = VDD or GND
1
+25
o
C
-
10
A
2
+125
o
C
-
1000
A
VDD = 18V, VIN = VDD or GND
3
-55
o
C
-
10
A
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20
1
+25
o
C
-100
-
nA
2
+125
o
C
-1000
-
nA
VDD = 18V
3
-55
o
C
-100
-
nA
Input Leakage Current
IIH
VIN = VDD or GND
VDD = 20
1
+25
o
C
-
100
nA
2
+125
o
C
-
1000
nA
VDD = 18V
3
-55
o
C
-
100
nA
Output Voltage
VOL15
VDD = 15V, No Load
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
-
50
mV
Output Voltage
VOH15
VDD = 15V, No Load (Note 3)
1, 2, 3
+25
o
C, +125
o
C, -55
o
C 14.95
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1
+25
o
C
0.53
-
mA
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1
+25
o
C
1.4
-
mA
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1
+25
o
C
3.5
-
mA
Output Current (Source)
IOH5A
VDD = 5V, VOUT = 4.6V
1
+25
o
C
-
-0.53
mA
Output Current (Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1
+25
o
C
-
-1.8
mA
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1
+25
o
C
-
-1.4
mA
Output Current (Source)
IOH15
VDD = 15V, VOUT = 13.5V
1
+25
o
C
-
-3.5
mA
N Threshold Voltage
VNTH
VDD = 10V, ISS = -10
A
1
+25
o
C
-2.8
-0.7
V
P Threshold Voltage
VPTH
VSS = 0V, IDD = 10
A
1
+25
o
C
0.7
2.8
V
Functional
F
VDD = 2.8V, VIN = VDD or GND
7
+25
o
C
VOH >
VDD/2
VOL <
VDD/2
V
VDD = 20V, VIN = VDD or GND
7
+25
o
C
VDD = 18V, VIN = VDD or GND
8A
+125
o
C
VDD = 3V, VIN = VDD or GND
8B
-55
o
C
Input Voltage Low
(Note 2)
VIL
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
-
1.5
V
Input Voltage High
(Note 2)
VIH
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
3.5
-
V
Input Voltage Low
(Note 2)
VIL
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
-
4
V
Input Voltage High
(Note 2)
VIH
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
11
-
V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
7-800
Specifications CD4029BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS (NOTE 1, 2)
GROUP A
SUBGROUPS
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Propagation Delay
Clock To Q Output
TPHL1
TPLH1
VDD = 5V, VIN = VDD or GND
9
+25
o
C
-
500
ns
10, 11
+125
o
C, -55
o
C
-
675
ns
Propagation Delay
Clock To Carry Out
TPHL2
TPLH2
VDD = 5V, VIN = VDD or GND
9
+25
o
C
-
560
ns
10, 11
+125
o
C, -55
o
C
-
756
ns
Propagation Delay
Preset Enable To Q
TPHL3
TPLH3
VDD = 5V, VIN = VDD or GND
9
+25
o
C
-
470
ns
10, 11
+125
o
C, -55
o
C
-
635
ns
Propagation Delay
Preset Enable To Carry-
Out
TPHL4
TPLH4
VDD = 5V, VIN = VDD or GND
9
+25
o
C
-
640
ns
10, 11
+125
o
C, -55
o
C
-
864
ns
Propagation Delay
Carry-In To
Carry-Out
TPHL5
TPLH5
VDD = 5V, VIN = VDD or GND
9
+25
o
C
-
340
ns
10, 11
+125
o
C, -55
o
C
-
459
ns
Transition Time
Q Output
TTHL
TTLH
VDD = 5V, VIN = VDD or GND
9
+25
o
C
-
200
ns
10, 11
+125
o
C, -55
o
C
-
270
ns
Maximum Clock Input
Frequency
FCL
VDD = 5V, VIN = VDD or GND
9
+25
o
C
2
-
MHz
10, 11
+125
o
C, -55
o
C
1.48
-
MHz
NOTES:
1. VDD = 5V, CL = 50pF, RL = 200K
2. -55
o
C and +125
o
C limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Supply Current
IDD
VDD = 5V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
-
5
A
+125
o
C
-
150
A
VDD = 10V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
-
10
A
+125
o
C
-
300
A
VDD = 15V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
-
10
A
+125
o
C
-
600
A
Output Voltage
VOL
VDD = 5V, No Load
1, 2
+25
o
C, +125
o
C,
-55
o
C
-
50
mV
Output Voltage
VOL
VDD = 10V, No Load
1, 2
+25
o
C, +125
o
C,
-55
o
C
-
50
mV
Output Voltage
VOH
VDD = 5V, No Load
1, 2
+25
o
C, +125
o
C,
-55
o
C
4.95
-
V
Output Voltage
VOH
VDD = 10V, No Load
1, 2
+25
o
C, +125
o
C,
-55
o
C
9.95
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1, 2
+125
o
C
0.36
-
mA
-55
o
C
0.64
-
mA
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1, 2
+125
o
C
0.9
-
mA
-55
o
C
1.6
-
mA
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1, 2
+125
o
C
2.4
-
mA
-55
o
C
4.2
-
mA
Output Current (Source)
IOH5A
VDD = 5V, VOUT = 4.6V
1, 2
+125
o
C
-
-0.36
mA
-55
o
C
-
-0.64
mA
7-801
Specifications CD4029BMS
Output Current (Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1, 2
+125
o
C
-
-1.15
mA
-55
o
C
-
-2.0
mA
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1, 2
+125
o
C
-
-0.9
mA
-55
o
C
-
-2.6
mA
Output Current (Source)
IOH15
VDD =15V, VOUT = 13.5V
1, 2
+125
o
C
-
-2.4
mA
-55
o
C
-
-4.2
mA
Input Voltage Low
VIL
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25
o
C, +125
o
C,
-55
o
C
-
3
V
Input Voltage High
VIH
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25
o
C, +125
o
C,
-55
o
C
7
-
V
Propagation Delay
Q Output
TPHL1
TPLH1
VDD = 10V
1, 2, 3
+25
o
C
-
240
ns
VDD = 15V
1, 2, 3
+25
o
C
-
180
ns
Propagation Delay
Carry Output
TPHL2
TPLH2
VDD = 10V
1, 2, 3
+25
o
C
-
260
ns
VDD = 15V
1, 2, 3
+25
o
C
-
190
ns
Propagation Delay
Preset Enable To Q
TPHL3
TPLH3
VDD = 10V
1, 2, 3
+25
o
C
-
200
ns
VDD = 15V
1, 2, 3
+25
o
C
-
160
ns
Propagation Delay
Preset Enable To Carry-
Out
TPHL4
TPLH4
VDD = 10V
1, 2, 3
+25
o
C
-
290
ns
VDD = 15V
1, 2, 3
+25
o
C
-
210
ns
Propagation Delay
Carry In To Carry Out
TPHL5
TPLH5
VDD = 10V
1, 2, 3
+25
o
C
-
140
ns
VDD = 15V
1, 2, 3
+25
o
C
-
100
ns
Transition Time
TTHL
TTLH
VDD = 10V
1, 2, 3
+25
o
C
-
100
ns
VDD = 15V
1, 2, 3
+25
o
C
-
80
ns
Maximum Clock Input
Frequency
FCL
VDD = 10V
1, 2, 3
+25
o
C
4
-
MHz
VDD = 15V
1, 2, 3
+25
o
C
5.5
-
MHz
Minimum Data Setup
Time
Note 4
TS
VDD = 5V
1, 2, 3
+25
o
C
-
340
ns
VDD = 10V
1, 2, 3
+25
o
C
-
140
ns
VDD = 15V
1, 2, 3
+25
o
C
-
100
ns
Clock Rise And Fall Time
Note 5
TRCL
TFCL
VDD = 5V
1, 2, 3
+25
o
C
-
15
s
VDD = 10V
1, 2, 3
+25
o
C
-
15
s
VDD = 15V
1, 2, 3
+25
o
C
-
15
s
Minimum Clock Pulse
Width
TW
VDD = 5V
1, 2, 3
+25
o
C
-
180
ns
VDD = 10V
1, 2, 3
+25
o
C
-
90
ns
VDD = 15V
1, 2, 3
+25
o
C
-
60
ns
Minimum Carry In Setup
Time
Note 6
TS
VDD = 5V
1, 2, 3
+25
o
C
-
200
ns
VDD = 10V
1, 2, 3
+25
o
C
-
70
ns
VDD = 15V
1, 2, 3
+25
o
C
-
60
ns
Minimum Carry Input
Hold Time
Note 6
TH
VDD = 5V
1, 2, 3
+25
o
C
-
50
ns
VDD = 10V
1, 2, 3
+25
o
C
-
30
ns
VDD = 15V
1, 2, 3
+25
o
C
-
25
ns
Minimum Preset Enable
Removal Time
Note 4
TREM
VDD = 5V
1, 2, 3
+25
o
C
-
200
ns
VDD = 10V
1, 2, 3
+25
o
C
-
110
ns
VDD = 15V
1, 2, 3
+25
o
C
-
80
ns
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
(Continued)
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
LIMITS
UNITS
MIN
MAX
7-802
Specifications CD4029BMS
Minimum Preset Enable
Pulse Width
TW
VDD = 5V
1, 2, 3
+25
o
C
-
130
ns
VDD = 10V
1, 2, 3
+25
o
C
-
70
ns
VDD = 15V
1, 2, 3
+25
o
C
-
50
ns
Input Capacitance
CIN
Any Input
1, 2
+25
o
C
-
7.5
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. From Up/Down, Binary/Decode, Carry In, or Preset Enable Control Inputs to Clock Edge.
5. If more than one unit is cascaded in the parallel clocked application, tr CL should be made
the sum of the fixed propagation delay at
15pF and the transition time of the carry output driving stage for the estimated capacitive load. This measurement was made with a de-
coupling capacitor (>1
F) between VDD and VSS.
6. From Carry In to Clock Edge.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Supply Current
IDD
VDD = 20V, VIN = VDD or GND
1, 4
+25
o
C
-
25
A
N Threshold Voltage
VNTH
VDD = 10V, ISS = -10
A
1, 4
+25
o
C
-2.8
-0.2
V
N Threshold Voltage
Delta
VTN
VDD = 10V, ISS = -10
A
1, 4
+25
o
C
-
1
V
P Threshold Voltage
VTP
VSS = 0V, IDD = 10
A
1, 4
+25
o
C
0.2
2.8
V
P Threshold Voltage
Delta
VTP
VSS = 0V, IDD = 10
A
1, 4
+25
o
C
-
1
V
Functional
F
VDD = 18V, VIN = VDD or GND
1
+25
o
C
VOH >
VDD/2
VOL <
VDD/2
V
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
TPHL
TPLH
VDD = 5V
1, 2, 3, 4
+25
o
C
-
1.35 x
+25
o
C
Limit
ns
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns
3. See Table 2 for +25
o
C limit.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25
O
C
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-2
IDD
1.0
A
Output Current (Sink)
IOL5
20% x Pre-Test Reading
Output Current (Source)
IOH5A
20% x Pre-Test Reading
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
(Continued)
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
LIMITS
UNITS
MIN
MAX
7-803
Specifications CD4029BMS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
READ AND RECORD
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS
MIL-STD-883
METHOD
TEST
READ AND RECORD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
Group E Subgroup 2
5005
1, 7, 9
Table 4
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
FUNCTION
OPEN
GROUND
VDD
9V
-0.5V
OSCILLATOR
50kHz
25kHz
Static Burn-In 1
Note 1
2, 6, 7, 11, 14
1, 3 - 5, 8 - 10, 12,
13, 15
16
Static Burn-In 2
Note 1
2, 6, 7, 11, 14
8
1, 3 - 5, 9, 10, 12,
13, 15, 16
Dynamic Burn-
In Note 1
-
1, 3 - 5, 8, 12, 13
9, 10, 16
2, 6, 7, 11, 14
15
-
Irradiation
Note 2
2, 6, 7, 11, 14
8
1, 3 - 5, 9, 10, 12,
13, 15, 16
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K
5%, VDD = 18V
0.5V
2. Each pin except VDD and GND will have a series resistor of 47K
5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V
0.5V
7-804
FIGURE 1.
2
BINARY/
DECADE
9
PRESET
ENABLE
1
PE
J
TE2 Q2
F/F2
Q2
PE
J
TE3 Q3
F/F3
Q3
PE
J
TE4 Q4
F/F4
Q4
5
10
15
6
4
12
14
13
3
7
PE
J
TE1 Q1
F/F1
Q1
CARRY
OUT
Q4
J4
*
CL
Q3
CL
*
11
Q2
CL
CL
*
*
*
*
*
J3
J2
J1
Q2
CLOCK
UP/DOWN
CLOCK
ENABLE
CARRY IN
*
*
VDD
VSS
*
ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
PE
J
TE
Q
Q
TRUTH TABLE
FUNCTION TABLE
CLOCK
TE
PE
J
Q
Q
CONTROL
INPUT
LOGIC
LEVEL
ACTION
X
X
0
0
0
1
BIN/DEC
(B/D)
1
0
Binary Count
Decade Count
0
1
X
Q
Q
UP/DOWN
(U/D)
1
0
Up Count
Down Count
X
X
0
1
1
0
Preset Enable
(PE)
1
0
Jam In
No Jam
1
1
X
Q
Q
NC
CARRY IN (CI)
(CLOCK ENABLE)
1
0
No Counter Advance at
POS Clock Transition
Advance Counter at
POS Clock Transition
X
1
X
Q
Q
NC
X = Don't Care
CD4029BMS
Logic Diagram
7-805
CD4029BMS
Typical Performance Characteristics
FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
FIGURE 6. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE
FIGURE 7. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF LOAD CAPACITANCE (Q OUTPUT)
10V
5V
AMBIENT TEMPERATURE (T
A
) = +25
o
C
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
0
5
10
15
15
10
5
20
25
30
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
AMBIENT TEMPERATURE (T
A
) = +25
o
C
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
10V
5V
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
15
12.5
10
7.5
5
2.5
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-10V
-15V
AMBIENT TEMPERATURE (T
A
) = +25
o
C
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
0
-5
-10
-15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-20
-25
-30
0
-5
-10
-15
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
-10V
-15V
AMBIENT TEMPERATURE (T
A
) = +25
o
C
0
-5
-10
-15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
0
-5
-10
-15
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
AMBIENT TEMPERATURE (T
A
) = +25
o
C
LOAD CAPACITANCE (CL) (pF)
0
40
60
80
100
20
0
50
100
150
200
SUPPLY VOLTAGE (VDD) = 5V
10V
15V
TRANSITION TIME (tTHL, tTLH) (ns)
AMBIENT TEMPERATURE (T
A
) = +25
o
C
10V
15V
SUPPLY VOLTAGE (VDD) = 5V
PROP
AGA
TION DELA
Y TIME (tPHL, tPLH) (ns)
300
200
100
0
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
7-806
CD4029BMS
Typical Performance Characteristics
(Continued)
Timing Diagrams
FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF LOAD CAPACITANCE (CARRY
OUTPUT)
FIGURE 9. TYPICAL POWER DISSIPATION AS A FUNCTION
OF FREQUENCY
AMBIENT TEMPERATURE (T
A
) = +25
o
C
SUPPLY VOLTAGE (VDD) = 5V
10V
15V
PROP
AGA
TION DELA
Y TIME (t
PHL
, t
PLH
) (ns)
300
200
100
0
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
1
10
10
2
10
3
10
4
2
4 6 8
2
4 6 8
2
4 6 8
2
4 6 8
2
4
6
8
10
10
3
10
4
10
5
10
2
CLOCKFREQUENCY (fCL) (kHz)
POWER DISSIP
A
TION (PD) (
W)
2
4 6 8
2
4
6
8
2
4
6
8
2
4
6
8
CL = 50pF
CL = 15pF
SUPPLY VOLTAGE (VDD) = 15V
AMBIENT TEMPERATURE (T
A
) = +25
o
C
10V
10V
5V
CARRY IN
(CL ENABLE)
UP/DOWN
BINARY/
PRESET
ENABLE
J1
J2
J3
J4
Q1
Q2
Q3
Q4
CARRY OUT
COUNT
5
6
7
8
9 10 11 12 13 14 15 9
8
7
6
5
4
3
2
1
0
0
15
DECADE
CLOCK (CL)
The CD4029BMS CLOCK and UP/DOWN inputs are used
directly in most applications. In applications where CLOCK
UP and CLOCK DOWN inputs are provided, conversion to
the CD4029BMS CLOCK and UP/DOWN inputs can easily
be realized by use of the circuit in Figure 11.
CD4029BMS changes count on positive transitions of
CLOCK UP or CLOCK DOWN inputs. For the gate configu-
ration in Figure 12, when counting up the CLOCK DOWN
input must be maintained high and conversely when count-
ing down the CLOCK UP input must be maintained high.
FIGURE 11. CONVERSION OF CLOCK UP, CLOCK DOWN
INPUT SIGNALS TO CLOCK AND UP/DOWN
INPUT SIGNALS
"UP/DOWN"
"CLOCK"
VDD
1 CD4011
QUAD 2 INPUT NAND GATE
"CLOCK UP"
"CLOCK
DOWN"
807
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Timing Diagrams
(Continued)
FIGURE 12. TIMING DIAGRAM-DECADE MODE
FIGURE 13. CASCADING COUNTER PACKAGES
0
1
2
3
4
5
6
7
8
9
8
7
6
5
4
3
2
1
0
0
9
8
7
CLOCK (CL)
CARRY IN
(CL ENABLE)
UP/DOWN
BINARY/
PRESET
ENABLE
J1
J2
J3
J4
Q1
Q2
Q3
Q4
CARRY OUT
COUNT
DECADE
*
CARRY OUT LINES AT THE 2ND, 3RD, ETC, STAGES MAY HAVE A NEG-
ATIVE-GOING GLITCH PULSE RESULTING FROM DIFFERENTIAL
DELAYS OF DIFFERENT CD4029BMS IC'S. THESE NEGATIVE GOING
GLITCHES DO NOT AFFECT PROPER CD4029BMS OPERATION. HOW-
EVER, IF THE CARRY OUT SIGNALS ARE USED TO TRIGGER OTHER
EDGE-SENSITIVE LOGIC DEVICES, SUCH AS FF'S OR COUNTERS, THE
CARRY OUT SIGNALS SHOULD BE GATED WITH THE CLOCK SIGNAL
USING A 2-INPUT OR GATE SUCH AS CD4071BMS.
UP/D
B/D
PE
CL Q1 Q2 Q3 Q4
CI
CO
J1 J2 J3 J4
CD4029
UP/D
B/D
PE
CL Q1 Q2 Q3 Q4
CI
CO
J1 J2 J3 J4
CD4029
UP/D
B/D
PE
CL Q1 Q2 Q3 Q4
CI
CO
J1 J2 J3 J4
CD4029
*
UP/DOWN
PRESET
ENABLE
CLOCK
BINARY/
DECADE
"PARALLEL CLOCKING"
CD4029BMS
7-808
CD4029BMS
Timing Diagrams
(Continued)
FIGURE 13. CASCADING COUNTER PACKAGES
(Continued)
Chip Dimensions and Pad Layout
RIPPLE CLOCKING MODE:
THE UP/DOWN CONTROL CAN BE CHANGED AT ANY COUNT. THE ONLY
RESTRICTION ON CHANGING THE UP/DOWN CONTROL IS THAT THE CLOCK
INPUT TO THE FIRST COUNTING STAGE MUST BE HIGH. FOR CASCADING
COUNTERS OPERATING IN A FIXED UP-COUNT OR DOWN-COUNT MODE,
THE OR GATES ARE NOT REQUIRED BETWEEN STAGES, AND CO IS CON-
NECTED DIRECTLY TO THE CL INPUT OF THE NEXT STAGE WITH CI
GROUNDED.
UP/D
B/D
PE
CL Q1 Q2 Q3 Q4
CI
CO
J1 J2 J3 J4
CD4029
UP/D
B/D
PE
CL Q1 Q2 Q3 Q4
CI
CO
J1 J2 J3 J4
CD4029
UP/D
B/D
PE
CL Q1 Q2 Q3 Q4
CI
CO
J1 J2 J3 J4
CD4029
UP/DOWN
PRESET
ENABLE
CLOCK
BINARY/
DECADE
1/4 CD4071B
1/4 CD4071B
"RIPPLE CLOCKING"
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10
-3
inch)
METALLIZATION:
Thickness: 11k
-
14k
, AL.
PASSIVATION:
10.4k - 15.6k
, Silane
BOND PADS:
0.004 inches X 0.004 inches MIN
DIE THICKNESS:
0.0198 inches - 0.0218 inches
PDF 
ZIP