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Электронный компонент: CD4042BMS

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7-868
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
CD4042BMS
CMOS Quad Clocked "D" Latch
Pinout
CD4042BMS
TOP VIEW
Functional Diagram
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
Q4
Q1
Q1
D1
CLOCK
POLARITY
VSS
D2
VDD
D4
D3
Q3
Q3
Q2
Q2
Q4
NC = NO CONNECTION
4
7
13
14
5
6
16
8
2
3
10
9
11
12
1
15
CL
D1
D2
D3
D4
CLOCK
POLARITY
VDD
VSS
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Features
High-Voltage Type (20V Rating)
Clock Polarity Control
Q and Q Outputs
Common Clock
Low Power TTL Compatible
Standardized Symmetrical Output Characteristics
100% Tested for Quiescent Current at 20V
Maximum Input Current of 1
A at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25
o
C
5V, 10V and 15V Parametric Ratings
Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
Meets All Requirements of JEDEC Tentative Standard
No. 13B, "Standard Specifications for Description of
`B' Series CMOS Devices"
Applications
Buffer Storage
Holding Register
General Digital Logic
Description
CD4042BMS types contain four latch circuits, each strobed by a
common clock. Complementary buffered outputs are available
from each circuit. The impedance of the n- and p- channel output
devices is balanced and all outputs are electrically identical.
Information present at the data input is transferred to outputs Q
and Q during the CLOCK level which is programmed by the
POLARITY input. For POLARITY = 0 the transfer occurs during
the 0 CLOCK level and for POLARITY = 1 the transfer occurs
during the 1 CLOCK level. The outputs follow the data input
defined above are present. When a CLOCK transition occurs
(positive for POLARITY = 0 and negative for POLARITY = 1) the
information present at the input during the CLOCK transition is
retained at the outputs until an opposite CLOCK transition
occurs.
The CD4042BMS is supplied in these 16 lead outline packages:
Braze Seal DIP
H4T
Frit Seal DIP
H1E
Ceramic Flatpack
H6W
December 1992
File Number
3310
7-869
Specifications CD4042BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input
. . . . . . . . . . . . . . . . . . . . . . . .
10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265
o
C
At Distance 1/16
1/32 Inch (1.59mm
0.79mm) from case for
10s Maximum
Thermal Resistance . . . . . . . . . . . . . . . .
ja
jc
Ceramic DIP Package . . . . . . . . . . . . .
80
o
C/W
20
o
C/W
Flatpack Package . . . . . . . . . . . . . . . .
70
o
C/W
20
o
C/W
Maximum Package Power Dissipation (PD) at +125
o
C
For TA = -55
o
C to +100
o
C (Package Type D, F, K) . . . . . . 500mW
For TA = +100
o
C to +125
o
C (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/
o
C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS (NOTE 1)
GROUP A
SUBGROUPS
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Supply Current
IDD
VDD = 20V, VIN = VDD or GND
1
+25
o
C
-
2
A
2
+125
o
C
-
200
A
VDD = 18V, VIN = VDD or GND
3
-55
o
C
-
2
A
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20
1
+25
o
C
-100
-
nA
2
+125
o
C
-1000
-
nA
VDD = 18V
3
-55
o
C
-100
-
nA
Input Leakage Current
IIH
VIN = VDD or GND
VDD = 20
1
+25
o
C
-
100
nA
2
+125
o
C
-
1000
nA
VDD = 18V
3
-55
o
C
-
100
nA
Output Voltage
VOL15
VDD = 15V, No Load
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
-
50
mV
Output Voltage
VOH15
VDD = 15V, No Load (Note 3)
1, 2, 3
+25
o
C, +125
o
C, -55
o
C 14.95
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1
+25
o
C
0.53
-
mA
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1
+25
o
C
1.4
-
mA
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1
+25
o
C
3.5
-
mA
Output Current (Source)
IOH5A
VDD = 5V, VOUT = 4.6V
1
+25
o
C
-
-0.53
mA
Output Current (Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1
+25
o
C
-
-1.8
mA
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1
+25
o
C
-
-1.4
mA
Output Current (Source)
IOH15
VDD = 15V, VOUT = 13.5V
1
+25
o
C
-
-3.5
mA
N Threshold Voltage
VNTH
VDD = 10V, ISS = -10
A
1
+25
o
C
-2.8
-0.7
V
P Threshold Voltage
VPTH
VSS = 0V, IDD = 10
A
1
+25
o
C
0.7
2.8
V
Functional
F
VDD = 2.8V, VIN = VDD or GND
7
+25
o
C
VOH >
VDD/2
VOL <
VDD/2
V
VDD = 20V, VIN = VDD or GND
7
+25
o
C
VDD = 18V, VIN = VDD or GND
8A
+125
o
C
VDD = 3V, VIN = VDD or GND
8B
-55
o
C
Input Voltage Low
(Note 2)
VIL
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
-
1.5
V
Input Voltage High
(Note 2)
VIH
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
3.5
-
V
Input Voltage Low
(Note 2)
VIL
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
-
4
V
Input Voltage High
(Note 2)
VIH
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
11
-
V
NOTES: 1. All voltages referenced to device GND.
2. Go/no go test with limits applied to inputs.
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
7-870
Specifications CD4042BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS (NOTES 1, 2)
GROUP A
SUBGROUPS
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Propagation Delay
(Note 2)
Data in to Q
TPHL1
TPLH1
VDD = 5V, VIN = VDD or GND
9
+25
o
C
-
220
ns
10, 11
+125
o
C, -55
o
C
-
297
ns
Propagation Delay
(Note 2)
Data in to Q
TPHL2
TPLH2
VDD = 5V, VIN = VDD or GND
9
+25
o
C
-
300
ns
10, 11
+125
o
C, -55
o
C
-
405
ns
Propagation Delay
(Note 2)
Clock to Q
TPHL3
TPLH3
VDD = 5V, VIN = VDD or GND
9
+25
o
C
-
450
ns
10, 11
+125
o
C, -55
o
C
-
608
ns
Propagation Delay
(Note 2)
Clock to Q
TPHL4
TPLH4
VDD = 5V, VIN = VDD or GND
9
+25
o
C
-
500
ns
10, 11
+125
o
C, -55
o
C
-
675
ns
Transition Time
(Note 2)
TTHL
TTLH
VDD = 5V, VIN = VDD or GND
9
+25
o
C
-
200
ns
10, 11
+125
o
C, -55
o
C
-
270
ns
NOTES:
1. VDD = 5V, CL = 50pF, RL = 200K, input TR, TF < 20ns.
2. -55
o
C and +125
o
C limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Supply Current
IDD
VDD = 5V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
-
1
A
+125
o
C
-
30
A
VDD = 10V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
-
2
A
+125
o
C
-
60
A
VDD = 15V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
-
2
A
+125
o
C
-
120
A
Output Voltage
VOL
VDD = 5V, No Load
1, 2
+25
o
C, +125
o
C,
-55
o
C
-
50
mV
Output Voltage
VOL
VDD = 10V, No Load
1, 2
+25
o
C, +125
o
C,
-55
o
C
-
50
mV
Output Voltage
VOH
VDD = 5V, No Load
1, 2
+25
o
C, +125
o
C,
-55
o
C
4.95
-
V
Output Voltage
VOH
VDD = 10V, No Load
1, 2
+25
o
C, +125
o
C,
-55
o
C
9.95
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1, 2
+125
o
C
0.36
-
mA
-55
o
C
0.64
-
mA
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1, 2
+125
o
C
0.9
-
mA
-55
o
C
1.6
-
mA
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1, 2
+125
o
C
2.4
-
mA
-55
o
C
4.2
-
mA
Output Current (Source)
IOH5A
VDD = 5V, VOUT = 4.6V
1, 2
+125
o
C
-
-0.36
mA
-55
o
C
-
-0.64
mA
Output Current (Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1, 2
+125
o
C
-
-1.15
mA
-55
o
C
-
-2.0
mA
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1, 2
+125
o
C
-
-0.9
mA
-55
o
C
-
-1.6
mA
Output Current (Source)
IOH15
VDD =15V, VOUT = 13.5V
1, 2
+125
o
C
-
-2.4
mA
-55
o
C
-
-4.2
mA
Input Voltage Low
VIL
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25
o
C, +125
o
C,
-55
o
C
-
3
V
Input Voltage High
VIH
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25
o
C, +125
o
C,
-55
o
C
+7
-
V
7-871
Specifications CD4042BMS
Propagation Delay
Data in to Q
TPHL1
TPLH1
VDD = 10V
1, 2, 3
+25
o
C
-
110
ns
VDD = 15V
1, 2, 3
+25
o
C
-
80
ns
Propagation Delay
Data in to Q
TPHL2
TPLH2
VDD = 10V
1, 2, 3
+25
o
C
-
150
ns
VDD = 15V
1, 2, 3
+25
o
C
-
100
ns
Propagation Delay
Clock to Q
TPHL3
TPLH3
VDD = 10V
1, 2, 3
+25
o
C
-
200
ns
VDD = 15V
1, 2, 3
+25
o
C
-
160
ns
Propagation Delay
Clock to Q
TPLH4
TPHL4
VDD = 10V
1, 2, 3
+25
o
C
-
230
ns
VDD = 15V
1, 2, 3
+25
o
C
-
180
ns
Transition Time
TTHL
VDD = 10V
1, 2, 3
+25
o
C
-
100
ns
VDD = 15V
1, 2, 3
+25
o
C
-
80
ns
Clock Input Rise and Fall
Time (Note 4)
TRCL
TFCL
VDD = 5V
1, 2, 3
+25
o
C
-
*
-
VDD = 10V
1, 2, 3
+25
o
C
-
*
-
VDD = 15V
1, 2, 3
+25
o
C
-
*
-
Minimum Data Setup
Time
TS
VDD = 5V
1, 2, 3
+25
o
C
-
50
ns
VDD = 10V
1, 2, 3
+25
o
C
-
30
ns
VDD = 15V
1, 2, 3
+25
o
C
-
25
ns
Minimum Data Hold Time
TH
VDD = 5V
1, 2, 3
+25
o
C
-
120
ns
VDD = 10V
1, 2, 3
+25
o
C
-
60
ns
VDD = 15V
1, 2, 3
+25
o
C
-
50
ns
Minimum Clock Pulse
Width
TW
VDD = 5V
1, 2, 3
+25
o
C
-
200
ns
VDD = 10V
1, 2, 3
+25
o
C
-
100
ns
VDD = 15V
1, 2, 3
+25
o
C
-
60
ns
Input Capacitance
CIN
Any Input
1, 2
+25
o
C
-
7.5
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K.
4. * Not sensitive
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Supply Current
IDD
VDD = 20V, VIN = VDD or GND
1, 4
+25
o
C
-
7.5
A
N Threshold Voltage
VNTH
VDD = 10V, ISS = -10
A
1, 4
+25
o
C
-2.8
-0.2
V
N Threshold Voltage
Delta
VTN
VDD = 10V, ISS = -10
A
1, 4
+25
o
C
-
1
V
P Threshold Voltage
VTP
VSS = 0V, IDD = 10
A
1, 4
+25
o
C
0.2
2.8
V
P Threshold Voltage
Delta
VTP
VSS = 0V, IDD = 10
A
1, 4
+25
o
C
-
1
V
Functional
F
VDD = 18V, VIN = VDD or GND
1
+25
o
C
VOH >
VDD/2
VOL <
VDD/2
V
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
TPHL
TPLH
VDD = 5V
1, 2, 3, 4
+25
o
C
-
1.35 x
+25
o
C
Limit
ns
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25
o
C limit.
4. Read and Record
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
(Continued)
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
LIMITS
UNITS
MIN
MAX
7-872
Specifications CD4042BMS
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25
O
C
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-1
IDD
0.2
A
Output Current (Sink)
IOL5
20% x Pre-Test Reading
Output Current (Source)
IOH5A
20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
METHOD
GROUP A SUBGROUPS
READ AND RECORD
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
Subgroups 1, 2 3
NOTE:
1. 1.5% parametric, 3% functional; cumulative for static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS
METHOD
TEST
READ AND RECORD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
Group E Subgroup 2
5005
1, 7, 9
Table 4
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
FUNCTION
OPEN
GROUND
VDD
9V
-0.5V
OSCILLATOR
50kHz
25kHz
Static Burn-In 1
Note 1
1 - 3, 9 - 12, 15
4 - 8, 13, 14
16
Static Burn-In 2
Note 1
1 - 3, 9 - 12, 15
8
4 - 7, 13, 14, 16
Dynamic Burn-
In Note 1
-
8
6, 16
1 - 3, 9 - 12, 15
5
4, 7, 13, 14
Irradiation
Note 2
1 - 3, 9 - 12, 15
8
4 - 7, 13, 14, 16
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K
5%, VDD = 18V
0.5V
2. Each pin except VDD and GND will have a series resistor of 47K
5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V
0.5V
873
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
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Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
Specifications CD4042BMS
Logic Diagram
LOGIC BLOCK DIAGRAM
TRUTH TABLE
CLOCK
POLARITY
Q
0
0
D
0
LATCH
1
1
D
1
LATCH
TG
CL
CL
TG
CL
CL
TG
P
TG
P
P
P
P
CL
CL
2
3
4
5
6
D1
*
Q1
Q1
CLOCK
POLARITY
*
*
VDD
VSS
*
ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
ONE OF FOUR LATCHES
CONTROL
7-874
CD4042BMS
Typical Performance Characteristics
FIGURE 1. TYPICAL OUTPUT LOW (SINK) CURRENT CHAR-
ACTERISTICS
FIGURE 2. MINIMUM OUTPUT LOW (SINK) CURRENT CHAR-
ACTERISTICS
FIGURE 3. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
FIGURE 4. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
FIGURE 5. TYPICAL PROPAGATION DELAY TIME vs LOAD
CAPACITANCE - DATA TO Q
FIGURE 6. TYPICAL PROPAGATION DELAY TIME vs LOAD
CAPACITANCE - DATA TO Q
10V
5V
AMBIENT TEMPERATURE (T
A
) = +25
o
C
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
0
5
10
15
15
10
5
20
25
30
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
10V
5V
AMBIENT TEMPERATURE (T
A
) = +25
o
C
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
0
5
10
15
7.5
5.0
2.5
10.0
12.5
15.0
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
-10V
-15V
AMBIENT TEMPERATURE (T
A
) = +25
o
C
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
0
-5
-10
-15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-20
-25
-30
0
-5
-10
-15
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
-10V
-15V
AMBIENT TEMPERATURE (T
A
) = +25
o
C
0
-5
-10
-15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
0
-5
-10
-15
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
AMBIENT TEMPERATURE (T
A
) = +25
o
C
25
LOAD CAPACITANCE (CL) (pF)
0
10
PROP
AGA
TION DELA
Y TIME (tPHL, tPLH) (ns)
SUPPLY VOLTAGE (VDD) = 5V
10V
15V
20
30
40
50
60
70
80
90
100
50
75
100
125
150
175
25
LOAD CAPACITANCE (CL) (pF)
0
10
PROP
AGA
TION DELA
Y TIME (tPHL, tPLH) (ns)
SUPPLY VOLTAGE (VDD) = 5V
10V
15V
20
30
40
50
60
70
80
90
100
50
75
100
125
150
175
AMBIENT TEMPERATURE (T
A
) = +25
o
C
7-875
CD4042BMS
FIGURE 7. TYPICAL PROPAGATION DELAY TIME vs LOAD
CAPACITANCE - CLOCK TO Q
FIGURE 8. TYPICAL PROPAGATION DELAY TIME vs LOAD
CAPACITANCE - CLOCK TO Q
FIGURE 9. TYPICAL POWER DISSIPATION vs FREQUENCY
FIGURE 10. TYPICAL TRANSITION TIME vs LOAD CAPACI-
TANCE
Typical Performance Characteristics
(Continued)
AMBIENT TEMPERATURE (T
A
) = +25
o
C
10V
SUPPLY VOLTAGE (VDD) = 5V
PROP
AGA
TION DELA
Y TIME (tPHL, tPLH) (ns)
150
100
50
0
20
40
60
80
LOAD CAPACITANCE (CL) (pF)
15V
200
250
300
100
120
140
AMBIENT TEMPERATURE (T
A
) = +25
o
C
SUPPLY VOLTAGE (VDD) = 5V
PROP
AGA
TION DELA
Y TIME (tPHL, tPLH) (ns)
150
100
50
0
20
40
60
80
LOAD CAPACITANCE (CL) (pF)
15V
200
250
300
100
120
140
10V
10V
5V
10V
AMBIENT TEMPERATURE (T
A
) = +25
o
C
SUPPLY VOLTAGE (VDD) = 15V
CL = 15pF
CL = 50pF
INPUT FREQUENCY (fI) (kHz)
10
3
10
4
10
5
10
6
10
7
10
5
10
3
10
1
10
6
POWER DISSIP
A
TION PER DEVICE (PD) (
W)
10
2
10
4
AMBIENT TEMPERATURE (T
A
) = +25
o
C
LOAD CAPACITANCE (CL) (pF)
0
40
60
80
100
20
0
50
100
150
200
SUPPLY VOLTAGE (VDD) = 5V
10V
15V
TRANSITION TIME (tTHL, tTLH) (ns)
FIGURE 11. DYNAMIC TEST PARAMETERS
t
S
t
H
tPHL, tPLH
D TO Q OR Q
tPHL, tPLH
CL TO Q OR Q
CLOCK
CL
DATA
INPUT
D
Q
OUTPUT
NOTES:
1. For positive clock edge, input data is
latched when polarity is low.
2. For negative clock edge, input data is
latched when polarity is high.
NOTE 1
NOTE 2
LATCH
LOW DATA
LATCH
HIGH DATA
LOW DATA
LATCHED
HIGH DATA
LATCHED
Chip Dimensions and Pad Layout
Dimensions in parentheses are in millimeters and are
derived from the basic inch dimensions as indicated
Grid graduations are in mils (10
-3
inch).