S E M I C O N D U C T O R
1
Features
This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
Exceeds 2kV ESD Protection MIL-STD-883, Method 3015
Meets JEDEC Standard No. 20
SCR - Latch-Up-Resistant CMOS Process and Circuit
Design
Speed of Bipolar FAST/A/S with Significantly Reduced
Power Consumption
Functionally and Pin-Compatible with Industry 54
Bipolar Types in the FAST, AS and S Series
Balanced Propagation Delays
Military Operating Temperature Range
- Ceramic (CERDIP) 54 Series: . . . . . . . . -55 to 125
o
C
24mA Output Drive Current, Drives 75
Lines with-
out Need for Terminations
Fan Out (Over Temperature)
- ACL Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2400
- FAST Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
- AS Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Operating Voltage
- AC Types . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5V to 5.5V
- ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
Functional Diagram
Description
The CD54AC541F3A and CD54ACT541F3A are octal
buffer/line drivers that utilize the Harris Advanced CMOS
Logic
technology.
The
CD54AC541F3A
and
CD54ACT541F3A are non-inverting three-state buffers having
two active-LOW output enables.
Pinout
18
17
16
15
13
11
12
14
2
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
OE
2
OE
1
1
19
4
9
3
5
6
7
8
A0
A1
A2
A3
A4
A5
A6
A7
GND = 10
V
CC
= 20
Ordering Information
PART NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG.
NO.
CD54AC541F3A
-55 to 125
20 Ld CERDIP
F20.3
CD54ACT541F3A
-55 to 125
20 Ld CERDIP
F20.3
NOTE:
1. Wafer and die for this part number is available which meets all elec-
trical specifications. Please contact your local sales office or Harris
customer service for ordering information.
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
OE
1
A0
A1
A2
A3
A4
A6
A5
A7
GND
V
CC
Y0
Y1
Y2
OE
2
Y3
Y4
Y5
Y6
Y7
July 1998
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
Harris Corporation 1998
CD54AC541F3A,
CD54ACT541F3A
Octal Buffer/Line Driver
Three-State, Non-Inverting
File Number
3914.1
2
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .
20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
50mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
50mA
DC V
CC
or Ground Current, I
CC or
I
GND
(Note 2)
. . . . . . . . .
100mA
Operating Conditions
Temperature Range, T
A
. . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
(Note 3)
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Slew Rate, dt/dv
AC Types
1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)
3.6V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
4.5V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
Thermal Resistance (Typical, Note 4)
JA
(
o
C/W)
JC
(
o
C/W)
CERDIP Package . . . . . . . . . . . . . . . .
85
24
Maximum Junction Temperature (Hermetic Package or Die) . . . 175
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2. For up to 4 outputs per device, add
25mA for each additional output.
3. Unless otherwise specified, all voltages are referenced to ground.
4.
JA
is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
MAX
MIN
MAX
AC TYPES
High Level Input Voltage
V
IH
-
-
1.5
1.2
-
1.2
-
V
3
2.1
-
2.1
-
V
4.5
3.15
(Note 5)
-
3.15
(Note 5)
-
V
5.5
3.85
-
3.85
-
V
Low Level Input Voltage
V
IL
-
-
1.5
-
0.3
-
0.3
V
3
-
0.9
-
0.9
V
4.5
-
1.35
(Note 5)
-
1.35
(Note 5)
V
5.5
-
1.65
-
1.65
V
High Level Output Voltage
V
OH
V
IH
or V
IL
-0.05
1.5
1.4
-
1.4
-
V
-0.05
3
2.9
-
2.9
-
V
-0.05
4.5
4.4
-
4.4
-
V
-4
3
2.58
-
2.4
-
V
-24
4.5
3.94
(Note 5)
-
3.7
(Note 5)
-
V
-50
(Note 6, 7)
5.5
-
-
3.85
-
V
CD54AC541F3A, CD54ACT541F3A
3
Low Level Output Voltage
V
OL
V
IH
or V
IL
0.05
1.5
-
0.1
-
0.1
V
0.05
3
-
0.1
-
0.1
V
0.05
4.5
-
0.1
-
0.1
V
12
3
-
0.36
-
0.5
V
24
4.5
-
0.36
(Note 5)
-
0.5
(Note 5)
V
50
(Note 6, 7)
5.5
-
-
-
1.65
V
Input Leakage Current
I
I
V
CC
or
GND
-
5.5
-
0.1
(Note 5)
-
1
(Note 5)
A
Three-State Leakage
Current
I
OZ
V
IH
or V
IL
V
O
= V
CC
or GND
-
5.5
-
0.5
(Note 5)
-
10
(Note 5)
A
Quiescent Device Current
I
CC
V
CC
or
GND
0
5.5
-
8
(Note 5)
-
160
(Note 5)
A
ACT TYPES
High Level Input Voltage
V
IH
-
-
4.5 to 5.5
2
(Note 5)
-
2
(Note 5)
-
V
Low Level Input Voltage
V
IL
-
-
4.5 to 5.5
-
0.8
(Note 5)
-
0.8
(Note 5)
V
High Level Output Voltage
V
OH
V
IH
or V
IL
-0.05
4.5
4.4
-
4.4
-
V
-24
4.5
3.94
(Note 5)
-
3.7
(Note 5)
-
V
-50
(Note 6, 7)
5.5
-
-
3.85
-
V
Low Level Output Voltage
V
OL
V
IH
or V
IL
0.05
4.5
-
0.1
-
0.1
V
24
4.5
-
0.36
(Note 5)
-
0.5
(Note 5)
V
50
(Note 6, 7)
5.5
-
-
-
1.65
V
Input Leakage Current
I
I
V
CC
or
GND
-
5.5
-
0.1
(Note 5)
-
1
(Note 5)
A
Three-State or Leakage
Current
I
OZ
V
IH
or V
IL
V
O
= V
CC
or GND
-
5.5
-
0.5
(Note 5)
-
10
(Note 5)
A
Quiescent Device Current
I
CC
V
CC
or
GND
0
5.5
-
8
(Note 5)
-
160
(Note 5)
A
Additional Supply Current per
Input Pin TTL Inputs High
1 Unit Load
I
CC
V
CC
-2.1
-
4.5 to 5.5
-
2.4
-
3
mA
NOTES:
5. Tested 100%.
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
7. Test verifies a minimum transmission-line-drive capability of 75
for 54AC/ACT Series.
DC Electrical Specifications
(Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
MAX
MIN
MAX
CD54AC541F3A, CD54ACT541F3A
4
ACT Input Load Table
INPUT
UNIT LOAD
Data
0.5
OE1, OE2
1.3
NOTE: Unit load is
I
CC
limit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25
o
C.
Switching Specifications
Input t
r
, t
f
= 3ns, C
L
= 50pF (Worst Case)
PARAMETER
SYMBOL
V
CC
(V)
-55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
AC TYPES
Propagation Delay, Data to Output
t
PLH
, t
PHL
1.5
-
-
98
ns
3.3 (Note 9)
3.3
-
10.9
ns
5 (Note 10)
2.3
-
7.8 (Note 8)
ns
Propagation Delay, Enable, Disable to
Output
t
PZL
, t
PZH
1.5
-
-
150
3.3
5.4
-
18
5
3.6
-
12 (Note 8)
t
PLZ
, t
PHZ
1.5
-
-
150
3.3
4.5
-
15
5
3.6
-
12 (Note 8)
Minimum (Valley) V
OH
During Switching
of Other Outputs
(Output Under Test Not Switching)
V
OHV
See Figure 1
5
-
4 at 25
o
C
-
V
Maximum (Peak) V
OL
During Switching of
Other Outputs
(Output Under Test Not Switching)
V
OLP
See Figure 1
5
-
1 at 25
o
C
-
V
Three-State Output Capacitance
C
O
-
-
-
15
pF
Input Capacitance
C
I
-
-
-
10
pF
Power Dissipation Capacitance
C
PD
(Note 11)
-
-
60
-
pF
ACT TYPES
Propagation Delay, Data to Output
t
PLH
, t
PHL
5 (Note 10)
2.5
-
8.3 (Note 8)
ns
Propagation Delay, Enable, Disable to
Output
t
PLZ
, t
PZL
,
t
PZH
, t
PHZ
5
4
-
13.4 (Note 8)
ns
Minimum (Valley) V
OH
During Switching
of Other Outputs
(Output Under Test Not Switching)
V
OHV
See Figure 1
5
-
4 at 25
o
C
-
V
Maximum (Peak) V
OL
During Switching of
Other Outputs
(Output Under Test Not Switching)
V
OLP
See Figure 1
5
-
1 at 25
o
C
-
V
Three-State Output Capacitance
C
O
-
-
-
15
pF
Input Capacitance
C
I
-
-
-
10
pF
Power Dissipation Capacitance
C
PD
(Note 11)
-
-
60
-
pF
NOTES:
8. Limits tested 100%.
9. 3.3V Min is at 3.6V, Max si at 3V.
10. 5V Min is at 5.5V, Max is at 4.5V
11. C
PD
is used to determine the dynamic power consumption per gate.
AC: P
D
= V
CC
2
f
i
(C
PD
+ C
L
)
ACT: P
D
= V
CC
2
f
i
(C
PD
+ C
L
) + V
CC
I
CC
where f
i
= input frequency, C
L
= output load capacitance, V
CC
= supply voltage.
CD54AC541F3A, CD54ACT541F3A
5
All Harris Semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Harris Semiconductor products are sold by description only. Harris Semiconductor reserves the right to make changes in circuit design and/or specifications at
any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Harris is
believed to be accurate and reliable. However, no responsibility is assumed by Harris or its subsidiaries for its use; nor for any infringements of patents or other
rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Harris or its subsidiaries.
Sales Office Headquarters
For general information regarding Harris Semiconductor and its products, call 1-800-4-HARRIS
NORTH AMERICA
Harris Semiconductor
P. O. Box 883, Mail Stop 53-210
Melbourne, FL 32902
TEL: 1-800-442-7747
(407) 729-4984
FAX: (407) 729-5321
EUROPE
Harris Semiconductor
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Harris Semiconductor PTE Ltd.
No. 1 Tannery Road
Cencon 1, #09-01
Singapore 1334
TEL: (65) 748-4200
FAX: (65) 748-0400
S E M I C O N D U C T O R
Burn-In Test Circuit Connections
(Use DC II for F3A Burn-In and AC for Life Test)
DC
DC BURN-IN I
DC BURN-IN II
OPEN
GROUND
V
CC
(6V)
OPEN
GROUND
V
CC
(6V)
CD54AC/ACT541
11-18
1-10, 19
20
11-18
10
1-9, 19, 20
AC
OPEN
GROUND
1/2 V
CC
(3V)
V
CC
(6V)
OSCILLATOR
50kHz
25kHz
CD54AC/ACT541
-
10
11-18
20
1, 19
2-9
NOTE: Each pin except V
CC
and Gnd will have a resistor of 2k
-47k
.
DUT
OUTPUT
R
L
(NOTE)
OUTPUT
LOAD
500
C
L
50pF
NOTE: For AC Series Only: When V
CC
= 1.5V, R
L
= 1k
.
FIGURE 1. PROPAGATION DELAY TIMES
CD54AC
CD54ACT
Input Level
V
CC
3V
Input Switching Voltage, V
S
0.5 V
CC
1.5V
Output Switching Voltage, V
S
0.5 V
CC
0.5 V
CC
CD54AC541F3A, CD54ACT541F3A
PDF 
ZIP