S E M I C O N D U C T O R
1
Features
This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
Exceeds 2kV ESD Protection MIL-STD-883, Method 3015
Meets JEDEC Standard No. 20
SCR - Latch-Up-Resistant CMOS Process and Circuit
Design
Speed of Bipolar FAST/A/S with Significantly Reduced
Power Consumption
Functionally and Pin-Compatible with Industry 54
Bipolar Types in the FAST, AS and S Series
Balanced Propagation Delays
Military Operating Temperature Range
- Ceramic (CERDIP) 54 Series: . . . . . . . . -55 to 125
o
C
24mA Output Drive Current, Drives 75
Lines with-
out Need for Terminations
Fan Out (Over Temperature)
- ACL Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2400
- FAST Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
- AS Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Operation Voltage . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
Functional Diagram
Description
The CD54ACT623F3A is an octal bus transceiver that uti-
lizes Harris Advanced CMOS Logic technology. It is a non-
inverting three-state bidirectional transceiver-buffer that
allows for two-way transmission from "A" bus to "B" bus or
"B" bus to "A" bus depending on the logic levels of the Output
Enable (OE
AB
, OE
BA
) inputs.
The dual Output Enable provision gives these devices the
capability to store data by simultaneously enabling OE
AB
and OE
BA
. Each output reinforces its input under these con-
ditions, and when all other data sources to the bus lines are
at high-impedance, both sets of bus lines will remain in their
last states.
Pinout
18
17
16
15
13
11
12
14
2
B0
B1
B2
B3
B4
B5
B6
B7
OE
BA
OE
AB
1
19
4
9
3
5
6
7
8
A0
A1
A2
A3
A4
A5
A6
A7
Ordering Information
PART NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG.
NO.
CD54ACT623F3A
-55 to 125
20 Ld CERDIP
F20.3
NOTE:
1. Wafer and die for this part number is available which meets all elec-
trical specifications. Please contact your local sales office or Harris
customer service for ordering information.
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
OE
AB
A0
A1
A2
A3
A4
A6
A5
A7
GND
V
CC
B0
B1
B2
OE
BA
B3
B4
B5
B6
B7
July 1998
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
Harris Corporation 1998
CD54ACT623F3A
Octal Bus Transceiver
Three-State, Non-Inverting
File Number
3917.1
2
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .
20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
50mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
50mA
DC V
CC
or Ground Current, I
CC or
I
GND
(Note 2)
. . . . . . . . .
100mA
Operating Conditions
Temperature Range, T
A
. . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
(Note 3) . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Thermal Resistance (Typical, Note 4)
JA
(
o
C/W)
JC
(
o
C/W)
CERDIP Package . . . . . . . . . . . . . . . .
80
22
Maximum Junction Temperature (Hermetic Package or Die) . . . 175
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2. For up to 4 outputs per device, add
25mA for each additional output.
3. Unless otherwise specified, all voltages are referenced to ground.
4.
JA
is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-55
o
C TO 125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
MAX
MIN
MAX
High Level Input Voltage
V
IH
-
-
4.5 to 5.5
2
(Note 5)
-
2
(Note 5)
-
V
Low Level Input Voltage
V
IL
-
-
4.5 to 5.5
-
0.8
(Note 5)
-
0.8
(Note 5)
V
High Level Output Voltage
V
OH
V
IH
or V
IL
-0.05
4.5
4.4
-
4.4
-
V
-24
4.5
3.94
(Note 5)
-
3.7
(Note 5)
-
V
-50
(Note 6, 7)
5.5
-
-
3.85
-
V
Low Level Output Voltage
V
OL
V
IH
or V
IL
0.05
4.5
-
0.1
-
0.1
V
24
4.5
-
0.36
(Note 5)
-
0.5
(Note 5)
V
50
(Note 6, 7)
5.5
-
-
-
1.65
V
Input Leakage Current
I
I
V
CC
or
GND
-
5.5
-
0.1
(Note 5)
-
1
(Note 5)
A
Three-State or Leakage
Current
I
OZ
V
IH
or V
IL
V
O
= V
CC
or GND
-
5.5
-
0.5
(Note 5)
-
10
(Note 5)
A
Quiescent Device Current
I
CC
V
CC
or
GND
0
5.5
-
8
(Note 5)
-
160
(Note 5)
A
Additional Supply Current per
Input Pin TTL Inputs High
1 Unit Load
I
CC
V
CC
-2.1
-
4.5 to 5.5
-
2.4
-
3
mA
NOTES:
5. Tested 100%.
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
7. Test verifies a minimum transmission-line-drive capability of 75
for 54ACT Series.
CD54ACT623F3A
3
ACT Input Load Table
INPUT
UNIT LOAD
An, Bn
0.83
OE
BA
0.64
OE
AB
0.15
NOTE: Unit load is
I
CC
limit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25
o
C.
Switching Specifications
Input t
r
, t
f
= 3ns, C
L
= 50pF (Worst Case)
PARAMETER
SYMBOL
V
CC
(V)
-55
o
C TO 125
o
C
UNITS
MIN
TYP
MAX
Propagation Delay, Data to Output
t
PLH
, t
PHL
5 (Note 10)
1.8
-
10.6 (Note 8
ns
Propagation Delay, Output Disable to Output
t
PLZ
, t
PHZ
5
2.5
-
14.4 (Note 8)
ns
Propagation Delay, Output Enable to Output
t
PZL
, t
PZH
5
2.5
-
14.4 (Note 8)
ns
Minimum (Valley) V
OH
During Switching of Other Outputs
(Output Under Test Not Switching)
V
OHV
See Figure 1
5
-
4 at 25
o
C
-
V
Maximum (Peak) V
OL
During Switching of Other Outputs
(Output Under Test Not Switching)
V
OLP
See Figure 1
5
-
1 at 25
o
C
-
V
Three-State Output Capacitance
C
O
-
-
-
15
pF
Input Capacitance
C
I
-
-
-
10
pF
Power Dissipation Capacitance
C
PD
(Note 11)
-
-
79
-
pF
NOTES:
8. Limits tested 100%.
9. 3.3V Min = 3.6V, Max = 3V.
10. 5V Min = 5.5V, Max = 4.5V
11. C
PD
is used to determine the dynamic power consumption per gate.
P
D
= V
CC
2
f
i
(C
PD
+ C
L
) + V
CC
I
CC
where f
i
= input frequency, C
L
= output load capacitance, V
CC
= supply voltage.
Burn-In Test Circuit Connections
(Use DC II for F3A Burn-In and AC for Life Test)
DC
DC BURN-IN I
DC BURN-IN II
OPEN
GROUND
V
CC
(6V)
OPEN
GROUND
V
CC
(6V)
CD54ACT623
2-9
1, 10-19
20
11-18
10
1-9, 19, 20
AC
OPEN
GROUND
1/2 V
CC
(3V)
V
CC
(6V)
OSCILLATOR
50kHz
25kHz
CD54ACT623
-
10
11-18
19, 20
2-9
1
NOTE: Each pin except V
CC
and Gnd will have a resistor of 2k
-47k
.
DUT
OUTPUT
R
L
OUTPUT
LOAD
500
C
L
50pF
FIGURE 1. PROPAGATION DELAY TIMES
CD54ACT
Input Level
3V
Input Switching Voltage, V
S
1.5V
Output Switching Voltage, V
S
0.5 V
CC
CD54ACT623F3A
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