42
TM
Features
Access Time
- 610ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . at V
DD
= 5V
- 320ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . at V
DD
= 10V
No Precharge or Clock Required
Description
The CDP1824/3 and CDP1824C/3 types are high-reliability
CMOS 32-word x 8-bit fully static random-access memories
for use in CDP1800-series microprocessor systems. These
parts are compatible with the CDP1802 microprocessor and
will interface directly without additional components.
The CDP1824/3 is fully decoded and does not require a pre-
charge or clocking signal for proper operation. It has com-
mon input and output and is operated from a single voltage
supply. The MRD signal (output disable control) enables the
three-state output drivers, and overrides the MWR signal. A
CS input is provided for memory expansion.
The CDP1824C/3 is functionally identical to the CDP1824/3.
The CDP1824/3 has a recommended operating voltage
range of 4V to 10.5V, and the CDP1824C/3 has an operating
voltage range of 4V to 6.5V.
Ordering Information
5V
10V
PACK-
AGE
TEMP. RANGE
PKG.
NO.
CDP1824CD3 CDP1824D3 SBDIP
-55
o
C to
+125
o
C
D18.3
Pinout
CDP1824/3, CDP1824C/3 (SBDIP)
TOP VIEW
Functional Diagram
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1
V
DD
MRD
CS
BUS0
BUS1
BUS2
BUS3
MWR
BUS4
MA4
MA3
MA2
MA1
MA0
BUS7
BUS5
BUS6
V
SS
MA4
MA3
MA2
MA1
MA0
MWR
CS
V
DD
= 18
V
SS
= 9
BUS
7
BUS
6
BUS
5
BUS
4
BUS
3
BUS
2
BUS
1
BUS
0
MRD
16
5
4
3
2
1
17
15
6
7
8
10
11
12
13
14
ADDRESS
DECODER
32 X 8-BIT
ARRAY
SENSE
AMPL
I/O BUFFERS
OPERATIONAL MODES
FUNCTION
CS
MRD
MWR
DATA PINS STATUS
READ
0
0
X
Output: High/Low Dependent on Data
WRITE
0
1
0
Input: Output Disabled
Not Selected
1
X
X
Output Disabled: High-Impedance State
Standby
0
1
1
Output Disabled: High-Impedance State
Logic 1 = High Logic 0 = Low X = Don't Care
March 1997
CDP1824/3,
CDP1824C/3
High-Reliability CMOS 32-Word x 8-Bit
Static Random-Access Memory
File Number
1717.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2001. All Rights Reserved
43
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage Range, (V
DD
)
(All Voltages Referenced to V
SS
Terminal)
CDP1824/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1824C/3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to V
DD
+0.5V
DC Input Current, Any One Input
. . . . . . . . . . . . . . . . . . . . . . . .
10mA
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
JC
(
o
C/W)
SBDIP Package. . . . . . . . . . . . . . . . . .
75
20
Device Dissipation Per Output Transistor
T
A
= Full Package Temperature Range
(All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW
Operating Temperature Range (T
A
)
Package Type D . . . . . . . . . . . . . . . . . . . . . . . . .-55
o
C to +125
o
C
Storage Temperature Range (T
STG
) . . . . . . . . . . .-65
o
C to +150
o
C
Lead Temperature (During Soldering)
At distance 1/16
1/32 In. (1.59
0.79mm)
from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265
o
C
Recommended Operating Conditions
T
A
= Full Package-Temperature Range. For maximum reliability, nominal operating
conditions should be selected so that operation is always within the following ranges:
PARAMETER
LIMITS
UNITS
CDP1824/3
CDP1824C/3
MIN
MAX
MIN
MAX
DC Operating Voltage Range
4
10.5
4
6.5
V
Input Voltage Range
V
SS
V
DD
V
SS
V
DD
V
Static Electrical Specifications
PARAMETER
SYMBOL
CONDITIONS
LIMITS
UNITS
V
O
(V)
V
IN
(V)
V
DD
(V)
-55
o
C, +25
o
C
+125
o
C
MIN
MAX
MIN
MAX
Quiescent Device Current
(Note 1)
I
DD
-
0, 5
5
-
50
-
500
A
-
0, 10
10
-
500
-
1000
A
Output Voltage Low-Level
(Note 2)
V
OL
-
0, 5
5
-
0.1
-
0.2
V
-
10
-
0.1
-
0.2
V
Output Voltage High-Level
(Note 2)
V
OH
-
0, 5
5
4.9
-
4.8
-
V
-
-
10
9.9
-
4.8
-
V
Input Low Voltage
V
IL
0.5, 4.5
-
5
-
1.5
-
1.5
V
1, 9
-
10
-
3
-
-
V
Input High Voltage
V
IH
0.5, 4.5
-
5
3.5
-
3.5
-
V
1, 9
-
10
7
-
7
-
V
Output Low Drive (Sink)
Current
I
OL
0.4
0, 5
5
4
-
1.5
-
mA
0.5
0, 10
10
4
-
2.9
-
mA
Output High Drive (Source)
Current
I
OH
4.6
0, 5
5
-
-1
-
-0.75
mA
9.5
0, 10
10
-
-2
-
-1.5
mA
Input Current
I
IN
Any
Input
0, 5
5
-
1
-
5
A
0, 10
10
-
1
-
5
A
Three-State Output
Leakage Current
I
OUT
0, 5
0, 5
5
-
2
-
5
A
0, 10
0, 10
10
-
2
-
5
A
Input Capacitance
C
IN
(Note 2)
-
10
-
10
pF
Output Capacitance
C
OUT
(Note 2)
-
15
-
15
pF
NOTES:
1. The CDP1824C/3 meets all 5V Static Electrical Characteristics of the CDP1824/3 except Quiescent Device Current for which the limits
are I
DD
= 200
A at +25
o
C/-55
o
C; I
DD
= 1000
A at +125
o
C.
2. Guaranteed, but not tested.
CDP1824/3, CDP1824C/3
44
Read Cycle Dynamic Electrical Specifications
Input t
R
, t
F
15ns, C
L
= 50pF
PARAMETER
SYMBOL
TEST
CONDITIONS
LIMITS
UNITS
-55
o
C, +25
o
C
+125
o
C
V
DD
(V)
MIN
MAX
MIN
MAX
Access Time From Address Change
t
AA
5
-
610
-
825
ns
10
-
320
-
375
ns
Access Time From Chip Select
t
DOA
5
-
610
-
825
ns
10
-
320
-
375
ns
Output Active From MRD
t
AM
5
-
610
-
825
ns
10
-
320
-
375
ns
NOTE:
1. Minimum timing for valid data output longer times will initiate an earlier, but invalid output.
FIGURE 1. READ CYCLE TIMING DIAGRAM
t
AM
(NOTE 1)
t
AA
t
DOA
(NOTE 1)
HIGH IMPEDANCE
MRD
MA
CS
DATA OUT
CDP1824/3, CDP1824C/3
45
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
Write Cycle Dynamic Electrical Specifications
Input t
R
, t
F
15ns, C
L
= 50pF
PARAMETER
SYMBOL
TEST
CONDITIONS
LIMITS
UNITS
-55
o
C, +25
o
C
+125
o
C
V
DD
(V)
(NOTE 1)
MIN
MAX
(NOTE 1)
MIN
MAX
Write Pulse Width
t
WRW
5
350
-
475
-
ns
10
180
-
220
-
ns
Data Setup Time
t
DS
5
400
-
560
-
ns
10
190
-
260
-
ns
Data Hold Time
t
DH
5
70
-
90
-
ns
10
35
-
45
-
ns
Chip Select Setup Time
t
CS
5
550
-
775
-
ns
10
340
-
475
-
ns
Address Setup Time
t
AS
5
550
-
775
-
ns
10
340
-
475
-
ns
NOTE:
1. Time required by a device to allow for the indicated function.
FIGURE 2. WRITE CYCLE TIMING DIAGRAM
MA
CS
MWR
BUS
t
AS
t
CS
t
WRW
t
DS
t
DH
CDP1824/3, CDP1824C/3
46
Static Burn-In Circuit
Data Retention Specifications
At T
A
= +25
o
C
PARAMETER
SYMBOL
TEST
CONDITIONS
LIMITS
UNITS
CDP1824/3
CDP1824C/3
V
DR
(V)
V
DD
(V)
MIN
MAX
MIN
MAX
Data Retention Voltage
V
DR
-
-
2.5
-
2.5
-
V
Data Retention Quiescent Current
I
DD
2.5
-
-
10
-
40
A
Chip Deselect to Data Retention Time
t
CDR
2.5
5
600
-
600
-
ns
2.5
10
300
-
-
-
ns
Recovery to Normal Operation Time
t
RC
2.5
5
600
-
600
-
ns
2.5
10
300
-
-
-
ns
TYPE
V
DD
TEMPERATURE
TIME
CDP1824
11V
+125
o
C
160 Hrs., Min.
CDP1824C
7V
+125
o
C
160 Hrs., Min.
NOTE: t
r
, t
f
> 1
s.
FIGURE 3. LOW V
DD
DATA RETENTION WAVEFORMS AND TIMING DIAGRAM
DATA RETENTION
MODE
0.95 V
DD
0.95 V
DD
t
F
V
DD
t
CDR
t
F
t
RC
V
DD
V
IH
V
IL
V
IL
V
IH
CS
(NOTE 1)
(NOTE 1)
V
DD
V
DD
V
SS
V
SS
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1
All Resistors 47k
(
20%)
CDP1824/3, CDP1824C/3
PDF 
ZIP