1
CMOS Serial 8-Bit Input/Output Port
The CDP68HC68P1 is a serially addressed 8-bit
Input/Output port that allows byte or individual bit control. It
consists of three registers, an output buffer and control logic.
Data is shifted in and out of the device via shift register that
utilizes the SPI (Serial Peripheral Interface) bus. The I/O port
data flow is controlled by the Data Direction Register and
data is stored in the Data Register that outputs or senses the
logic levels at the buffered I/O pins. All inputs, including the
serial interface are Schmitt triggered. This device also
features a compare function that compares the data register
and port pin values for 4 programmable conditions and sets
a software accessible flag if the condition is satisfied. The
user also has the option of bit-set or bit-clear when writing to
the data register.
Features
Fully Static Operation
Operating Voltage Range 3-6V
Compatible with Intersil/Motorola SPI Bus
2 External Address Pins Tied to V
DD
or V
SS
to Allow Up to
4 Devices to Share the Same Chip Enable
Versatile Bit-Set and Bit-Clear Capability
Accepts Either SCK Clock Polarity - SCK Voltage Level is
Latched When Chip Enable Goes Active
All Inputs are Schmitt-Trigger
8-Bit I/O Port - Each Bit can be Individually Programmed
as an Input or Output Via an 8-Bit Data Direction Register
Programmable On Board Comparator
Simultaneous Transfer of Compare Information to CPU
During Read or Write - Separate Access Not Required
Pinout
CDP68HC68P1
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG.
NO.
CDP68HC68P1E
-55 to 85
16 Ld PDIP
E16.3
CDP68HC68P1M
-55 to 85
16 Ld SOIC
M16.15
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
ID
0
MISO
MOSI
SCK
CE
V
SS
DO
V
DD
D2
D3
D4
D5
D6
D7
D1
ID
1
FN1858.3
CDP68HC68P1
Data Sheet
September 2003
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
2
CDP68HC68P1
Pin Descriptions
ID
0
, ID
1
- Chip identify pins, normally tied to V
DD
to V
SS
.
The 4 possible combinations of these pins allow 4 I/Os to
share a common chip enable. When the levels at these pins
match those of the identify bits in the control word, the serial
bus is enabled. The chip identify pins will retain their
previous logic state if the lines driving them become Hi-Z.
MISO - Master-in, Slave out pin. Data bytes are shifted out
at this pin most significant bit first. When the chip enable
signal is high, this pin is Hi-Z.
MOSI - Master-out, Slave in pin. Data bytes are shifted in at
this pin most significant bit first. This pin will retain its
previous logic state if its driving line becomes Hi-Z.
SCK - Serial clock input. This input causes serial data to be
latched from the MOSI input and shifted out on the MISO
output.
CE - A negative chip enable input. A high to low transition on
this pin latches the inactive SCK polarity and compare flag
and indicates the start of a data transfer. The serial interface
logic is enabled only when CE is low. This pin will retain its
previous logic state if its driving line becomes Hi-Z.
D0 -D7 - I/O Port pins. Individual programmable inputs or
outputs.
V
DD
and V
SS
- Positive and negative power supply line.
All pins except the power supply lines and MISO have
Schmitt-trigger buffered inputs.
FIGURE 1. SINGLE PORT I/O BLOCK DIAGRAM
SHIFT REGISTER
CONTROL
LOGIC
COMPARATOR
INPUT/OUTPUT
D0 - D7
DIRECTION
REGISTER
DIRECTION
REGISTER
CE
SCK
ID
1
ID
0
MOSI
MISO
FIGURE 2. SINGLE PORT I/O
CHIP
DATA OUT
CLOCK
CE
CHIP
IDENTIFY
I/O PORT
DATA IN
DATA
IN/OUT
ID
0
ID
1
D0 - D7
CDP68HC68P1
SCK
MISO
MOSI
ENABLE
3
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage Range, (V
DD
) . . . . . . . . . . . . . . . . . -0.5V to +7V
(Voltage Referenced to V
SS
Terminal)
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to V
DD
+0.5V
DC Input Current, Any One Input
. . . . . . . . . . . . . . . . . . . . . . . .
10mA
Power Dissipation Per Package (P
D
)
T
A
= -40
o
C to 60
o
C (Package Type E) . . . . . . . . . . . . . . .500mW
T
A
= 60
o
C to 85
o
C (Package Type E)
Derate Linearly at. . . . . . . . . . . . . . . . . . . . . 12mW/
o
C to 200mW
T
A
= -40
o
C to 60
o
C (Package Type M) (Note 1) . . . . . . . .300mW
T
A
= 60
o
C to 85
o
C (Package Type M) (Note 1)
Derate Linearly at. . . . . . . . . . . . . . . . . . . . . . 5mW/
o
C to 175mW
Operating Conditions
Temperature Range (T
A
)
Package Type E, M . . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to 85
o
C
DC Operating Voltage Range . . . . . . . . . . . . . . . . . 3V Min, 6V Max
Serial Clock Frequency, f
SCK
, V
DD
= 3V. . . . . . . . . . .1.05MHz Max
Serial Clock Frequency, f
SCK
, V
DD
= 4.5V . . . . . . . . . .2.1MHz Max
Input Voltage Range, V
IH
. . . . . . . . . . . . . . . . . . . . V
DD
+0.3V Max
Input Voltage Range, V
IL
. . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V Min
Thermal Resistance (Typical, Note 2)
JA
(
o
C/W)
JC
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . .
90
NA
SOIC Package . . . . . . . . . . . . . . . . . . .
110
NA
Device Dissipation Per Output Transistor . . . . . . . . . . . . . . .100mW
T
A
= Full Package Temperature Range (All Package Types)
Maximum Storage Temperature Range (T
STG
) . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s)
At Distance 1/16in
1/32in. (1.59
0.79mm) . . . . . . . . . . .265
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Printed circuit board mount: 57mm x 57mm minimum area x 1.6mm thick G10 epoxy glass, or equivalent.
2.
JA
is measured with the component mounted on an evaluation PC board in free air.
Static Electrical Specifications
T
A
= -40
o
C to 85
o
C, V
DD
= 3.3V 10%, Unless Otherwise Specified.
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
(NOTE 3)
TYP
MAX
UNITS
Output Voltage
V
OH
I
OH
= -0.4mA, V
DD
= 3V
2.7
-
-
V
V
OL
I
OL
= 0.4mA, V
DD
= 3V
-
-
0.3
V
Input Voltage
D0 - D7
Positive Trigger Threshold
V
P
1.85
-
2.4
V
Negative Trigger Threshold
V
N
0.85
-
1.35
V
Hysteresis V
IH
0.85
-
1.25
V
Input Voltage
ID
0
, ID
1
, MOSI, SCK, CE
Positive Trigger Threshold
V
P
1.3
-
1.9
V
Negative Trigger Threshold
V
N
0.8
-
1.2
V
Hysteresis V
IH
0.5
-
0.95
V
Input Leakage Current
I
IN
-
-
1
A
Standby Device Current
I
DDS
-
1
15
A
Three-State Output Leakage Current
I
OUT
-
-
10
A
Operating Device Current (Note 4)
I
OPER
V
IN
= V
IL
, V
IH
-
0.1
1
mA
Input Capacitance
C
IN
V
IN
= 0V, f = 1MHz, T
A
= 25
o
C
-
4
6
pF
NOTES:
3. Typical values are for T
A
= 25
o
C and nominal V
DD
.
4. Outputs open circuited; cycle time = Min. t
CYCLE
, duty = 100%.
CDP68HC68P1
4
Static Electrical Specifications
At T
A
= -40
o
C to 85
o
C, V
DD
= 5V 10%, Unless Otherwise Specified.
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
(NOTE 5)
TYP
MAX
UNITS
Output Voltage
V
OH
I
OH
= -1.6mA, V
DD
= 4.5V
3.7
-
-
V
V
OL
I
OL
= 1.6mA, V
DD
= 4.5V
-
-
0.4
V
V
OH
I
OH
20
A, V
DD
= 4.5V
4.4
-
-
V
V
OL
I
OL
20
A, V
DD
= 4.5V
-
-
0.1
V
Input Voltage
D0 - D7
Positive Trigger Threshold
V
P
2.15
-
3.05
V
Negative Trigger Threshold
V
N
1.35
-
2
V
Hysteresis V
IH
0.8
-
1.2
V
Input Voltage
ID
0
, ID
1
, MOSI, SCK, CE
Positive Trigger Threshold
V
P
3.15
-
3.85
V
Negative Trigger Threshold
V
N
1.7
-
2.25
V
Hysteresis V
IH
1.3
-
1.7
V
Input Leakage Current
I
IN
-
-
1
A
Standby Device Current
I
DDS
-
1
15
A
Three-State Output Leakage Current
I
OUT
-
-
10
A
Operating Device Current
(Note 6)
I
OPER
V
IN
= V
IL
, V
IH
-
0.2
2
mA
Input Capacitance
C
IN
V
IN
= 0V, f = 1MHz, T
A
= 25
o
C
-
4
6
pF
NOTES:
5. Typical values are for T
A
= 25
o
C and nominal V
DD
.
6. Outputs open circuited; cycle time = Min, t
CYCLE
, duty = 100%.
Dynamic Electrical Specifications - Bus Timing
V
DD
10%, V
SS
= 0V DC, T
A
= -40
o
C to 85
o
C, C
L
= 200pF.
See Figures 8 and 9.
PARAMETER
SYMBOL
V
DD
= 3.3V
V
DD
= 5V
UNITS
MIN
MAX
MIN
MAX
Chip Enable Set-Up Time
t
EVCV
200
-
100
-
ns
Chip Enable after Clock Hold Time
t
CVEX
250
-
125
-
ns
Clock Width High
t
WH
400
-
200
-
ns
Clock Width Low
t
WL
400
-
200
-
ns
Data In to Clock Set-Up Time
t
DVCV
200
-
100
-
ns
Data In after Clock Hold Time
t
CVDX
200
-
100
-
ns
Clock to Data Propagation Delay
t
CVDV
-
200
-
100
ns
Chip Disable to Output High Z
t
EXQZ
-
200
-
100
ns
Output Rise Time
t
r
-
200
-
100
ns
Output Fall Time
t
f
-
200
-
100
ns
Clock to Data Out Archive
t
CVQX
-
200
-
100
ns
Clock Recovery Time
t
REC
200
-
200
-
ns
CDP68HC68P1
5
Waveforms
Introduction
The single port I/O is serially accessed via the synchronous
SPI bus. It features 8 data pins that are programmed as
inputs or outputs. Serial access consists of a two-byte
operation. The first byte shifted in is the control byte that
configures the device. The second byte transferred is the
data byte that is read from or written to the data register or
data direction register. This data byte can also be
programmed to act as a mask to set or clear individual bits.
Functional Description
The single port I/O consists of three byte-wide registers,
(data direction, data and shift) an input/output buffer and
control logic circuitry (See Figure 1). Data is transferred
between the I/O data and data direction registers via the shift
register. Once the I/O port is selected, the first byte shifted in
to the shift register is the control byte that selects the register
(the Data or Data direction register), determines data
transfer direction (read or write) and sets the compare
FIGURE 3. PORT-PIN DATA CHANGES
t
CVEX
t
REC
t
WH
t
WL
t
EVCV
t
CVDX
t
DVCV
t
CVDX
t
DVCV
t
r
, t
f
HI Z
MISO
MOSI
CE
SCK
X
C07
C06
C05
C04
C00
D7
D6
D0
X
D0
D6
D7
COMPARE FLAG
HI Z
C07
C06
FIGURE 4. READ CYCLE TIMING WAVEFORMS
t
CVEX
t
REC
t
WH
t
WL
t
EVCV
t
CVDV
t
CVQX
X
MOSI
MISO
CE
SCK
HI Z
C07
C06
COMPARE FLAG
D7
D6
D0
HI Z
X
C07
C04
t
EXQZ
C06
C05
C00
NOTE: CPOL and CPHA are bits in the CDP68HC05C4B and
CDP68HC05C16B MCU control register and determine inactive
clock polarity and phase. CPHA must always equal 1.
FIGURE 5. DATA TRANSFERS UTILIZING CLOCK INPUT
SHIFT INTERNAL
STROBE
CE
SCK
(CPOL = 1)
CE
MOSI
SCK
(CPOL = 0)
OR
MISO
SHIFT INTERNAL
STROBE
MSB
MSB - 1
CDP68HC68P1
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