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1
FN7356.0
EL5225
10-Channel TFT-LCD Reference Voltage
Generator
The EL5225 is designed to produce the reference voltages
required in TFT-LCD applications. Each output is
programmed to the required voltage with 10 bits of
resolution. Reference pins determine the high and low
voltages of the output range, which are capable of swinging
to either supply rail. Programming of each output is
performed using the 3-wire, SPI compatible interface.
A number of the EL5225 can be stacked for applications
requiring more than 10 outputs. The reference inputs can be
tied to the rails, enabling each part to output the full voltage
range, or alternatively, they can be connected to external
resistors to split the output range and enable finer
resolutions of the outputs.
The EL5225 has 10 outputs, and is available in the 24-pin
TSSOP package. They are specified for operation over the
full -40C to +85C temperature range.
Features
10-channel reference outputs
Accuracy of 1%
Supply voltage of 5V to 16.5V
Digital supply 3.3V to 5V
Low supply current of 9mA
Rail-to-rail capability
Pb-free available (RoHS compliant)
Applications
TFT-LCD drive circuits
Reference voltage generators
Ordering Information
PART
NUMBER
(See Note)
PACKAGE
(Pb-Free)
TAPE &
REEL
PKG. DWG. #
EL5225IRZ
24-Pin TSSOP
-
MDP0044
EL5225IRZ-T7
24-Pin TSSOP
7"
MDP0044
EL5225IRZ-T13
24-Pin TSSOP
13"
MDP0044
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
Pinout
EL5225
(24-PIN TSSOP)
TOP VIEW
ENA
OUTA
SDI
SCLK
SDO
EXT_OSC
VS+
VSD
REFH
REFL
VS+
GND
CAP
OUTB
OUTC
GND
OUTD
OUTE
OUTF
OUTG
GND
OUTH
OUTI
OUTJ
1
2
3
4
16
15
14
13
5
6
7
12
11
9
8
10
20
19
18
17
24
23
22
21
Data Sheet
March 11, 2004
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002-2004. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.
All other trademarks mentioned are the property of their respective owners.
2
FN7356.0
March 11, 2004
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
Absolute Maximum Ratings
(T
A
= 25C)
Supply Voltage between V
S
& GND. . . . . . . . 4.5V (min) to 18V (max)
Supply Voltage between V
SD
& GND . . 3V (min) to V
S
and 7V (max)
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
V
S
= 15V, V
SD
= 5V, V
REFH
= 13V, V
REFL
= 2V, R
L
= 1.5k
and C
L
= 200pF to 0V, T
A
= 25C, unless
otherwise specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
I
S
Supply Current
No load
9
11.5
mA
I
SD
Digital Supply Current
0.17
0.35
mA
ANALOG
V
OL
Output Swing Low
Sinking 5mA (V
REFH
= 15V, V
REFL
= 0)
50
150
mV
V
OH
Output Swing High
Sourcing 5mA (V
REFH
= 15V, V
REFL
= 0)
14.85
14.95
V
I
SC
Short Circuit Current
R
L
= 10
100
140
mA
PSRR
Power Supply Rejection Ratio
V
S
+ is moved from 14V to 16V
45
65
dB
t
D
Program to Out Delay
4
ms
V
AC
Accuracy referred to the ideal value
Code = 512
20
mV
V
MIS
Channel to Channel Mismatch
Code = 512
2
mV
V
DROOP
Droop Voltage
1
2
mV/ms
R
INH
Input Resistance @ V
REFH
, V
REFL
32
k
REG
Load Regulation
I
OUT
= 5mA step
0.5
1.5
mV/mA
CAP
Band Gap
Bypass with 0.1F
1
1.3
1.6
V
DIGITAL
V
IH
Logic 1 Input Voltage
V
SD
= 5V
4
V
V
SD
= 3.3V
2
V
F
CLK
Clock Frequency
5
MHz
V
IL
Logic 0 Input Voltage
V
SD
= 3.3V/5V
1
V
t
S
Setup Time
20
ns
t
H
Hold Time
20
ns
t
LC
Load to Clock Time
20
ns
t
CE
Clock to Load Line
20
ns
t
DCO
Clock to Out Delay Time
Negative edge of SCLK
10
ns
R
SDIN
S
DIN
Input Resistance
1
G
T
PULSE
Minimum Pulse Width for EXT_OSC
Signal
5
s
Duty Cycle
Duty Cycle for EXT_OSC Signal
50
%
INL
Integral Nonlinearity Error
1.3
LSB
DNL
Differential Nonlinearity Error
0.5
LSB
F_OSC
Internal Refresh Oscillator Frequency
OSC_Select = 0
21
kHz
EL5225
3
FN7356.0
March 11, 2004
Pin Descriptions
PIN NUMBER
PIN NAME
PIN TYPE
PIN FUNCTION
1
ENA
Logic Input
Chip select, low enables data input to logic
2
SDI
Logic Input
Serial data input
3
SCLK
Logic Input
Serial data clock
4
SDO
Logic Output
Serial data output
5
EXT_OSC
Logic Input/Output
External oscillator input or internal oscillator output
6, 10
VS+
Analog Power
Positive supply voltage for analog circuits
NC
Not connected
7
VSD
Digital Power
Positive power supply for digital circuits (3.3V - 5V)
8
REFH
Analog Reference Input
High reference voltage
9
REFL
Analog Reference Input
Low reference voltage
11
GND
Ground
Ground
12
CAP
Analog Bypass Pin
Decoupling capacitor for internal reference generator, 0.1F
13
OUTJ
Analog Output
Channel J programmable output voltage
14
OUTI
Analog Output
Channel I programmable output voltage
15
OUTH
Analog Output
Channel H programmable output voltage
17
OUTG
Analog Output
Channel G programmable output voltage
18
OUTF
Analog Output
Channel F programmable output voltage
19
OUTE
Analog Output
Channel E programmable output voltage
20
OUTD
Analog Output
Channel D programmable output voltage
22
OUTC
Analog Output
Channel C programmable output voltage
23
OUTB
Analog Output
Channel B programmable output voltage
24
OUTA
Analog Output
Channel A programmable output voltage
OUTL
Analog Output
Channel L programmable output voltage
OUTK
Analog Output
Channel K programmable output voltage
16, 21
GND
Power
Ground
EL5225
4
FN7356.0
March 11, 2004
Typical Performance Curves
FIGURE 1. DIFFERENTIAL NONLINEARITY vs CODE
FIGURE 2. INTEGRAL NONLINEARITY ERROR
FIGURE 3. TRANSIENT LOAD REGULATION (SOURCING)
FIGURE 4. TRANSIENT LOAD REGULATION (SINKING)
FIGURE 5. LARGE SIGNAL RESPONSE (RISING FROM 0V
TO 8V)
FIGURE 6. LARGE SIGNAL RESPONSE (FALLING FROM 8V
TO 0V)
10
210
410
610
810
1010
INPUT CODE
0.3
0.2
-0.2
-0.3
0
-0.1
0.1
DIFFERENTIAL NONLINE
A
R
I
TY (LSB)
V
S
=15V
V
SD
=5V
V
REFH
=13V
V
REFL
=2V
0
200
400
600
800
1200
CODE
1.5
1
-1
0
-0.5
0.5
INL
(L
SB)
1000
REF
H
=13V
REF
L
=2V
5mA
5V
0mA
C
L
=4.7nF
R
S
=20
C
L
=1nF
R
S
=20
C
L
=180pF
M=400ns/DIV
5mA/DIV
200mV/DIV
V
S
=V
REFH
=15V
5mA
0mA
200mV/DIV
V
S
=V
REFH
=15V
C
L
=180pF
C
L
=4.7nF
R
S
=20
C
L
=1nF
R
S
=20
M=400ns/DIV
M=400s/DIV
OUTPUT
SDA
SCLK
5V
0V
5V
0V
5V
0V
10V
M=400s/DIV
OUTPUT
SDA
SCLK
5V
0V
5V
0V
5V
0V
10V
EL5225
5
FN7356.0
March 11, 2004
General Description
The EL5225 provides a versatile method of providing the
reference voltages that are used in setting the transfer
characteristics of LCD display panels. The V/T
(Voltage/Transmission) curve of the LCD panel requires that
a correction is applied to make it linear; however, if the panel
is to be used in more than one application, the final curve
may differ for different applications. By using the EL5225,
the V/T curve can be changed to optimize its characteristics
according to the required application of the display product.
Each of the eight reference voltage outputs can be set with a
10-bit resolution. These outputs can be driven to within
50mV of the power rails of the EL5225. As all of the output
buffers are identical, it is also possible to use the EL5225 for
applications other than LCDs where multiple voltage
references are required that can be set to 10 bit accuracy.
Digital Interface
The EL5225 uses a simple 3-wire SPI compliant digital
interface to program the outputs. The EL5225 can support
the clock rate up to 5MHz.
Serial Interface
The EL5225 is programmed through a three-wire serial
interface. The start and stop conditions are defined by the
ENA signal. While the ENA is low, the data on the SDI (serial
data input) pin is shifted into the 16-bit shift register on the
positive edge of the SCLK (serial clock) signal. The MSB (bit
15) is loaded first and the LSB (bit 0) is loaded last (see
Table 1). After the full 16-bit data has been loaded, the ENA
is pulled high and the addressed output channel is updated.
The SCLK is disabled internally when the ENA is high. The
SCLK must be low before the ENA is pulled low.
FIGURE 7. SMALL SIGNAL RESPONSE (RISING FROM 0V
TO 200mV)
FIGURE 8. SMALL SIGNAL RESPONSE (FALLING FROM
200mV TO 0V)
FIGURE 9. POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 10. POWER DISSIPATION vs AMBIENT
TEMPERATURE
Typical Performance Curves
(Continued)
M=400s/DIV
5V
0V
5V
0V
0V
200mV
OUTPUT
SDA
SCLK
M=400s/DIV
5V
0V
5V
0V
0V
200mV
OUTPUT
SDA
SCLK
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.176W
TS
SO
P2
4
JA
=85
C
/W
0
25
50
75
100
125
AMBIENT TEMPERATURE (C)
1.4
1.2
0
0.8
0.6
1
P
O
WE
R
DI
SSI
PATIO
N
(
W
)
0.4
0.2
85
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
781mW
JA
=12
8C
/W
TS
SO
P2
4
0
25
50
75
100
125
AMBIENT TEMPERATURE (C)
0.9
0.8
0.6
0.5
0.7
P
O
WE
R
DI
SSI
PATIO
N
(
W
)
0.4
0.2
85
0
0.3
0.1
EL5225
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