www.docs.chipfind.ru
1
FN7005.4
EL5825
8-Channel TFT-LCD Reference Voltage
Generator
The EL5825 is designed to produce the reference voltages
required in TFT-LCD applications. Each output is
programmed to the required voltage with 10 bits of
resolution. Reference pins determine the high and low
voltages of the output range, which are capable of swinging
to either supply rail. Programming of each output is
performed using the serial interface. A serial out pin enables
daisy chaining of multiple devices.
A number of the EL5825 can be stacked for applications
requiring more than 8 outputs. The reference inputs can be
tied to the rails, enabling each part to output the full voltage
range, or alternatively, they can be connected to external
resistors to split the output range and enable finer
resolutions of the outputs.
The EL5825 has 8 outputs and is available in both the 24-pin
TSSOP and the 24-pin QFN packages. It is specified for
operation over the full -40C to +85C temperature range.
Features
8-channel reference outputs
Accuracy of 0.1%
Supply voltage of 4.5V to 16.5V
Digital supply 3.3V to 5V
Low supply current of 8mA
Rail-to-rail capability
Pb-Free plus anneal available (RoHS compliant)
Applications
TFT-LCD drive circuits
Reference voltage generators
Pinouts
Ordering Information
PART
NUMBER
PACKAGE
TAPE & REEL PKG. DWG. #
EL5825IL
24-Pin QFN
-
MDP0046
EL5825IL-T7
24-Pin QFN
7"
MDP0046
EL5825IL-T13
24-Pin QFN
13"
MDP0046
EL5825ILZ
(See Note)
24-Pin QFN
(Pb-free)
-
MDP0046
EL5825ILZ-T7
(See Note)
24-Pin QFN
(Pb-free)
7"
MDP0046
EL5825ILZ-T13
(See Note)
24-Pin QFN
(Pb-free)
13"
MDP0046
EL5825IR
24-Pin TSSOP
-
MDP0044
EL5825IR-T7
24-Pin TSSOP
7"
MDP0044
EL5825IR-T13
24-Pin TSSOP
13"
MDP0044
EL5825IRZ
(See Note)
24-Pin TSSOP
(Pb-free)
-
MDP0044
EL5825IRZ-T7
(See Note)
24-Pin TSSOP
(Pb-free)
7"
MDP0044
EL5825IRZ-T13
(See Note)
24-Pin TSSOP
(Pb-free)
13"
MDP0044
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
SCLK
SDO
OSC
VSD
NC
VS
REFH
REFL
GND
NC
CAP
NC
SDI
ENA
OUTA
OUTB
OUTC
OUTD
GND
OUTE
OUTF
OUTG
OUTH
NC
EL5825
(24-PIN TSSOP)
TOP VIEW
1
2
3
4
16
15
14
13
5
6
7
12
11
9
8
10
20
19
18
17
24
23
22
21
EL5825
(24-PIN QFN)
TOP VIEW
19
18
17
16
15
14
13
24
23
22
21
20
8
9
10
11
12
1
2
3
4
5
6
7
Thermal Pad
OSC
VSD
NC
VS
REFH
REFL
GND
OUTB
OUTC
OUTD
GND
OUTE
OUTF
OUTG
SD
O
SC
LK
SD
I
EN
A
OUTA
CAP
NC
NC
NC
OU
T
H
THERMAL
PAD
Data Sheet
June 24, 2005
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2
FN7005.4
June 24, 2005
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
Absolute Maximum Ratings
(T
A
= 25C)
Supply Voltage between V
S
and GND. . . . . . . . . . . . . . . . . . . .+18V
Supply Voltage between V
SD
and GND . . . . . . . V
S
and +7V (max)
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 125C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
V
S
= 15V, V
SD
= 5V, V
REFH
= 13V, V
REFL
= 2V,
R
L
= 1.5k
and
C
L
= 200pF to 0V, T
A
= 25C, unless
otherwise specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
I
S
Supply Current
No load
7.6
9
mA
I
SD
Digital Supply Current
0.17
0.35
mA
ANALOG
V
OL
Output Swing Low
Sinking 5mA (V
REFH
= 15V, V
REFL
= 0)
50
150
mV
V
OH
Output Swing High
Sourcing 5mA (V
REFH
= 15V, V
REFL
= 0)
14.85
14.95
V
I
SC
Short Circuit Current
R
L
= 10
100
140
mA
PSRR
Power Supply Rejection Ratio
V
S
+ is moved from 14V to 16V
45
60
dB
t
D
Program to Out Delay
4
ms
V
AC
Accuracy
20
mV
V
DROOP
Droop Voltage
1
2
mV/ms
R
INH
Input Resistance @ V
REFH
, V
REFL
34
k
REG
Load Regulation
I
OUT
= 5mA step
0.5
1.5
mV/mA
BG
Band Gap
1.1
1.3
1.6
V
DIGITAL
V
IH
Logic 1 Input Voltage
V
SD
-
20%
V
V
IL
Logic 0 Input Voltage
20%*
V
SD
V
F
CLK
Clock Frequency
5
MHz
t
S
Setup Time
20
ns
t
H
Hold Time
20
ns
t
LC
Load to Clock Time
20
ns
t
CE
Clock to Load Line
20
ns
t
DCO
Clock to Out Delay Time
Negative edge of SCLK
10
ns
R
SDIN
S
DIN
Input Resistance
1
G
EL5825
3
FN7005.4
June 24, 2005
Pin Descriptions
24-PIN QFN
24-PIN TSSOP
PIN NAME
PIN TYPE
PIN DESCRIPTION
1
3
OSC
IP/OP
Oscillator pin for synchronizing multiple chips
2
4
VSD
Power
Positive power supply for digital circuits (3.3V - 5V)
3
5
NC
Not connected
4
6
VS
Power
Positive supply voltage for analog circuits
5
7
REFH
Analog Input
High reference voltage
6
8
REFL
Analog Input
Low reference voltage
7
9
GND
Power
Ground
8
11
CAP
Analog
Decoupling capacitor for internal reference generator, 0.1F
9
10
NC
Not connected
10
12
NC
Not connected
11
13
NC
Not connected
12
14
OUTH
Analog Output
Channel H programmable output voltage
13
15
OUTG
Analog Output
Channel G programmable output voltage
14
16
OUTF
Analog Output
Channel F programmable output voltage
15
17
OUTE
Analog Output
Channel E programmable output voltage
16
18
GND
Power
Ground
17
19
OUTD
Analog Output
Channel D programmable output voltage
18
20
OUTC
Analog Output
Channel C programmable output voltage
19
21
OUTB
Analog Output
Channel B programmable output voltage
20
22
OUTA
Analog Output
Channel A programmable output voltage
21
23
ENA
Logic Input
Chip select, low enables data input to logic
22
24
SDI
Logic Input
Serial data input
23
1
SCLK
Logic Input
Serial data clock
24
2
SDO
Logic Output
Serial data output
EL5825
4
FN7005.4
June 24, 2005
Typical Performance Curves
FIGURE 1. DIFFERENTIAL NONLINEARITY vs CODE
FIGURE 2. DIGITAL SUPPLY CURRENT vs DIGITAL SUPPLY
VOLTAGE
FIGURE 3. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 4. TRANSIENT LOAD REGULATION (SOURCING)
FIGURE 5. TRANSIENT LOAD REGULATION (SINKING)
FIGURE 6. LARGE SIGNAL RESPONSE (RISING FROM 0V
TO 8V)
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
10
210
410
610
810
1010
INPUT CODE
DIFFE
RE
NTIAL NO
N
L
I
N
EAR
I
TY
(LS
B
)
V
S
=15V
V
SD
=5V
V
REFH
=13V
V
REFL
=2V
180
140
100
60
40
20
0
3
3.5
4
4.5
5
5.5
V
SD
(V)
I
SD
(n
A
)
160
120
80
7.2
7
6.6
6.2
6
5.8
5.6
4
6
8
12
14
16
18
V
S
(V)
I
S
(mA)
V
OUT
=0V
6.8
6.4
10
0mA
5V
5mA/DIV
200mV/DIV
5mA
C
L
=180pF
C
L
=4.7nF
R
S
=20
C
L
=1nF
R
S
=20
V
S
=V
REFH
=15V
M=400ns/DIV
5mA
0mA
C
L
=1nF
R
S
=20
C
L
=180pF
V
S
=V
REFH
=15V
M=400ns/DIV
C
L
=4.7nF
R
S
=20
SCLK
SDA
ENA
OUTA
M=200s/DIV
EL5825
5
FN7005.4
June 24, 2005
FIGURE 7. SMALL SIGNAL RESPONSE (FALLING FROM 200mV TO 100mV)
FIGURE 8. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 9. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 10. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 11. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Typical Performance Curves
(Continued)
SCLK
SDA
ENA
OUTA
M=200s/div
1.4
0
AMBIENT TEMPERATURE (C)
P
O
WE
R DISS
IP
ATIO
N
(
W
)
1.2
1
0.8
0.6
0.4
0.2
0
25
50
75
100
125
85
1.176W
JA =8
5C
/W
TS
SO
P24
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
25
50
75
100
125
AMBIENT TEMPERATURE (C)
POWE
R DIS
S
IP
ATION (W)
85
781mW
JA =
128
C/
W
TS
SO
P24
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
3
2.5
2
1.5
1
0.5
0
0
25
50
75
100
150
AMBIENT TEMPERATURE (C)
POWE
R DIS
S
IP
ATION
(
W
)
2.703W
JA =
37
C
/W
QF
N2
4
125
85
JEDEC JESD51-3 AND SEMI G42-88 (SINGLE
LAYER) TEST BOARD
0.8
0.7
0.5
0.3
0.2
0.1
0
0
25
50
75
100
150
AMBIENT TEMPERATURE (C)
P
O
WE
R DISS
IPA
T
I
O
N (W
)
714mW
JA =
14
0C
/W
QF
N2
4
125
85
0.6
0.4
EL5825
PDF 
ZIP