FN7450.1

EL9111, EL9112

Triple Differential Receiver/Equalizer

The EL9111 and EL9112 are triple channel differential
receivers and equalizers. They contains three high speed
differential receivers with five programmable poles. The
outputs of these pole blocks are then summed into an output
buffer. The equalization length is set with the voltage on a
single pin. The EL9111 and EL9112 also contain a 3-statable
output, enabling multiple devices to be connected in parallel
and used in a multiplexing application.

The gain can be adjusted up or down on each channel by
6dB using its V

GAIN

control signal. In addition, a further 6dB

of gain can be switched in to provide a matched drive into a
cable.

The EL9111 and EL9112 have a bandwidth of 150MHz and
consume just 108mA on ±5V supply. A single input voltage is
used to set the compensation levels for the required length
of cable.

The EL9111 is a special version of the EL9112 that decodes
syncs encoded onto the common modes of three pairs of
CAT-5 cable by the EL4543. (Refer to the EL4543 datasheet
for details.)

The EL9111 and EL9112 are available in a 28-pin QFN
package and are specified for operation over the full -40°C to
+85°C temperature range.

Features

· 150MHz -3dB bandwidth

· CAT-5 compensation

- 50MHz @ 1000 ft
- 125MHz @ 500 ft

· 108mA supply current

· Differential input range 3.2V

· Common mode input range -4V to +3.5V

· ±5V supply

· Output to within 1.5V of supplies

· Available in 28-pin QFN package

· Pb-free available (RoHS compliant)

Applications

· Twisted-pair receiving/equalizer

· KVM (Keyboard/Video/Mouse)

· VGA over twisted-pair

· Security video

Pinouts

EL9111

(28-PIN QFN)

TOP VIEW

EL9112

(28-PIN QFN)

TOP VIEW

THERMAL

PAD

VSMO_B

VOUT_B

VSPO_B

VSPO_G

VOUT_G

VSMO_G

VSMO_R

VSP

VINM_B

VINP_B

VINM_G

VINP_G

VINM_R

VINP_R

ENABL

SYNCREF

VOUT

SPO

VCTRL

AIN_R

VGAIN_G

VSM

AIN_B

VOUT_R

THERMAL

PAD

VSMO_B

VOUT_B

VSPO_B

VSPO_G

VOUT_G

VSMO_G

VSMO_R

VSP

VINM_B

VINP_B

VINM_G

VINP_G

VINM_R

VINP_R

ENABL

VCM_B

VCM_G

SPO

VCTRL

AIN_R

VGAIN_G

VSM

AIN_B

VOUT_R

VCM_R

Data Sheet

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-352-6832

Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

May 17, 2005

FN7450.1

May 17, 2005

Ordering Information

PART

NUMBER

PACKAGE

TAPE &

REEL

PKG. DWG. #

PART

NUMBER

PACKAGE

TAPE &

REEL

PKG. DWG. #

EL9111IL

28-Pin QFN

MDP0046

EL9112IL

28-Pin QFN

MDP0046

EL9111IL-T7

28-Pin QFN

MDP0046

EL9112IL-T7

28-Pin QFN

MDP0046

EL9111IL-T13

28-Pin QFN

13"

MDP0046

EL9112IL-T13

28-Pin QFN

13"

MDP0046

EL9111ILZ
(Note)

28-Pin QFN

(Pb-Free)

MDP0046

EL9112ILZ
(Note)

28-Pin QFN

(Pb-Free)

MDP0046

EL9111ILZ-T7
(Note)

28-Pin QFN

(Pb-Free)

MDP0046

EL9112ILZ-T7
(Note)

28-Pin QFN

(Pb-Free)

MDP0046

EL9111ILZ-T13
(Note)

28-Pin QFN

(Pb-Free)

13"

MDP0046

EL9112ILZ-T13
(Note)

28-Pin QFN

(Pb-Free)

13"

MDP0046

NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-
free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

EL9111, EL9112

FN7450.1

May 17, 2005

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T

= T

Absolute Maximum Ratings

= 25°C)

Supply Voltage between V

+ and V

- . . . . . . . . . . . . . . . . . . . . .12V

Maximum Continuous Output Current per Channel. . . . . . . . . 30mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . V

- -0.5V to V

+ +0.5V

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Die Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Electrical Specifications

= V

= +5V, V

= V

= -5V, T

= 25°C, unless otherwise specified.

PARAMETER

DESCRIPTION

CONDITIONS

MIN

TYP

MAX

UNIT

AC PERFORMANCE

Bandwidth

(See Figure 1)

150

MHz

Slew Rate

= -1V to +1V, V

= 0.39, V

= 0,

= 75 + 75

1.5

kV/µs

THD

Total Harmonic Distortion

10MHz 2V

P-P

out, V

= 1V, X2 gain, V

= 0

-50

dBc

DC PERFORMANCE

V(V

OUT

)

Offset Voltage

X2 = high, no equalization

-110

-10

+78

Channel-to-Channel Offset Matching X2 = high, no equalization

-100

+100

INPUT CHARACTERISTICS

CMIR

Common-mode Input Range

-4/+3.5

NOISE

Output Noise

= 0V, V

= 0V, X2 = HIGH, R

LOAD

= 150

Input 50

to GND, 10MHz

-110

dBm

CMRR

Common-mode Rejection Ratio

Measured at 10kHz

-80

CMRR

Common-mode Rejection Ratio

Measured at 10MHz

-55

CMBW

CM Amplifier Bandwidth

10K || 10pF load

MHz

SLEW

CM Slew Rate

Measured @ +1V to -1V

100

V/µs

INDIFF

Differential Input Capacitance

Capacitance V

INP

to V

INM

600

INDIFF

Differential Input Resistance

Resistance V

INP

to V

INM

2.4

INCM

CM Input Capacitance

Capacitance V

INP

= V

INM

to GND

1.2

INCM

CM Input Resistance

Resistance V

INP

= V

INM

to GND

2.8

Positive Input Current

DC bias @ V

INP

= V

INM

= 0V

µA

-I

Negative Input Current

DC bias @ V

INP

= V

INM

= 0V

µA

INDIFF

Differential Input Range

INP

- V

INM

when slope gain falls to 0.9

2.5

3.2

OUTPUT CHARACTERISTICS

V(V

OUT

)

Output Voltage Swing

= 150

±3.5

I(V

OUT

)

Output Drive Current

= 10

, V

INP

= 1V, V

INM

= 0V, X2 = high,

= 0.39

R(V

)

CM Output Resistance of
VCM_R/G/B (EL9112 only)

at 100kHz

Gain

= 0, V

= 0.39, X2 = 5, R

= 150

0.85

1.0

1.1

Gain

Channel-to-Channel Gain Matching

= 0, V

= 0.39, X2 = 5, R

= 150

V(SYNC)

High Level output on V/H

OUT

(EL9111 only)

V(V

)

- 0.1V

V(V

)

EL9111, EL9112

FN7450.1

May 17, 2005

V(SYNC)

Low Level output on V/H

OUT

(EL9111 only)

V(SYNC

REF)

+ 0.1V

SUPPLY

SON

Supply Current per Channel

ENBL

= 5, V

INM

= 0

SOFF

Supply Current per Channel

ENBL

= 0, V

INM

= 0

0.2

0.4

PSRR

Power Supply Rejection Ratio

DC to 100kHz, ±5V supply

LOGIC CONTROL PINS (ENABLE, X2)

Logic High Level

- V

LOGIC

ref for guaranteed high level

1.35

LOW

Logic Low Level

- V

LOGIC

ref for guaranteed low level

0.8

LOGICH

Logic High Input Current

= 5V, V

LOGIC

= 0V

µA

LOGICL

Logic Low Input Current

= 0V, V

LOGIC

= 0V

µA

Electrical Specifications

= V

= +5V, V

= V

= -5V, T

= 25°C, unless otherwise specified. (Continued)

PARAMETER

DESCRIPTION

CONDITIONS

MIN

TYP

MAX

UNIT

Pin Descriptions

PIN

NUMBER

EL9111IL

PIN NAME

EL9111IL

PIN FUNCTION

EL9112IL

PIN NAME

EL9112IL

PIN FUNCTION

VSMO_B

-5V to blue output buffer

VSMO_B

-5V to blue output buffer

VOUT_B

Blue output voltage referenced to 0V pin

VOUT_B

Blue output voltage referenced to 0V pin

VSPO_B

+5V to blue output buffer

VSPO_B

+5V to blue output buffer

VSPO_G

+5V to green output buffer

VSPO_G

+5V to green output buffer

VOUT_G

Green output voltage referenced to 0V pin

VOUT_G

Green output voltage referenced to 0V pin

VSMO_G

-5V to green output buffer

VSMO_G

-5V to green output buffer

VSMO_R

-5V to red output buffer

VSMO_R

-5V to red output buffer

VOUT_R

Red output voltage referenced to 0V pin

VOUT_R

Red output voltage referenced to 0V pin

VSPO_R

+5V to red output buffer

VSPO_R

+5V to red output buffer

VCTRL

Equalization control voltage (0V to 1V)

VCTRL

Equalization control voltage (0V to 1V)

VREF

Reference voltage for logic signals, V

CTRL

and

GAIN

pins

VREF

Reference voltage for logic signals, V

CTRL

and

GAIN

pins

VGAIN_R

Red channel gain voltage (0V to 1V)

VGAIN_R

Red channel gain voltage (0V to 1V)

VGAIN_G

Green channel gain voltage (0V to 1V)

VGAIN_G

Green channel gain voltage (0V to 1V)

VGAIN_B

Blue channel gain voltage (0V to 1V)

VGAIN_B

Blue channel gain voltage (0V to 1V)

VSM

-5V to core of chip

VSM

-5V to core of chip

VINP_R

Red positive differential input

VINP_R

Red positive differential input

VINM_R

Red negative differential input

VINM_R

Red negative differential input

VINP_G

Green positive differential input

VINP_G

Green positive differential input

VINM_G

Green negative differential input

VINM_G

Green negative differential input

VINP_B

Blue positive differential input

VINP_B

Blue positive differential input

VINM_B

Blue negative differential input

VINM_B

Blue negative differential input

VSP

+5V to core of chip

VSP

+5V to core of chip

HOUT

Decoded Horizontal sync referenced to
SYNCREF

VCM_R

Red common-mode voltage at inputs

VOUT

Decoded Vertical sync referenced to SYNCREF

VCM_G

Green common-mode voltage at inputs

SYNCREF

Reference level for H

OUT

and V

OUT

logic outputs

VCM_B

Blue common-mode voltage at inputs

EL9111, EL9112

FN7450.1

May 17, 2005

FIGURE 11. COMMON-MODE REJECTION

FIGURE 12. CM AMPLIFIER BANDWIDTH

FIGURE 13. (+)PSRR vs FREQUENCY

FIGURE 14. (-)PSRR vs FREQUENCY

FIGURE 15. BLUE CROSSTALK

FIGURE 16. BLUE CROSSTALK

Typical Performance Curves

(Continued)

100K

10M

100M

-10

-20

-40

-60

-80

-100

GAIN

=0.35V

(ALL CHANNELS)
V

CTRL

=0V

=HIGH

FREQUENCY (Hz)

CMRR (dB)

100K

10M

100M

-2

-4

-6

GAIN

=0.35V

(ALL CHANNELS)
V

CTRL

=0V

LOAD

=150

=HIGH

FREQUENCY (Hz)

IN (

100K

100M

-20

-40

-60

-80

-100

=5V

CTRL

=0V

GAIN

=0V

(ALL CHANNELS)
INPUTS ON GND

FREQUENCY (Hz)

+PSRR (dB)

100

10K

10M

100K

100M

-20

-40

-60

-80

-100

-120

=-5V

CTRL

=0V

GAIN

=0V

(ALL CHANNELS)
INPUTS ON GND

FREQUENCY (Hz)

-P

SRR (dB

)

100

10K

10M

EL9111, EL9112

FN7450.1

May 17, 2005

Applications Information

Logic Control

The EL9112 has two logical input pins, Chip Enable
(ENABLE) and Switch Gain (X2). The logic circuits all have a
nominal threshold of 1.1V above the potential of the logic
reference pin (VREF). In most applications it is expected that
this chip will run from a +5V, 0V, -5V supply system with logic
being run between 0V and +5V. In this case the logic
reference voltage should be tied to the 0V supply. If the logic
is referenced to the -5V rail, then the logic reference should
be connected to -5V. The logic reference pin sources about
60µA and this will rise to about 200µA if all inputs are true
(positive).

The logic inputs all source up to 10µA when they are held at
the logic reference level. When taken positive, the inputs
sink a current dependent on the high level, up to 50µA for a
high level 5V above the reference level.

The logic inputs, if not used, should be tied to the
appropriate voltage in order to define their state.

Control Reference and Signal Reference

Analog control voltages are required to set the equalizer and
contrast levels. These signals are voltages in the range 0V -
1V, which are referenced to the control reference pin. It is
expected that the control reference pin will be tied to 0V and
the control voltage will vary from 0V to 1V. It is; however,
acceptable to connect the control reference to any potential
between -5V and 0V to which the control voltages are
referenced.

The control voltage pins themselves are high impedance.
The control reference pin will source between 0µA and
200µA depending on the control voltages being applied.

The control reference and logic reference effectively remove
the necessity for the 0V rail and operation from ±5V (or 0V
and 10V) only is possible. However we still need a further
reference to define the 0V level of the single ended output
signal. The reference for the output signal is provided by the
0V pin. The output stage cannot pull fully up or down to
either supply so it is important that the reference is
positioned to allow full output swing. The 0V reference
should be tied to a 'quiet ground' as any noise on this pin is
transferred directly to the output. The 0V pin is a high
impedance pin and draws dc bias currents of a few µA and
similar levels of AC current.

Equalizing

When transmitting a signal across a twisted pair cable, it is
found that the high frequency (above 1MHz) information is
attenuated more significantly than the information at low
frequencies. The attenuation is predominantly due to
resistive skin effect losses and has a loss curve which
depends on the resistivity of the conductor, surface condition
of the wire and the wire diameter. For the range of high

performance twisted pair cables based on 24awg copper
wire (CAT-5 etc.) these parameters vary only a little between
cable types, and in general cables exhibit the same
frequency dependence of loss. (The lower loss cables can
be compared with somewhat longer lengths of their more
lossy brothers.) This enables a single equalizing law
equation to be built into the EL9112.

With a control voltage applied between pins V

CTRL

and

REF

, the frequency dependence of the equalization is

shown in Figure 8. The equalization matches the cable loss
up to about 100MHz. Above this, system gain is rolled off
rapidly to reduce noise bandwidth. The roll-off occurs more
rapidly for higher control voltages, thus the system (cable +
equalizer) bandwidth reduces as the cable length increases.
This is desirable, as noise becomes an increasing issue as
the equalization increases.

Contrast

By varying the voltage between pins V

GAIN

and V

REF

, the

gain of the signal path can be changed in the ratio 4:1. The
gain change varies almost linearly with control voltage. For
normal operation it is anticipated the X2 mode will be
selected and the output load will be back matched. A unity
gain to the output load will then be achieved with a gain
control voltage of about 0.35V. This allows the gain to be
trimmed up or down by 6dB to compensate for any gain/loss
errors that affect the contrast of the video signal. Figure 26
shows an example plot of the gain to the load with gain
control voltage.

FIGURE 26. VARIATION OF GAIN WITH GAIN CONTROL

VOLTAGE

ommon Mode Sync Decoding

The EL9111 features common mode decoding to allow
horizontal and vertical synchronization information, which
has been encoded on the three differential inputs by the
EL4543, to be decoded. The entire RGB video signal can
therefore be transmitted, along with the associated
synchronization information, by using just three twisted
pairs.

0.8

GAIN

0.4

1.8

1.4

0.6

0.4

GAI

(

)

0.6

0.2

1.6

1.2

0.8

EL9111, EL9112

FN7450.1

May 17, 2005

Decoding is based on the EL4543 encoding scheme, as
described in Figure 27 and Table 1. The scheme is a three-
level system, which has been designed such that the sum of
the common mode voltages results in a fixed average DC
level with no AC content. This eliminates the effect of EMI
radiation into the common mode signals along the twisted
pairs of the cable

The common mode voltages are initially extracted by the
EL9111 from the three input pairs. These are then passed to
an internal logic decoding block to provide Horizontal and
Vertical sync output signals (H

OUT

and V

OUT

FIGURE 27. H & V SYNCS ENCODED

TABLE 1. H AND V SYNC DECODING

RED CM

GREEN CM

BLUE CM

SYNC

Mid

High

Low

High

Low

Mid

Low

High

Low

High

Mid

High

Low

Mid

Low

High

High High

NOTE: Level `Mid' is halfway between `High' and `Low'

TIME (0.5ms/DIV)

VOLTA

(0.

DIV

)

BLUE CM
OUT (CH A)

GREEN CM
OUT (CH B)

RED CM
OUT (CH C)

SYNC

LTA

(2.

DIV

)

EL9111, EL9112

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7450.1

May 17, 2005

Package Outline Drawing

NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
http://www.intersil.com/design/packages/index.asp

EL9111, EL9112

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: EL9112ILZ-T7

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: EL9112ILZ-T7