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1
FN7441.2
EL9115
Triple Analog Video Delay Line
The EL9115 is a triple analog delay line that allows skew
compensation between any three signals. This part is perfect
for compensating for the skew introduced by a typical CAT-5
cable with differing electrical lengths on each pair.
The EL9115 can be programmed in steps of 2ns up to 62ns
total delay on each channel.
Features
62ns total delay
2ns delay step increments
Operates from 5V supply
Up to 122MHz bandwidth
Low power consumption
20-pin QFN (5mm x 5mm) package
Pb-Free plus anneal available (RoHS compliant)
Applications
Skew control for RGB
Analog beamforming
Pinout
EL9115
[20-PIN QFN (5MM X 5MM)]
TOP VIEW
Ordering Information
PART NUMBER
PACKAGE
TAPE &
REEL
PKG. DWG. #
EL9115IL
20-Pin QFN
(5mm x 5mm)
-
MDP0046
EL9115IL-T7
20-Pin QFN
(5mm x 5mm)
7"
MDP0046
EL9115IL-T13
20-Pin QFN
(5mm x 5mm)
13"
MDP0046
EL9115ILZ
(See Note)
20-Pin QFN
(5mm x 5mm)
(Pb-Free)
-
MDP0046
EL9115ILZ-T7
(See Note)
20-Pin QFN
(5mm x 5mm)
(Pb-Free)
7"
MDP0046
EL9115ILZ-T13
(See Note)
20-Pin QFN
(5mm x 5mm)
(Pb-Free)
13"
MDP0046
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
EXPOSED DIEPLATE SHOULD BE CONNECTED TO -5V
1
2
3
4
15
14
13
12
6
7
8
9
20
19
18
17
VSP
RIN
GND
GIN
BIN
CENABLE
NSENABLE
SDA
T
A
X2
DELAYR
DELAYG
DELAYB
ROUT
GNDO
GOUT
VSMO
THERMAL
PAD
5
VSM
10
SCLOCK
11 BOUT
1
6
VS
PO
Data Sheet
September 8, 2005
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2
FN7441.2
September 8, 2005
Absolute Maximum Ratings
(T
A
= 25C)
Supply Voltage (V
S
+ to V
S
-) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60mA
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
DC Electrical Specifications
V
SA
+
= V
A
+
= +5V, V
SA
-
= V
A
-
= -5V, T
A
= 25C, exposed die plate = -5V, unless otherwise specified.
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
V+
Positive Supply Range
+4.5
+5.5
V
V-
Negative Supply Range
-4.5
-5.5
V
G_0
Gain Zero Delay
X2 = 5V, 150
load
1.81
1.89
2.04
G_m
Gain Mid Delay
1.66
1.84
2.04
G_f
Gain Full Delay
1.52
1.79
2.04
DG_m0
Difference in Gain, 0 - Mid
-7.5
-2.5
2.5
%
DG_f0
Difference in Gain, 0 - Full
-13.5
-6.0
2.5
%
DG_fm
Difference in Gain, Mid - Full
-10.0
-2.6
4.0
%
V
IN
Input Voltage Range
Gain falls to 90% of nominal
-0.7
1.3
V
V
OUT
Output Voltage Range
X2 = +5V into 150
load
-5
1.6
V
I
B
Input Bias Current
1
5
A
R
IN
Input Resistance
10
M
V
OS_0
Output Offset 0 Delay
X2 = +5V, 75 + 75
load
-200
-150
60
mV
V
OS_M
Output Offset full Delay
-200
-140
60
mV
V
OS_F
Output Offset mid Delay
-200
-130
60
mV
Z
OUT
Output Impedance
Chip enable = +5V
4.5
4.8
5.1
Chip enable = 0V
1
M
+PSRR
Rejection of Positive Supply
X2 = +5V into 75 + 75
load
-38
dB
-PSRR
Rejection of Negative Supply
X2 = +5V into 75 + 75
load
-53
dB
I
SP
Supply Current (Note 1)
Chip enable = +5V current on V
SP
75
87
115
mA
I
SM
Supply Current (Note 1)
Chip enable = +5V current in V
SM
-10.5
-8.6
-7
mA
I
SMO
Supply Current (Note 1)
Chip enable = +5V current in V
SMO
-13
-11.6
-10
mA
I
SPO
Supply Current (Note 1)
Chip enable = +5V current in V
SPO
10
11.8
15.5
I
SP
Supply Current (Note 1)
Increase in I
SP
per unit step in delay
0.9
mA
I
SP OFF
Supply Current (Note 1)
Chip enable = 0V current in V
SP
1.6
mA
I
OUT
Output Drive Current
10
load, 0.5V drive, X2 = 5V
30
mA
L
HI
Logic High
Switch high threshold
1.25
1.6
V
L
LO
Logic Low
Switch low threshold
0.8
1.15
V
NOTE:
1. All supply currents measured withe Delay R = 0ns, G = mid delay, B = full delay.
EL9115
3
FN7441.2
September 8, 2005
AC Electrical Specifications
V
SA
+
= V
A
+
= +5V, V
SA
-
= V
A
-
= -5V, T
A
= 25C, exposed die plate = -5V, unless otherwise specified.
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
BW -3dB
3 dB Bandwidth
0ns Delay Time
122
MHz
BW 0.1dB
0.1dB Bandwidth
0ns Delay Time
60
MHz
SR
Slew Rate
0ns Delay Time
400
V/s
T
R
- T
F
Transient Response Time
20% - 80%, for all delays, 1V step
2.5
ns
V
OVER
Voltage Overshoot
for any delay, response to 1V step input
5
10
%
Glitch
Switching Glitch
Time for o/p to settle after last s_clock edge
100
ns
THD
Total Harmonic Distortion
1V
P-P
10MHz sinewave, offset by +0.2V at
mid delay setting
-50
-40
dB
X
T
Hostile Crosstalk
Stimulate G, measure R/B at 1MHz
-80
dB
V
N
Output Noise
Gain X2, measured at 75
load
2.5
mV rms
d
T
Delay Increment
1.75
2
2.25
ns
T
MAX
Maximum Delay
55
62
70
ns
D
ELDT
Delay Diff Between Channels
1.6
%
t
PD
Propagation Delay
Measured input to output
8.5
9.8
11
ns
T
MAX
Max s_clock Frequency
Maximum programming clock speed
10
MHz
T_en_ck
Minimum Separation Between Serial
Enable and Clock .
Check enable low edge can occur after
T_en_ck of previous (igored) clock and up to
before T_en_ck of next (wanted) clock. Clock
edges occurring within T_en_ck of the enable
edge will have ncertain effect.
10
ns
Pin Descriptions
PIN NUMBER
PIN NAME
PIN DESCRIPTION
1
VSP
+5V for delay circuitry and input amp
2
RIN
Red channel input, ref GND
3
GND
0V for delay circuitry supply
4
GIN
Green channel input, ref GND
5
VSM
-5V for input amp
6
BIN
Blue channel input, ref GND
7
CENABLE
Chip enable logical +5V enables chip
8
NSENABLE
ENABLE for serial input; enable on low
9
SDATA
Data into registers; logic threshold 1.2V
10
SCLOCK
Clock to enter data; logical; data written on negative edge
11
BOUT
Blue channel output, ref GND
O
12
VSMO
-5V for output buffers
13
GOUT
Green channel output, ref GND
O
14
GNDO
0V reference for input and output buffers
15
ROUT
Red channel output, ref GND
O
16
VSPO
+5V for output buffers
17
TESTB
Blue channel phase detector output
18
TESTG
Green channel phase detector output
19
TESTR
Red channel phase detector output
20
X2
Sets gain to 2X if input high; X1 otherwise
Thermal Pad
Must be connected to -5V
EL9115
4
FN7441.2
September 8, 2005
Typical Performance Curves
FIGURE 1. GAIN vs FREQUENCY
FIGURE 2. GAIN vs FREQUENCY
FIGURE 3. TYPICAL DC OFFSET vs DELAY TIME (X2 = Hi)
FIGURE 4. TYPICAL DC OFFSET vs DELAY TIME (X2 = Low)
FIGURE 5. RISE TIME vs DELAY TIME
FIGURE 6. FALL TIME vs DELAY TIME
Delay 10, 20, 30, 40 and 50ns
Delay = 62ns
-3dB@80MHz
Delay = 0ns
-3dB@122MHz
Delay = 0ns
Delay = 62ns
Delay 10, 20, 30, 40 and 50ns
DELAY TIME (ns)
DELAY TIME (ns)
DELAY TIME (ns)
DELAY TIME (ns)
DELAY TIME (ns)
EL9115
5
FN7441.2
September 8, 2005
FIGURE 7. DISTORTION vs FREQUENCY
FIGURE 8. POSITVE SUPPLY CURRENT vs DELAY TIME
FIGURE 9. I
SUPPLY
+ vs V
SUPPLY
+
FIGURE 10. I
SUPPLY
- vs V
SUPPLY
-
FIGURE 11. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 12. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Typical Performance Curves
Vout = 1Vptp
DELAY TIME (ns)
3 Channels
X2 Low_0ns Delay
X2 Low_62ns Delay
X2 Hi_62ns Delay
X2 Hi_0ns Delay
X2 Low_0ns Delay
X2 Low_62ns Delay
X2 Hi_62ns Delay
X2 Hi_0ns Delay
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.2
1
0.8
0.6
0.4
0.2
0
0
25
50
75
100
150
AMBIENT TEMPERATURE (C)
POWE
R DI
SSI
PATI
ON
(W)
833mW
JA
=15
0C
/W
QFN
20
125
85
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
3.125W
JA
=40
C/W
QFN
20
4.5
4
3.5
3
2
1
0
0
25
50
75
100
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