1
TM
Microprocessor CORE Voltage Regulator
Two-Phase Buck PWM Controller
The ISL6562 two-phase current mode, PWM control IC
together with companion gate drivers, the HIP6601A,
HIP6602A, HIP6603A or HIP6604 and MOSFETs provides a
precision voltage regulation system for advanced
microprocessors. Two-phase power conversion is a marked
departure from earlier single phase converter configurations
previously employed to satisfy the ever increasing current
demands of modern microprocessors. Multi-phase
converters, by distributing the power and load current results
in smaller and lower cost transistors with fewer input and
output capacitors. These reductions accrue from the higher
effective conversion frequency with higher frequency ripple
current due to the phase interleaving process of this
topology. For example, a two phase converter operating at
350kHz per phase will have a ripple frequency of 700kHz.
Moreover, greater converter bandwidth of this design results
in faster response to load transients.
Outstanding features of this controller IC include
programmable VID codes from the microprocessor that
range from 1.050V to 1.825V with an accuracy of
0.8%.
Pull up currents on these VID pins eliminates the need for
external pull up resistors.
Another feature of this controller IC is the PWRGD monitor
circuit which is held low until the CORE voltage increases, to
within 18% of the programmed voltage. Over-voltage, 24%
above programmed CORE voltage, results in the PWRGD
output going low to indicate that the CORE is above the
specified limit. Under voltage is also detected and results in
PWRGD going low if the CORE voltage falls 18% below the
programmed level. Over-current protection folds back the
output voltage to 95mV, reducing the regulator dissipation.
These features provide monitoring and protection for the
microprocessor and power system.
Features
Two-Phase Power Conversion
Precision Channel Current Sharing
Precision CORE Voltage Regulation
-
0.8% Accuracy
Microprocessor Voltage Identification Input
- 5-Bit VID Input
- 1.050V to 1.825V in 25mV Steps
- Programmable "Droop" Voltage
Fast Transient Recovery Time
Over Current Protection
High Ripple Frequency, (Channel Frequency
Times Number of Channels). . . . . . . . . . . . .100kHz to 2MHz
Applications
VRM8.5 Modules
Intel Tualatin Processor Voltage Regulator
Low Output Voltage, High Current DC/DC Converters
Related Literature
Technical Brief TB363 "Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)"
Pinout
ISL6562 (SOIC)
TOP VIEW
Ordering Information
PART NUMBER
TEMP. (
o
C)
PACKAGE
PKG. NO.
ISL6562CB
0 to 70
16 Ld SOIC
M16.15
ISL6562CB-T
16 Ld SOIC Tape and Reel
ISL6560/62EVAL1
Evaluation Platform
VID3
VID2
VID1
VID0
VID25mV
CT
PWRGD
REF
PWM1
PWM2
VCC
FB
CS-
COMP
CS+
GND
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
File Number
9012
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Americas Inc.
Intel is a registered trademark of Intel Corporation.
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Copyright Intersil Americas Inc. 2001, All Rights Reserved
ISL6562
Data Sheet
March 2001
2
Block Diagram
Simplified Power System Diagram
Functional Pin Description
VID3 (Pin 1), VID2 (Pin 2), VID1 (Pin 3), VID0 (Pin 4)
and VID25mV (Pin 5)
Voltage Identification inputs from microprocessor. These pins
respond to TTL and 3.3V logic signals. The ISL6562 decodes
VID bits to establish the output voltage. See Table 1.
COMP (Pin 6)
Output of the internal transconductance error amplifier.
Voltage at this terminal sets the output current level of the
Current Sense Comparator. Pulling this pin to ground
disables the oscillator and drives both PWM outputs low.
FB (Pin 7)
Inverting input of the internal transconductance error
amplifier.
CT (Pin 8)
A capacitor on this terminal sets the frequency of the internal
oscillator.
GND (Pin 9)
Bias and reference ground. All signals are referenced to this
pin.
PWRGD (Pin 10)
Open drain connection. A high voltage level at this pin with a
resistor connected to this terminal and VCC indicates that
CORE voltage is at the proper level,
CS+ (Pin 11) and CS- (Pin 14)
These inputs monitor the
supply current to the converter positive input voltage. CS+ is
connected directly to the decoupled supply voltage and
current sampling resistor. CS- is connected to the other end
of the current sampling resistor and the upper drains of the
series transistors.
PWM2 (Pin 12) and PWM1 (Pin 13)
PWM outputs connected to the gate driver ICs.
REF (Pin 15)
Three volt supply used to bias the output of the
transconductance amplifier.
VCC (Pin 16)
Bias supply. Connect this pin to a 12V supply.
D/A
UV
OVP
E/A
CMP
PWM1
PWM2
CS+
CS-
GND
REF
VCC
FB
VID3
VID2
VID1
VID0
VID25mV
COMP
OSCILLATOR
X1.24
PWRGD
3V REFERENCE
BIAS CIRCUITS
UVLO and
CT
CONTROL
LOGIC
+
-
+
-
+
-
X 0.82
+
-
SYNCHRONOUS
ISL6562
MICROPROCESSOR
FB
VID
RECTIFIED BUCK
CHANNEL
SYNCHRONOUS
RECTIFIED BUCK
CHANNEL
PWM 1
PWM 2
VID3
VID2
VID1
VID0
VID25mV
CT
PWRGD
REF
PWM1
PWM2
VCC
FB
CS-
COMP
CS+
GND
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
ISL6562
3
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 15V
CS+. CS- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V
PWRGD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC
All Other Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5V
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . TBD
Machine Model (Per EIAJ ED-4701 Method C-111). . . . . . . . TBD
Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0
o
C to 70
o
C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . 125
o
C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V
10%
Thermal Resistance (Note 1)
JA
(
o
C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
106
Maximum Junction Temperature (Plastic Package) . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VCC SUPPLY CURRENT
Input Supply Current
I
CC
VCC = 12V
-
5.8
9.0
mA
Input Supply Current, UVLO Mode
I
CC(UVLO)
VCC
V
UVLO
, VCC Rising
-
5.7
8.9
mA
Undervoltage Lock Out Voltage
V
UVLO
5.4
6.4
6.9
V
Undervoltage Lock Out Hysteresis
0.1
0.4
0.8
V
DAC and REFERENCE VOLTAGES
Minimum DAC Programed Voltage
V
FB
DAC Programmed to 1.050V
1.042
1.050
1.058
V
Middle DAC Programed Voltage
V
FB
DAC Programmed to 1.500V
1.488
1.500
1.512
V
Maximum DAC Programed Voltage
V
FB
DAC Programmed to 1.825V
1.811
1.825
1.839
V
Line Regulation
V
FB
VCC = 10V to 14V
-
0.05
-
%
Crowbar Trip Point at FB Input
V
CROWBAR
Percent of Nominal DAC Voltage
114
124
134
%
Crowbar Reset Point at FB Input
V
CROWBAR
Percent of Nominal DAC Voltage
50
60
70
%
Crowbar Response Time
I
CROWBAR
Overvoltage to PWM Going Low
-
300
-
ns
Reference Voltage
V
REF
0mA
I
REF
1mA
2.952
3.000
3.048
V
Output Current
I
REF
300
-
-
A
VID INPUTS
Input Low Voltage
V
IL(VID)
-
-
0.6
V
Input High Voltage
V
IH(VID)
2.2
-
-
V
VID Pull-Up
I
VID
VIDx = 0V or VIDx = 3V
10
20
40
A
Internal Pull-Up Voltage
4.5
5.0
5.5
V
OSCILLATOR
Maximum Frequency
f
CT(MAX)
2.0
-
-
MHz
Frequency Variation
f
CT
T
A
= 25
o
C, CT = 91pF
430
500
570
kHz
CT Charging Current
I
CT
T
A
= 25
o
C, V
FB
in Regulation
130
150
170
A
CT Charging Current
I
CT
T
A
= 25
o
C, V
FB
= 0V
26
36
46
A
ERROR AMPLIFIER
Output Resistance
R
O(ERR)
-
200
-
k
Transconductance
g
m(ERR)
2.0
2.2
2.4
mS
ISL6562
4
.
Output Current
I
O(ERR)
FB Forced to V
OUT
- 3%
-
1
-
mA
Input Bias Current
I
FB
-
5
100
nA
Maximum Output Voltage
V
COMP(MAX)
FB Forced to V
OUT
- 3%
-
3.0
-
V
Output Disable Threshold
V
COMP(OFF)
560
720
800
mV
FB Low Foldback Threshold
V
FB(LOW)
375
425
500
mV
-3dB Bandwidth
BW
ERR
COMP = Open
-
500
-
kHz
CURRENT SENSE
Threshold Voltage
V
CS(TH)
CS+ = VCC, FB Forced to V
OUT
- 3%
69
79
89
mV
0.8
COMP
1V
-
0
15
mV
Current Limit Foldback Voltage
V
CS(FOLD)
FB
375mV
37
47
58
mV
V
COMP
/
V
CS
n
i
1 V
V
COMP
3
V
-
25
-
V/V
Input Bias Current
I
CS+
, I
CS-
CS+ = CS- = VCC
-
0.5
5.0
A
Response Time
t
CS
CS+ - (CS-)
89mV to PWM Going Low
-
50
-
ns
POWER GOOD COMPARATOR
Undervoltage Threshold
V
PWRGD(UV)
Percent of Nominal Output
76
82
88
%
Overvoltage Threshold
V
PWRGD(OV)
Percent of Nominal Output
114
124
134
%
Output Voltage Low
V
OL(PWRGD)
I
PWRGD(SINK)
= 100
A
-
30
200
mV
Response Time
-
200
-
ns
PWM OUTPUTS
Output Voltage Low
V
OL(PWM)
I
PWM(SINK)
= 400
A
-
100
500
mV
Output Voltage High
V
OH(PWM)
I
PWM(SOURCE)
= 400
A
4.5
5.0
5.5
V
Output Current
I
PWM
0.4
1
-
mA
Duty Cycle Limit, by Design
D
MAX
Per Phase, Relative to f
CT
-
-
50
%
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VOLTAGE IDENTIFICATION CODE AT
PROCESSOR PINS
V
CC
CORE
(VDC)
VID25mV
VID3
VID2
VID1
VID0
0
0
1
0
0
1.050
1
0
1
0
0
1.075
0
0
0
1
1
1.100
1
0
0
1
1
1.125
0
0
0
1
0
1.150
1
0
0
1
0
1.175
0
0
0
0
1
1.200
1
0
0
0
1
1.225
0
0
0
0
0
1.250
1
0
0
0
0
1.275
0
1
1
1
1
1.300
1
1
1
1
1
1.325
0
1
1
1
0
1.350
1
1
1
1
0
1.375
0
1
1
0
1
1.400
1
1
1
0
1
1.425
0
1
1
0
0
1.450
1
1
1
0
0
1.475
0
1
0
1
1
1.500
1
1
0
1
1
1.525
0
1
0
1
0
1.550
1
1
0
1
0
1.575
0
1
0
0
1
1.600
1
1
0
0
1
1.625
0
1
0
0
0
1.650
1
1
0
0
0
1.675
0
0
1
1
1
1.700
1
0
1
1
1
1.725
0
0
1
1
0
1.750
1
0
1
1
0
1.775
0
0
1
0
1
1.800
1
0
1
0
1
1.825
VOLTAGE IDENTIFICATION CODE AT
PROCESSOR PINS
V
CC
CORE
(VDC)
VID25mV
VID3
VID2
VID1
VID0
ISL6562
5
All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation's quality certifications can be viewed at website www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. How-
ever, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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NORTH AMERICA
Intersil Corporation
2401 Palm Bay Rd., Mail Stop 53-204
Palm Bay, FL 32905
TEL: (321) 724-7000
FAX: (321) 724-7240
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100, Rue de la Fusee
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TEL: (32) 2.724.2111
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Taipei, Taiwan 104
Republic of China
TEL: 886-2-2515-8508
FAX: 886-2-2515-8369
ISL6562
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension "D" does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension "E" does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. "L" is the length of terminal for soldering to a substrate.
7. "N" is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA
E
D
N
1
2
3
-B-
0.25(0.010)
C A
M
B S
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45
o
C
H
0.25(0.010)
B
M
M
M16.15
(JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.3859
0.3937
9.80
10.00
3
E
0.1497
0.1574
3.80
4.00
4
e
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
16
16
7
0
o
8
o
0
o
8
o
-
Rev. 0 12/93
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