1
File Number
3690.7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
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Copyright
Intersil Corporation 1999
HA5351
64ns Sample and Hold Amplifier
The HA5351 is a fast acquisition, wide bandwidth sample
and hold amplifier, built with the Intersil HBC-10 BiCMOS
process. This sample and hold amplifier offers a combination
of desirable features; fast acquisition time (70ns to 0.01%
maximum), excellent DC precision and extremely low power
dissipation, making it ideal for use in systems that sample
multiple signals and require low power.
The HA5351 is in an open loop configuration with fully
differential inputs providing flexibility for user defined
feedback. In unity gain the HA5351 is completely self-
contained and requires no external components. The on-
chip 15pF hold capacitor is completely isolated to minimizing
droop rate and reduce sensitivity to pedestal error. The
HA5351 is available in 8 lead PDIP and SOIC packages for
minimizing board space and ease of layout.
Functional Diagram
Features
Fast Acquisition to 0.01% . . . . . . . . . . . . . . . . . 70ns (Max)
Low Offset Error . . . . . . . . . . . . . . . . . . . . . . .
2mV (Max)
Low Pedestal Error . . . . . . . . . . . . . . . . . . . .
10mV (Max)
Low Droop Rate . . . . . . . . . . . . . . . . . . . . . . 2
V/
s (Max)
Wide Unity Gain Bandwidth . . . . . . . . . . . . . . . . . . 40MHz
Low Power Dissipation . . . . . . . . . . . . . . . 220mW (Max)
Total Harmonic Distortion (Hold Mode) . . . . . . . . . -72dBc
- (V
IN
= 5V
P-P
at 1MHz)
Fully Differential Inputs
On Chip Hold Capacitor
Applications
Synchronous Sampling
Wide Bandwidth A/D Conversion
Deglitching
Peak Detection
High Speed DC Restore
Pinout
HA5351
(PDIP, SOIC)
TOP VIEW)
Ordering Information
PART NUMBER
(BRAND)
TEMP.
RANGE (
o
C)
PACKAGE
PKG.
NO.
HA5351IP
-40 to 85
8 Ld PDIP
E8.3
HA5351IB
(H5351)
-40 to 85
8 Ld SOIC
M8.15
HA5351
G
M
BUFFER
A
V
+
8
1
5
-IN
+IN
S/H
OUT
15pF
4
6
3
V+
V-
7
GND
-
-
+
+IN
NC
V-
OUT
1
2
3
4
8
7
6
5
-IN
GND
V+
S/H
CTRL
Data Sheet
May 1999
2
Absolute Maximum Ratings
Thermal Information
Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . +11V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V
Voltage Between Sample and Hold Control and Ground . . . . . +5.5V
Output Current, Continuous . . . . . . . . . . . . . . . . . . . . . . . . . .
37mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
120
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
160
Maximum Junction Temperature (Plastic Package) . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Test Conditions: V
SUPPLY
=
5V; C
H
= Internal = 15pF, Digital Input: V
IL
= fc0V (Sample), V
IH
= 4.0V (Hold).
Non-Inverting Unity Gain Configuration (Output Tied to -Input), C
L
= 5pF,
Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
TEMP.
(
o
C)
HA5351I
UNITS
MIN
TYP
MAX
INPUT CHARACTERISTICS
Input Voltage Range
Full
-2.5
-
+2.5
V
Input Resistance (Note 2)
25
100
500
-
k
Input Capacitance
25
-
-
5
pF
Input Offset Voltage
25
-2
-
2
mV
Full
-3.0
-
3.0
mV
Offset Voltage Temperature Coefficient
Full
-
15
-
V/
o
C
Bias Current
Full
-
2.5
5
A
Offset Current
Full
-1.5
-
+1.5
A
Common Mode Range
Full
-2.5
-
+2.5
V
Common Mode Rejection Ratio
2.5V, Note 3
Full
60
80
-
dB
TRANSFER CHARACTERISTICS
Large Signal Voltage Gain
V
OUT
=
2.5V
25
95
108
-
dB
Full
85
-
-
dB
Unity Gain -3dB Bandwidth
25
-
40
-
MHz
TRANSIENT RESPONSE
Rise Time
200mV Step
25
-
8.5
-
ns
Overshoot
200mV Step
25
0
-
30
%
Slew Rate
5V Step
Full
88
105
-
V/
s
DIGITAL INPUT CHARACTERISTICS
Input Voltage
V
IH
25, 85
2.1
-
5.0
V
-40
2.4
-
5.0
V
V
IL
Full
0
-
0.8
V
Input Current
V
IL
= 0V
Full
-1.0
-
1.0
A
V
IH
= 5V
Full
-1.0
-
1.0
A
OUTPUT CHARACTERISTICS
Output Voltage
R
L
= 510
Full
-3.0
-
+3.0
V
Output Current
R
L
= 100
25, 85
20
25
-
mA
-40
15
-
-
mA
HA5351
3
Full Power Bandwidth
5V
P-P
, A
V
= +1, -3dB
Full
-
13
-
MHz
Output Resistance
Hold Mode
25
-
0.02
-
Total Output Noise
(DC to 10MHz)
Sample Mode
25
-
325
-
V
RMS
Hold Mode
25
-
325
-
V
RMS
DISTORTION CHARACTERISTICS
SAMPLE MODE
Total Harmonic Distortion
V
IN
= 4.5V
P-P
, f
IN
= 100kHz
25
-
-80
-
dBc
V
IN
= 5V
P-P
, f
IN
= 1MHz
25
-
-74
-
dBc
V
IN
= 1V
P-P
, f
IN
= 10MHz
25
-
-57
-
dBc
Signal to Noise Ratio
(RMS Signal to RMS Noise)
V
IN
= 4.5V
P-P
, f
IN
= 100kHz
25
-
73
-
dB
HOLD MODE (50% Duty Cycle S/H)
Total Harmonic Distortion
V
IN
= 4.5V
P-P
, f
IN
= 100kHz,
f
S
100kHz
25
-
-78
-
dBc
V
IN
= 5V
P-P
, f
IN
= 1MHz,
f
S
1MHz
25
-
-72
-
dBc
V
IN
= 1V
P-P
, f
IN
= 10MHz,
f
S
1MHz
25
-
-51
-
dBc
Signal to Noise Ratio
(RMS Signal to RMS Noise)
V
IN
= 4.5V
P-P
, f
IN
= 100kHz,
f
S
100kHz
25
-
70
-
dB
SAMPLE AND HOLD CHARACTERISTICS
Acquisition Time
0V to 2.0V Step to
1mV
25
-
53
-
ns
0V to 2.0V Step to 0.01%
(
200
V)
25
-
64
70
ns
-2.5V to +2.5V Step to 0.01%
(
500
V)
25
-
90
100
ns
Droop Rate
25
-
0.3
-
V/
s
Full
-2
-
2
V/
s
Hold Step Error
V
IL
= 0V, V
IH
= 4.0V, t
R
= 5ns
Full
-10
-
+
10
mV
Hold Mode Settling Time
To
1mV
25
-
50
-
ns
Hold Mode Feedthrough
5V
P-P
, 500kHz, Sine
25
-
72
-
dB
EADT (Effective Aperture Delay Time)
25
-
+1
-
ns
Aperture Time (Note 2)
25
-
10
-
ns
Aperture Uncertainty
25
-
10
20
ps
POWER SUPPLY CHARACTERISTICS
Positive Supply Current
Full
-
20
22
mA
Negative Supply Current
Full
-
20
22
mA
PSRR
10% Delta
Full
60
74
-
dB
NOTES:
2. Derived from Computer Simulation only, not tested.
3. +CMRR is measured from 0V to +2.5V, -CMRR is measured from 0V to -2.5V.
Electrical Specifications
Test Conditions: V
SUPPLY
=
5V; C
H
= Internal = 15pF, Digital Input: V
IL
= fc0V (Sample), V
IH
= 4.0V (Hold).
Non-Inverting Unity Gain Configuration (Output Tied to -Input), C
L
= 5pF,
Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
TEMP.
(
o
C)
HA5351I
UNITS
MIN
TYP
MAX
HA5351
4
Typical Performance Curves
FIGURE 1. LARGE SIGNAL RESPONSE
FIGURE 2. SMALL SIGNAL RESPONSE
FIGURE 3. UNITY GAIN FREQUENCY RESPONSE
FIGURE 4. CLOSED LOOP GAIN/PHASE A
V
= +1000
FIGURE 5. 5V
P-P
FULL POWER FREQUENCY RESPONSE
FIGURE 6. -3dB BANDWIDTH vs SUPPLY VOLTAGE
2
0
-2
0
100
200
300
400
500
TIME (ns)
OUTPUT (V)
0.1
0.0
-0.1
200
400
600
TIME (ns)
OUTPUT (V)
100K
1M
10M
100M
2
0
-2
-4
-6
-8
FREQUENCY (Hz)
GAIN (dB)
40.163156MHz
-3dB
1K
10K
100K
1M
10M
100M
FREQUENCY (Hz)
60
40
20
0
-20
0
-30
-60
-90
-120
-150
-180
PHASE (DEGREES)
GAIN (dB)
0dB AT 21.34MHz
GAIN
PHASE
-119.86 DEG
10K
100K
1M
10M
100M
2
0
-2
-4
-6
-8
FREQUENCY (Hz)
GAIN (dB)
13.241189MHz
-3dB
3.5
4
4.5
5
5.5
6
0
10
20
30
40
50
60
SUPPLY VOLTAGE (V)
-3dB B
AND
WIDTH (MHz)
4 TYPICAL UNITS
200mV
P-P
HA5351
5
FIGURE 7. DROOP RATE vs TEMPERATURE
FIGURE 8. SLEW RATE vs TEMPERATURE
FIGURE 9. RISE TIME vs TEMPERATURE
FIGURE 10. HOLD MODE SETTLING vs TEMPERATURE
FIGURE 11. PEDESTAL vs S/H CONTROL RISE TIME
FIGURE 12. ACQUISITION TIME (0.01%, 0V TO 2V STEP)
Typical Performance Curves
(Continued)
-50
0
50
100
0
0.1
0.2
0.3
0.4
0.5
TEMPERATURE (
o
C)
DR
OOP RA
TE (
V/
s)
3 TYPICAL UNITS
-50
0
50
100
80
90
100
110
120
130
140
150
160
TEMPERATURE (
o
C)
SLEW RA
TE (V/
s)
UNIT #2
UNIT #3
UNIT #1
3 TYPICAL UNITS
-SLEW RATE
+SLEW RATE
-50
0
50
100
4
5
6
7
8
9
TEMPERATURE (
o
C)
RISE TIME (ns)
4 TYPICAL UNITS
-50
0
50
100
30
35
40
45
50
55
60
65
TEMPERATURE (
o
C)
HOLD MODE SETTLING TIME (ns)
4 TYPICAL UNITS
0
10
20
30
40
50
-2
-1
0
1
2
3
S/H CONTROL RISE TIME (ns)
PEDEST
AL ERR
OR (mV)
0V TO 4V S/H CTRL
0.01
0.00
-0.01
3.0E-7
0
5
10
TIME (ns)
OUTPUT (V)
S/H CONTR
OL (V)
67.25ns
OUTPUT
S/H
CONTROL
HA5351
6
Die Characteristics
DIE DIMENSIONS:
2530
m x 1760
m x 525
m
100 mils x 69 mils x 19 mils
METALLIZATION:
Type: Metal 1: AlSiCu/TiW
Thickness: Metal 1: 6k
750
Type: Metal 2: AlSiCu
Thickness: Metal 2: 16k
1.1k
PASSIVATION:
Type: Sandwich Passivation
Nitride - 4k
, Undoped Si Glass (USG) - 8k
,
Total - 12k
2k
SUBSTRATE POTENTIAL:
V-
TRANSISTOR COUNT:
156
Metallization Mask Layout
HA5351
FIGURE 13. HOLD MODE SETTLING TIME (
200
V)
Typical Performance Curves
(Continued)
0.02
0.00
-0.02
-0.04
0
20
40
60
80
0
5
10
TIME (ns)
51.4 ns
OUTPUT (V)
S/H CONTR
OL (V)
OUTPUT
+IN
-IN
V-
V-
V-
V
OUT
V
OUT
S/H CONTROL
V+
V+
V+
GND
GND
GND
HA5351
7
HA5351
Dual-In-Line Plastic Packages (PDIP)
C
L
E
e
A
C
e
B
e
C
-B-
E1
INDEX
1 2 3
N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1
B
e
D
D1
A
A2
L
A
1
-A-
0.010 (0.25)
C
A
M
B S
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the "MO Series Symbol List" in Section
2.2 of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and
are measured with the leads constrained to be per-
pendicular to datum
.
7. e
B
and e
C
are measured at the lead tips with the leads uncon-
strained. e
C
must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
e
A
-C-
E8.3
(JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
B1
0.045
0.070
1.15
1.77
8, 10
C
0.008
0.014
0.204
0.355
-
D
0.355
0.400
9.01
10.16
5
D1
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
2.54 BSC
-
e
A
0.300 BSC
7.62 BSC
6
e
B
-
0.430
-
10.92
7
L
0.115
0.150
2.93
3.81
4
N
8
8
9
Rev. 0 12/93
8
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
HA5351
Small Outline Plastic Packages (SOIC)
INDEX
AREA
E
D
N
1
2
3
-B-
0.25(0.010)
C A
M
B S
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45
o
C
H
0.25(0.010)
B
M
M
NOTES:
1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension "D" does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension "E" does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. "L" is the length of terminal for soldering to a substrate.
7. "N" is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width "B", as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
M8.15
(JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
e
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
8
8
7
0
o
8
o
0
o
8
o
-
Rev. 0 12/93
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