HI-5701

6-Bit, 30MSPS, Flash A/D Converter

The HI-5701 is a monolithic, 6-bit, CMOS flash Analog-to-
Digital Converter. It is designed for high speed applications
where wide bandwidth and low power consumption are
essential. Its 30MSPS speed is made possible by a parallel
architecture which also eliminates the need for an external
sample and hold circuit. The HI-5701 delivers

0.7 LSB

differential nonlinearity while consuming only 250mW (Typ)
at 30MSPS. Microprocessor compatible data output latches
are provided which present valid data to the output bus 1.5
clock cycles after the convert command is received. An
overflow bit is provided to allow the series connection of two
converters to achieve 7-bit resolution.

Features

· 30MSPS with No Missing Codes

· Full Power Input Bandwidth . . . . . . . . . . . . . . . . . . 20MHz

· No Missing Codes Over Temperature

· Sample and Hold Not Required

· Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . .+5V

· Power Dissipation (Max). . . . . . . . . . . . . . . . . . . . . 300mW

· CMOS/TTL Compatible

· Overflow Bit

· /883 Version Available

Applications

· Video Digitizing

· Radar Systems

· Communication Systems

· High Speed Data Acquisition Systems

Pinout

HI-5701

(SOIC)

TOP VIEW

Ordering Information

PART NUMBER

TEMP.

RANGE (

PACKAGE

PKG.

DWG. #

HI9P5701K-5

0 to 70

18 Ld SOIC

M18.3

D0 (LSB)

REF

D5 (MSB)

OVF

CE2

CE1

PHASE

CLK

REF

Data Sheet

September 9, 2005

FN2937.10

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or

1-888-468-3774

Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Absolute Maximum Ratings

Thermal Information

Supply Voltage, V

to V

. . . . . . . . . . . (V

0.5) < V

< +7V

Analog and Reference Input Pins (V

0.5) < V

INA

< (V

+0.5V)

Digital I/O Pins . . . . . . . . . . . . . . . .(V

0.5) < V

I/O

< (V

+0.5V)

Operating Conditions

Temperature Range

HI9P5701-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0

C to 70

Thermal Resistance (Typical, Note 1)

(

C/W)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum Power Dissipation at 70

C (Note 2) . . . . . . . . . . . 635mW

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150

Maximum Storage Temperature Range . . . . . . . . . . -65

C to 150

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

is measured with the component mounted on an evaluation PC board in free air.

2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.

Electrical Specifications

= +5.0V; V

REF

+ = +4.0V; V

REF-

= V

= GND; f

= Specified Clock Frequency at 50% Duty Cycle;

= 30pF; Unless Otherwise Specified

PARAMETER

TEST CONDITIONS

(NOTE 3)

C TO 70

UNITS

MIN

TYP

MAX

MIN

MAX

SYSTEM PERFORMANCE

Resolution

Bits

Integral Linearity Error, INL
(Best Fit Line)

= 20MHz

0.5

1.25

2.0

LSB

= 30MHz

1.5

LSB

Differential Linearity Error, DNL
(Guaranteed No Missing Codes)

= 20MHz

0.3

0.6

0.75

LSB

= 30MHz

0.7

LSB

Offset Error, V

(Adjustable to Zero)

= 20MHz (Note 3)

0.5

2.0

2.5

LSB

= 30MHz

0.5

LSB

Full Scale Error, FSE
(Adjustable to Zero)

= 20MHz (Note 3)

0.25

2.0

2.5

LSB

= 30MHz

0.25

LSB

DYNAMIC CHARACTERISTICS

Maximum Conversion Rate

No Missing Codes

MSPS

Minimum Conversion Rate

No Missing Codes (Note 3)

0.125

MSPS

Full Power Input Bandwidth

= 30MHz

MHz

Signal to Noise Ratio, SNR

= 1MHz, f

= 100kHz

= 30MHz, f

= 4MHz

Signal to Noise Ratio, SINAD

= 1MHz, f

= 100kHz

= 30MHz, f

= 4MHz

Total Harmonic Distortion

= 1MHz, f

= 100kHz

dBc

= 30MHz, f

= 4MHz

dBc

Differential Gain

= 14.32MHz, f

= 3.58MHz

Differential Phase

= 14.32MHz, f

= 3.58MHz

Degree

ANALOG INPUTS

Analog Input Resistance, R

= 4V

Analog Input Capacitance, C

= 0V

RMS Signal

RMS Noise

---------------------------------

RMS Signal

RMS Noise + Distortion

--------------------------------------------------------------

HI-5701

Analog Input Bias Current, IB

= 0V, 4V

0.01

1.0

REFERENCE INPUTS

Total Reference Resistance, R

250

370

235

Reference Resistance Tempco, T

+0.266

DIGITAL INPUTS

Input Logic High Voltage, V

2.0

Input Logic Low Voltage, V

0.8

Input Logic High Current, I

= 5V

1.0

Input Logic Low Current, I

= 0V

1.0

Input Capacitance, C

DIGITAL OUTPUTS

Output Logic Sink Current, I

= 0.4V

3.2

Output Logic Source Current, I

= 4.5V

-3.2

3.2

Output Leakage, I

OFF

CE2 = 0V

1.0

Output Capacitance, C

OUT

CE2 = 0V

5.0

TIMING CHARACTERISTICS

Aperture Delay, t

Aperture Jitter, t

Data Output Enable Time, t

(Note 3)

Data Output Disable Time, t

DIS

(Note 3)

Data Output Delay, t

(Note 3)

Data Output Hold, t

(Note 3)

POWER SUPPLY REJECTION

Offset Error PSRR,

= 5V

10%

0.1

1.0

1.5

LSB

Gain Error PSRR,

FSE

= 5V

10%

0.1

1.0

1.5

LSB

POWER SUPPLY CURRENT

Supply Current, I

= 20MHz

NOTE:

3. Parameter guaranteed by design or characterization and not production tested.

Electrical Specifications

= +5.0V; V

REF

+ = +4.0V; V

REF-

= V

= GND; f

= Specified Clock Frequency at 50% Duty Cycle;

= 30pF; Unless Otherwise Specified (Continued)

PARAMETER

TEST CONDITIONS

(NOTE 3)

C TO 70

UNITS

MIN

TYP

MAX

MIN

MAX

HI-5701

Typical Performance Curves

FIGURE 3. EFFECTIVE NUMBER OF BITS vs f

FIGURE 4. ENOB vs TEMPERATURE

FIGURE 5. SNR vs TEMPERATURE

FIGURE 6. TOTAL HARMONIC DISTORTION vs TEMPERATURE

FIGURE 7. INL vs TEMPERATURE

FIGURE 8. DNL vs TEMPERATURE

0.5

1.5

2.5

3.5

4.5

INPUT FREQUENCY (f

) - MHz

FEC

E B

I
TS

= 5V, V

REF

+ = 4V

= 25

= 20MHz

= 30MHz

= 40MHz

= 5V, V

REF

+ = 4V

= 1MHz, f

= 100kHz

= 30MHz, f

= 4MHz

EFFECTIVE BI

TEMPERATURE (

= 5V, V

REF

+ = 4V

= 30MHz, f

= 4MHz

= 1MHz, f

= 100kHz

-40 -30 -20 -10

TEMPERATURE (

= 30MHz, f

= 4MHz

= 5V, V

REF

+ = 4V

= 1MHz, f

= 100kHz

-40 -30 -20 -10

-34

-36

-38

-40

-42

-44

-46

dBc

TEMPERATURE (

= 30MHz

= 100kHz

= 5V, V

REF

+ = 4V

1.5

0.5

-40 -30 -20 -10

TEMPERATURE (

LSBs

= 1MHz

0.75

0.5

0.25

LSBs

TEMPERATURE

-40 -30 -20 -10

= 30MHz

= 1MHz

= 100kHz

= 5V, V

REF

+ = 4V

HI-5701

FIGURE 9. POWER SUPPLY REJECTION vs TEMPERATURE

FIGURE 10. SUPPLY CURRENT vs TEMPERATURE

FIGURE 11. SUPPLY CURRENT vs CLOCK AND DUTY CYCLE

FIGURE 12. EFFECTIVE NUMBER OF BITS vs CLOCK

FREQUENCY

Typical Performance Curves

(Continued)

PSRR FSE

PSRR V

0.5

-1

-40 -30 -20 -10

TEMPERATURE (

LSBs

-0.5

= 5V

10%, V

REF

+ = 4V

-20

100

TEMPERATURE (

(mA)

= 1MHz

-40

= 5V, V

REF

+ = 4V

= 20MHz

0.1

100

CLOCK FREQUENCY (MHz)

)

= 5V, V

REF

+ = 4V

= 25

D = 50%

D = 25%

D = 10%

------------------------

CLOCK FREQUENCY (MHz)

= 1MHz

1.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

EFFECTIVE BI

HI-5701

Theory of Operation

The HI-5701 is a 6-bit analog-to-digital converter based on a
parallel CMOS "flash" architecture. This flash technique is an
extremely fast method of A/D conversion because all bit
decisions are made simultaneously. In all, 64 comparators
are used in the HI-5701; 63 comparators to encode the
output word, plus an additional comparator to detect an
overflow condition.

The CMOS HI-5701 works by alternately switching between
a "Sample" mode and an "Auto Balance" mode. Splitting up
the comparison process in this CMOS technique offers a
number of significant advantages. The offset voltage of each
CMOS comparator is dynamically canceled with each
conversion cycle such that offset voltage drift is virtually

eliminated during operation. The block diagram and timing
diagram illustrate how the HI-5701 CMOS flash converter
operates.

The input clock which controls the operation of the HI-5701
is first split into a non-inverting

1 clock and an inverting

clock. These two clocks, in turn, synchronize all internal
timing of analog switches and control logic within the
converter.

In the "Auto Balance" mode (

1), all

1 switches close and

2 switches open. The output of each comparator is

momentarily tied to its own input, self-biasing the comparator
midway between V

and V

and presenting a low

impedance to a small input capacitor. Each capacitor, in turn,
is connected to a reference voltage tap from the resistor
ladder. The Auto Balance mode quickly precharges all 64
input capacitors between the self-bias voltage and each
respective tap voltage.

In the "Sample" mode (

2), all

1 switches open and

switches close. This places each comparator in a sensitive
high gain amplifier configuration. In this open loop state, the
input impedance is very high and any small voltage shift at
the input will drive the output either high or low. The

2 state

also switches each input capacitor from its reference tap to
the input signal. This instantly transfers any voltage
difference between the reference tap and input voltage to the
comparator input. All 64 comparators are thus driven
simultaneously to a defined logic state. For example, if the
input voltage is at mid-scale, capacitors precharged near
zero during

1 will push comparator inputs higher than the

self bias voltage at

2; capacitors precharged near the

reference voltage push the respective comparator inputs
lower than the bias point. In general, all capacitors
precharged by taps above the input voltage force a "low"
voltage at comparator inputs; those precharged below the
input voltage force "high" inputs at the comparators.

During the next

1 state, comparator output data is latched

into the encoder logic block and the first stage of encoding
takes place. The following

2 state completes the encoding

process. The 6 data bits (plus overflow bit) are latched into
the output flip-flops at the next falling clock edge. The
Overflow bit is set if the input voltage exceeds V

REF

+ -

LSB. The output bus may be either enabled or disabled
according to the state of CE1 and CE2 (See Table 2). When
disabled, output bits assume a high impedance state.

As shown in the timing diagram, the digital output word
becomes valid after the second

1 state. There is thus a one

and a half cycle pipeline delay between input sample and
digital output. "Data Output Delay" time indicates the slight
time delay for data to become valid at the end of the

1 state.

Refer to the Glossary of Terms for other definitions.

TABLE 1. PIN DESCRIPTIONS

PIN #

NAME

DESCRIPTION

Bit 6, Output (MSB).

OVF

Overflow, Output.

Digital Ground.

No Connection.

CE2

Three-State Output Enable Input, Active
High (See Table 2).

CE1

Three-State Output Enable Input, Active
Low (See Table 2).

CLK

Clock Input.

PHASE

Sample Clock Phase Control Input. When
Phase is Low, Sample Unknown

(

1) Oc-

curs When the Clock is Low and Auto Bal-
ance

(

2) Occurs When the Clock is High

(See Text).

REF

Reference Voltage Positive Input.

REF

Reference Voltage Negative Input.

Analog Signal Input.

Power Supply, +5V.

Bit 1, Output (LSB).

Bit 2, Output.

Bit 3, Output.

Reference Ladder Midpoint.

Bit 4, Output.

Bit 5, Output.

TABLE 2. CHIP ENABLE TRUTH TABLE

CE1

CE2

OVF

Valid

Three-State

Valid

Three-State

X = Don't Care

HI-5701

Application Information

Voltage Reference

The reference voltage is applied across the resistor ladder at
the input of the converter, between V

REF

+ and V

REF

-. In

most applications, V

REF

- is simply tied to analog ground

such that the reference source drives V

REF

+. The reference

must be capable of supplying enough current to drive the
minimum ladder resistance of 235

over temperature.

The HI-5701 is specified for a reference voltage of 4.0V, but
will operate with voltages as high as the V

supply. In the

case of 4.0V reference operation, the converter encodes the
analog input into a binary output in LSB increments of
(V

REF

+ -V

REF

)/64, or 62.5mV. Reducing the reference

voltage reduces the LSB size proportionately and thus
increases linearity errors. The minimum practical reference
voltage is about 2V. Because the reference voltage terminals
are subjected to internal transient currents during
conversion, it is important to drive the reference pins from a
low impedance source and to decouple thoroughly. Again,
ceramic and tantalum (0.01

F and 10

F) capacitors near

the package pin are recommended. It is not necessary to
decouple the

R tap point pin for most applications.

It is possible to elevate V

REF

- from ground if necessary. In

this case, the V

REF

- pin must be driven from a low

impedance reference capable of sinking the current through
the resistor ladder. Careful decoupling is again
recommended.

Digital Control and Interface

The HI-5701 provides a standard high speed interface to
external CMOS and TTL logic families. Four digital inputs are
provided to control the function of the converter. The clock

and phase inputs control the sample and auto balance
modes. The digital outputs change state on the clock phase
which begins the sample mode. Two chip enable inputs
control the three-state outputs of output bits D0 through D5
and the Overflow OVF bit. As indicated in Table 2, all output
bits are high impedance when CE2 is low, and output bits D0
through D5 are independently controlled by CE1.

Although the Digital Outputs are capable of handling typical
data bus loading, the bus capacitance charge/discharge
currents will produce supply and local ground disturbances.
Therefore, an external bus driver is recommended.

Clock

The clock should be properly terminated to digital ground
near the clock input pin. Clock frequency defines the
conversion frequency and controls the converter as
described in the "Theory of Operation" section. The Auto
Balance

1 half cycle of the clock may be reduced to 16ns;

the Sample

2 half cycle may be varied from a minimum of

16ns to a maximum of 8

Gain and Offset Adjustment

In applications where accuracy is of utmost importance,
three adjustments can be made; i.e., offset, gain, and

CLOCK

INPUT

+4V

REF+

PHASE

CLK

CE1

CE2

OVF

+5V

0.01

1/2R

REF-

+5V

0.01

+9V to +12V

0.01

ANALOG
SIGNAL
INPUT

HA-5033

100

0.01

-9V to -12V

DATA
OUPUT

FIGURE 13. TEST CIRCUIT

TABLE 3. PHASE CONTROL

CLOCK

PHASE

INTERNAL GENERATION

Sample Unknown (

Auto Balance

(

Auto Balance

(

Sample Unknown

(

HI-5701

midpoint trim. In general, offset and gain correction can be
done in the preamp circuitry.

Offset Adjustment

The preferred offset correction method is to introduce a DC
component to V

of the converter. An alternate method is to

adjust the V

REF

- input to produce the desired offset

adjustment. The theoretical input voltage to produce the first
transition is

LSB.

(0 to 1 transition) =

LSB =

REF

/64) = V

REF

/128.

Gain Adjustment

In general, full scale error correction can be done in the
preamp circuitry by adjusting the gain of the op amp. An
alternate method is to adjust the V

REF

+ input voltage. This

adjustment is performed by setting V

to the 63 to overflow

transition. The theoretical input voltage to produce the
transition is

LSB less than V

REF

+ and is calculated as

follows:

(63 to 64 transition) = V

REF

- (V

REF

/128)

= V

REF

(127/128).

To perform the gain trim, first do the offset trim and then
apply the required V

for the 63 to overflow transition. Now

adjust V

REF

+ until that transition occurs on the outputs.

Midpoint Trim

The reference center (

R) is available to the user as the

midpoint of the resistor ladder. The

R point can be used

to improve linearity or create unique transfer functions. The
offset and gain trims should be done prior to adjusting the
midpoint. The theoretical transition from count 31 to 32
occurs at 31.5 LSBs. That voltage is calculated as follows:

(31 to 32 transition) = 31.5(V

REF

/64) = V

REF

(63/128).

An adjustable voltage follower can be used to drive the

pin. Set V

to the 31 to 32 transition voltage, then adjust the

voltage follower until the transition occurs on the output bits.

Signal Source

A current pulse is present at the analog input (V

) at the

beginning of every sample and auto balance period. The
transient current is due to comparator charging and switch
feed through in the capacitor array. It varies with the
amplitude of the analog input and the sampling rate.

The signal source must be capable of recovering from the
transient prior to the end of the sample period to ensure a
valid signal for conversion. Suitable broad band amplifiers or
buffers which exhibit low output impedance and high output
drive include the HFA-0005, HA-5004, HA-5002, and HA-
5033.

The signal source may drive above or below the power
supply rails, but should not exceed 0.5V beyond the rails or
damage may occur. Input voltages of -0.5V to +

LSB are

converted to all zeros; input voltages of V

REF

+ -

LSB to

+ 0.5 are converted to all ones with the Overflow bit set.

Power Supply

The HI-5701 operates nominally from a 5V supply, but will
function from 3V to 6V. The supply should be well regulated
and "clean" of significant noise, especially high frequency
noise. It is recommended that power supply decoupling
capacitors be placed as close to the supply pin as possible.
A combination of 0.01

F ceramic and 10

F tantalum

capacitors is recommended for this purpose as shown in the
test circuit Figure 13.

Reducing Power Consumption

Power dissipation in the HI-5701 is related to clock frequency
and clock duty cycle. For a fixed 50% clock duty cycle, power
may be reduced by lowering the clock frequency. For a given
conversion frequency, power may be reduced by shortening
the Auto Balance

1 portion of the clock duty cycle.

TABLE 4. OUTPUT CODE TABLE

CODE

DESCRIPTION

INPUT VOLTAGE

REF

= 4V

REF

= 0V

(V)

DECIMAL

COUNT

BINARY OUTPUT CODE

MSB

LSB

OVF

Overflow (OVF)

4.000

127

Full Scale (FS)

3.9063

1 LSB

3.8438

·
·

·
·
·

2.9688

·
·
·

HI-5701

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Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

Glossary of Terms

Aperture Delay - is The time delay between the external
sample command (the rising edge of the clock) and the time
at which the signal is actually sampled. This delay is due to
internal clock path propagation delays.

Aperture Jitter, t

- This is the RMS variation in the

aperture delay due to variation of internal

1 and

2 clock

path delays and variation between the individual comparator
switching times.

Differential Linearity Error, DNL - The differential linearity
error is the difference in LSBs between the spacing of the
measured midpoint of adjacent codes and the spacing of
ideal midpoints of adjacent codes. The ideal spacing of each
midpoint is 1 LSB. The range of values possible is from
-1 LSB (which implies a missing code) to greater than
+1 LSB.

Full Power Input Bandwidth - Full power bandwidth is the
frequency at which the amplitude of the fundamental of the
digital output word has decreased 3dB below the amplitude
of an input sine wave. The input sine wave has a peak-to-
peak amplitude equal to the reference voltage. The
bandwidth given is measured at the specified sampling
frequency.

Full Scale Error, FSE - is The difference between the actual
input voltage of the 63 to 64 code transition and the ideal
value of V

REF

+ - 1.5 LSB. This error is expressed in LSBs.

Integral Linearity Error, INL - The integral linearity error is
the difference in LSBs between the measured code centers
and the ideal code centers. The ideal code centers are
calculated using a best fit line through the converter's
transfer function.

LSB - Least Significant Bit = (V

REF

+ - V

REF

-)/64. All

HI-5701 specifications are given for a 62.5mV LSB size
V

REF

+ = 4V, V

REF

- = 0V.

Offset Error, V

- Offset error is the difference between

the actual input voltage of the 0 to 1 code transition and the
ideal value of V

REF

- + 0.5 LSB. V

error is expressed in

LSBs.

Power Supply Rejection Ratio, PSRR - Is expressed in
LSBs and is the maximum shift in code transition points due
to a power supply voltage shift. This is measured at the 0 to
1 code transition point and the 62 to 63 code transition point
with a power supply voltage shift from the nominal value of
5.0V.

Signal to Noise Ratio, SNR - SNR is the ratio in dB of the
RMS signal to RMS noise at specified input and sampling
frequencies.

Signal to Noise and Distortion Ratio, SINAD - Is the ratio
in dB of the RMS signal to the RMS sum of the noise and
harmonic distortion at specified input and sampling
frequencies.

Total Harmonic Distortion, THD - Is the ratio in dBc of the
RMS sum of the first five harmonic components to the RMS
signal for a specified input and sampling frequency

1.9688

·
·
·

0.9688

·
·
·

1 LSB

0.0313

Zero

The voltages listed above represent the ideal transition of each output code shown as a function of the reference voltage.

TABLE 4. OUTPUT CODE TABLE (Continued)

CODE

DESCRIPTION

INPUT VOLTAGE

REF

= 4V

REF

= 0V

(V)

DECIMAL

COUNT

BINARY OUTPUT CODE

MSB

LSB

OVF

HI-5701

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