4-1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

Intersil and Design is a trademark of Intersil Corporation.

Intersil Corporation 2000

File Number

4659.5

HC55120, HC55121, HC55130, HC55131, HC55140,

HC55141, HC55142, HC55143, HC55150, HC55151

Low Power Universal SLIC Family

The UniSLIC14 is a family of Ultra Low Power SLICs. The
feature set and common pinouts of the UniSLIC14 family
positions it as a universal solution for: Plain Old Telephone
Service (POTS), PBX, Central Office, Loop Carrier, Fiber in the
Loop, ISDN-TA and NT1+, Pairgain and Wireless Local Loop.

The UniSLIC14 family achieves its ultra low power operation
through: Its automatic single and dual battery selection
(based on line length) and battery tracking anti clipping to
ensure the maximum loop coverage on the lowest battery
voltage. This architecture is ideal for power critical
applications such as ISDN NT1+, Pairgain and Wireless
local loop products.

The UniSLIC14 family has many user programmable
features. This family of SLICs delivers a low noise, low
component count solution for Central Office and Loop
Carrier universal voice grade designs. The product family
integrates advanced pulse metering, test and signaling
capabilities, and zero crossing ring control.

The UniSLIC14 family is designed in the Intersil "Latch" free
Bonded Wafer process. This process dielectrically isolates
the active circuitry to eliminate any leakage paths as found in
our competition's JI process. This makes the UniSLIC14
family compliant with "hot plug" requirements and operation
in harsh outdoor environments.

Block Diagram

Features

· Ultra Low Active Power (OHT) < 60mW

· Single/Dual Battery Operation

· Automatic Silent Battery Selection

· Power Management/Shutdown

· Battery Tracking Anti Clipping

· Single 5V Supply with 3V Compatible Logic

· Zero Crossing Ring Control

- Zero Voltage On/Zero Current Off

· Tip/Ring Disconnect

· Pulse Metering Capability

· 4 Wire Loopback

· Programmable Current Feed

· Programmable Resistive Feed

· Programmable Loop Detect Threshold

· Programmable On-Hook and Off-Hook Overheads

· Programmable Overhead for Pulse Metering

· Programmable Polarity Reversal Time

· Selectable Transmit Gain 0dB/-6dB

· 2 Wire Impedance Set by Single Network

· Loop and Ground Key Detectors

· On-Hook Transmission

· Common Pinout

· HC55121

- Polarity Reversal

· HC55130

- -63dB Longitudinal Balance

· HC55140

- Polarity Reversal
- Ground Start
- Line Voltage Measurement
- 2 Wire Loopback
- -63dB Longitudinal Balance

· HC55142

- Polarity Reversal
- Ground Start
- Line Voltage Measurement
- 2.2V

RMS

Pulse Metering

- 2 Wire Loopback

· HC55150

- Polarity Reversal
- Line Voltage Measurement
- 2.2V

RMS

Pulse Metering

- 2 Wire Loopback

Applications

· Related Literature

- AN9871, User's Guide for UniSLIC14 Eval Board

RRLY

TIP

RING

RING AND TEST

RELAY DRIVERS

RING TRIP

DETECTOR

BGND

BATTERY

SELECTION

AND

BIAS

NETWORK

ZERO CURRENT

2-WIRE

INTERFACE

CROSSING

TRLY1

TRLY2

C2
C3

GKD_LVM

ROH

CDC
RDC_RAC

ZT
C

LOOP CURRENT

DETECTOR

PTG

ILIM

STATE

DECODER

AND

DETECTOR

LOGIC

GKD/LOOP LENGTH

DETECTOR

RSYNC_REV

SHD

4-WIRE INTERFACE

VF SIGNAL PATH

LINE FEED

CONTROL

C4
C5

CRT_REV_LVM

POLARITY
REVERSAL

PULSE METERING

SPM

SIGNAL PATH

AGND

Data Sheet

June 2000

4-2

Ordering Information

PART

NUMBER

MAX

LOOP

CURRENT

(mA)

POLARITY

REVERSAL

GND

START

GND

KEY

LINE

VOLTAGE

MEASUREMENT

PULSE

METERING

2 TEST

RELAY

DRIVERS

2 WIRE

LOOP-

BACK

LONGITUDINAL

BALANCE

TEMP

RANGE

(

PKG.

NO.

HC55120CB

53dB

0 to 70 M28.3

SOIC

HC55120CM

53dB

0 to 70 N28.45

PLCC

HC55121IB

53dB

-40 to

M28.3
SOIC

HC55121IM

53dB

-40 to

N28.45
PLCC

HC55130IB

63dB

-40 to

M28.3
SOIC

HC55130IM

63dB

-40 to

N28.45
PLCC

HC55131IM

63dB

-40 to

N32.45x55
PLCC

HC55140IB

63dB

-40 to

M28.3
SOIC

HC55140IM

63dB

-40 to

N28.45
PLCC

HC55141IM

63dB

-40 to

N32.45x55
PLCC

HC55142IB

63dB

-40 to

M28.3
SOIC

HC55142IM

63dB

-40 to

N28.45
PLCC

HC55143IM

63dB

-40 to

N32.45x55
PLCC

HC55150CB

55dB

0 to 70 M28.3

SOIC

HC55150CM

55dB

0 to 70 N28.45

PLCC

HC55151CM

55dB

0 to 70 N32.45x55

PLCC

HC5514XEVAL1 Evaluation board

Available by placing SLIC in Test mode.

Device Operating Modes

DESCRIPTION

HC55120

HC55121

HC55130/1

HC55140/1

HC55142/3

HC55150/1

Open Circuit
4-Wire Loopback

Ringing

Forward Active

Test Forward Active
2 Wire Loopback and
Line Voltage Measurement

Tip Open Ground Start

Reserved

Reverse Active

Test Reverse Active
Line Voltage Measurement

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

4-3

Absolute Maximum Ratings

= 25

Thermal Information

Temperature, Humidity

Storage Temperature Range . . . . . . . . . . . . . . . . -65

C to 150

Operating Temperature Range . . . . . . . . . . . . . . . -40

C to 110

Operating Junction Temperature Range. . . . . . . . -40

C to 150

Power Supply (-40

Supply Voltage V

to GND . . . . . . . . . . . . . . . . . . . . -0.4V to 7V

Supply Voltage V

to GND . . . . . . . . . . . . . . . . . . . .-V

to 0.4V

Supply Voltage V

to GND, Continuous. . . . . . . . . . -75V to 0.4V

Supply Voltage V

to GND, 10ms . . . . . . . . . . . . . . -80V to 0.4V

Relay Driver

Ring Relay Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 0V to 14V
Ring Relay Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA

Digital Inputs, Outputs (C1, C2, C3, C4, C5, SHD, GKD_LVM)

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to V

Output Voltage (SHD, GKD_LVM Not Active). . . . . . -0.4V to V

Output Current (SHD, GKD_LVM) . . . . . . . . . . . . . . . . . . . . . 5mA

ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500V
Gate Count. . . . . . . . . . . . . . . . . . . . . . . .543 Transistors, 51 Diodes
Tipx and Ringx Terminals (-40

Tipx or Ringx Current . . . . . . . . . . . . . . . . . . . . -100mA to 100mA

Thermal Resistance (Typical, Note 1)

28 Lead PLCC Package . . . . . . . . . . . . . . . . . . . . . .

C/W

28 Lead SOIC Package . . . . . . . . . . . . . . . . . . . . . .

C/W

32 Lead PLCC Package . . . . . . . . . . . . . . . . . . . . . .

66.2

C/W

Continuous Power Dissipation at 85

28 Lead PLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5W
28 Lead SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.0W
32 Lead PLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.4W

Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . . . . . 300

(PLCC, SOIC - Lead Tips Only)

Derate above 70

Tip and Ring Terminals

Tipx or Ringx, Current, Pulse < 10ms, T

REP

> 10s . . . . . . . . . .2A

Tipx or Ringx, Current, Pulse < 1ms, T

REP

> 10s . . . . . . . . . . .5A

Tipx or Ringx, Current, Pulse < 10

s, T

REP

> 10s . . . . . . . . .15A

Tipx or Ringx, Current, Pulse < 1

s, T

REP

> 10s . . . . . . . . . .20A

Tipx or Ringx, Pulse < 250ns, T

REP

> 10s

20A

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured with the component mounted on an evaluation PC board in free air.

Typical Operating Conditions

These represent the conditions under which the device was developed and are suggested as guidelines.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Ambient Temperature

HC55120, HC55150/1

HC55121, HC55130/1, HC55140/1,
HC55142/3

-40

with Respect to GND

-58

-8

with Respect to GND

4.75

5.25

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

4-4

Electrical Specifications

= -40

C to 85

C, V

= +5V

5%, V

= -48V, V

= -24V, PTG = Open, R

= R

= 0

= 120k

, R

LIM

= 38.3k

, R

= 50k

, RDC_RAC = 20k

= 40k

, C

= 0.1

F, C

= 4.7

F, C

RT/REV

= 0.47

F, GND = 0V, RL = 600

. Unless Otherwise Specified.

(·)

Symbol used to indicate the test applies

to the part. (NA) symbol used to indicate the test does not apply to the part.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

HC55120

HC55121

HC55130/1

HC55140/1

HC55142/3

HC55150/1

2-WIRE PORT

Overload Level, Off Hook
Forward and Reverse

1% THD, I

DCMET

18mA

(Note 2, Figure 1)

3.2

PEAK

Forward

Only

Forward

Only

Overload Level, On Hook
Forward and Reverse

1% THD, IDCMET

5mA

(Note 3, Figure 1)

1.3

PEAK

Forward

Only

Forward

Only

Input Impedance (Into Tip and Ring)

/200

Longitudinal Impedance (Tip, Ring)
Forward and Reverse

0 < f < 100Hz (Note 4, Figure 2)

/Wire

Forward

Only

Forward

Only

LONGITUDINAL CURRENT LIMIT (TIP, RING)

On-Hook, Off-Hook (Active),
R

= 736

Forward and Reverse

No False Detections, (Loop
Current), LB > 45dB (Notes 5, 6,
Figures 3A, 3B)

mARMS

Wire

Forward

Only

Forward

Only

FIGURE 1. OVERLOAD LEVEL (OFF HOOK, ON HOOK)

FIGURE 2. LONGITUDINAL IMPEDANCE

FIGURE 3A. LONGITUDINAL CURRENT LIMIT ON-HOOK (ACTIVE)

FIGURE 3B. LONGITUDINAL CURRENT LIMIT OFF-HOOK (ACTIVE)

TIP

RING

VRX

DCMET

0 < f < 100Hz

= V

RMS

300

TIP

RING

VRX

368

TIP

RING

SHD

VRX

368

TIP

RING

SHD

VRX

HC55120,

HC55121,

HC55130,

HC55131,

HC55140,

HC55141,

HC55142,

HC55143,

HC55150,

HC55151

4-5

OFF-HOOK LONGITUDINAL BALANCE

MIN

Longitudinal to Metallic (Note 7)
Forward and Reverse

IEEE 455 - 1985, R

, R

= 368

Normal Polarity:

Forward

Only

Forward

Only

0.2kHz < f < 1.0kHz, 0

C to 70

1.0kHz < f < 3.4kHz, 0

C to 70

0.2kHz < f < 1.0kHz, -40

C to 85

1.0kHz < f < 3.4kHz, -40

C to 85

Reverse Polarity 0.2kHz < f < 3.4kHz,
(Figure 4)

MIN

Longitudinal to Metallic (Note 7)
Forward and Reverse

, R

= 300

Normal Polarity:

Forward

Only

Forward

Only

0.2kHz < f < 1.0kHz, 0

C to 70

1.0kHz < f < 3.4kHz, 0

C to 70

0.2kHz < f < 1.0kHz, -40

C to 85

1.0kHz < f < 3.4kHz, -40

C to 85

Reverse Polarity 0.2kHz < f < 3.4kHz,
(Figure 4)

MIN

Longitudinal to 4-Wire (Note 9)
(Forward and Reverse)

Normal Polarity:

Forward

Only

Forward

Only

0.2kHz < f < 1.0kHz, 0

C to 70

1.0kHz < f < 3.4kHz, 0

C to 70

0.2kHz < f < 1.0kHz, -40

C to 85

1.0kHz < f < 3.4kHz, -40

C to 85

Reverse Polarity 0.2kHz < f < 3.4kHz,
(Figure 4)

Metallic to Longitudinal (Note 10)
Forward and Reverse

FCC Part 68, Para 68.310 (Note 8)
0.2kHz < f < 3.4kHz, (Figure 5)

Forward

Only

Forward

Only

4-Wire to Longitudinal (Note 11)
Forward and Reverse

0.2kHz < f < 3.4kHz, (Figure 5)

Forward

Only

Forward

Only

Electrical Specifications

= -40

C to 85

C, V

= +5V

5%, V

= -48V, V

= -24V, PTG = Open, R

= R

= 0

= 120k

, R

LIM

= 38.3k

, R

= 50k

, RDC_RAC = 20k

= 40k

, C

= 0.1

F, C

= 4.7

F, C

RT/REV

= 0.47

F, GND = 0V, RL = 600

. Unless Otherwise Specified.

(·)

Symbol used to indicate the test applies

to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

HC55120

HC55121

HC55130/1

HC55140/1

HC55142/3

HC55150/1

HC55120,

HC55121,

HC55130,

HC55131,

HC55140,

HC55141,

HC55142,

HC55143,

HC55150,

HC55151

4-6

FIGURE 4. LONGITUDINAL TO METALLIC AND LONGITUDINAL TO 4-WIRE BALANCE

FIGURE 5. METALLIC TO LONGITUDINAL AND 4-WIRE TO LONGITUDINAL

BALANCE

2-Wire Return Loss
Forward and Reverse

0.2kHz to 1.0kHz (Note 12, Figure 6)

Forward

Only

Forward

Only

1.0kHz to 3kHz (Note 12, Figure 6)

3kHz to 3.4kHz (Note 12, Figure 6)

TIP IDLE VOLTAGE (User Programmable)

TIPX Idle Voltage

Active, I

< 5mA

-2.6

-2.2

-1.8

Forward

Only

Forward

Only

Forward and Reverse

RING IDLE VOLTAGE (User Programmable)

RINGX Idle Voltage
Forward and Reverse

Active, I

< 5mA

-46.4

-45.3

-44.2

Forward

Only

Forward

Only

Tip open, I

< 5mA

-46.4

-45.3

-44.2

Forward and Reverse

Active, I

< 5mA

43.1

Forward

Only

Forward

Only

TR(ROH)

Pulse Metering

Forward and Reverse

Active, I

8.5mA, R

= 50k

38.1

FIGURE 6. TWO-WIRE RETURN LOSS

FIGURE 7. OVERLOAD LEVEL (4-WIRE TRANSMIT PORT), OUTPUT OFFSET

VOLTAGE AND HARMONIC DISTORTION

Electrical Specifications

= -40

C to 85

C, V

= +5V

5%, V

= -48V, V

= -24V, PTG = Open, R

= R

= 0

= 120k

, R

LIM

= 38.3k

, R

= 50k

, RDC_RAC = 20k

= 40k

, C

= 0.1

F, C

= 4.7

F, C

RT/REV

= 0.47

F, GND = 0V, RL = 600

. Unless Otherwise Specified.

(·)

Symbol used to indicate the test applies

to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

HC55120

HC55121

HC55130/1

HC55140/1

HC55142/3

HC55150/1

2.16

TIP

RING

VRX

300

2.16

TIP

RING

VRX

TIP

RING

VRX

TIP

RING

VRX

600

HC55120,

HC55121,

HC55130,

HC55131,

HC55140,

HC55141,

HC55142,

HC55143,

HC55150,

HC55151

4-7

4-WIRE TRANSMIT PORT (V

)

Overload Level, Off Hook (I

18mA)

Forward and Reverse

> 20k

, IL 1% THD) (Note 13,

Figure 7) T

= 0

C to 85

= -40

C to 0

3.2

PEAK

Forward

Only

Forward

Only

3.0

PEAK

Overload Level, On Hook (I

5mA)

Forward and Reverse

> 20k

, 1% THD)

(Note 14, Figure 7)

1.3

PEAK

Forward

Only

Forward

Only

Output Offset Voltage

Forward and Reverse

= 0, Z

, (Note 15, Figure 7)

-200

200

Forward

Only

Forward

Only

Output Impedance
(Guaranteed by Design)

0.2kHz < f < 03.4kHz

0.1

4-WIRE RECEIVE PORT (VRX)

VRX Input Impedance
(Guaranteed by Design)

0.2kHz < f < 3.4kHz

500

600

FREQUENCY RESPONSE (OFF-HOOK)

2-Wire to 4-Wire
Forward and Reverse

Relative to 0dBm at 1.0kHz, E

= 0V

Forward

Only

Forward

Only

0.3kHz < f < 3.4kHz

-0.15

0.15

f = 8.0kHz (Note 16, Figure 8)

0.24

0.5

f = 12kHz (Note 16, Figure 8)

0.58

1.0

f = 16kHz (Note 16, Figure 8)

1.0

1.5

4-Wire to 2-Wire
Forward and Reverse

Relative to 0dBm at 1.0kHz, E

= 0V

0.3kHz < f < 3.4kHz

-0.15

0.15

Forward

Only

Forward

Only

f = 8kHz (Note 17, Figure 8)

-0.5

0.24

f = 12kHz (Note 17, Figure 8)

-1.0

0.58

f = 16kHz (Note 17, Figure 8)

-1.5

1.0

4-Wire to 4-Wire
Forward and Reverse

Relative to 0dBm at 1.0kHz, E

= 0V

Forward

Only

Forward

Only

0.3kHz < f < 3.4kHz (Note 18, Figure 8) -0.15

0.15

8kHz, 12kHz, 16kHz (Note 18, Figure 8)

-0.5

0.5

FIGURE 8. FREQUENCY RESPONSE, INSERTION LOSS, GAIN TRACKING

AND HARMONIC DISTORTION

FIGURE 9. IDLE CHANNEL NOISE

Electrical Specifications

= -40

C to 85

C, V

= +5V

5%, V

= -48V, V

= -24V, PTG = Open, R

= R

= 0

= 120k

, R

LIM

= 38.3k

, R

= 50k

, RDC_RAC = 20k

= 40k

, C

= 0.1

F, C

= 4.7

F, C

RT/REV

= 0.47

F, GND = 0V, RL = 600

. Unless Otherwise Specified.

(·)

Symbol used to indicate the test applies

to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

HC55120

HC55121

HC55130/1

HC55140/1

HC55142/3

HC55150/1

600

TIP

RING

VRX

PTG

OPEN

600

TIP

RING

VRX

HC55120,

HC55121,

HC55130,

HC55131,

HC55140,

HC55141,

HC55142,

HC55143,

HC55150,

HC55151

4-8

INSERTION LOSS

2-Wire to 4-Wire
Forward and Reverse

0dBm, 1kHz

PTG = Open (Note 19, Figure 8)

-0.2

0.2

Forward

Only

Forward

Only

PTG = GND (Note 20, Figure 8)

-6.22

-6.02

-5.82

4-Wire to 2-Wire
Forward and Reverse

0dBm, 1kHz (Note 21, Figure 8)

-0.2

0.2

Forward

Only

Forward

Only

GAIN TRACKING (Ref = -10dBm, at 1.0kHz)

2-Wire to 4-Wire
Forward and Reverse

-40dBm to +3dBm (Note 22, Figure 8)

-0.1

0.1

Forward

Only

Forward

Only

-55dBm to -40dBm (Note 22, Figure 8)

-0.2

0.2

4-Wire to 2-Wire
Forward and Reverse

-40dBm to +3dBm (Note 23, Figure 8)

-0.1

0.1

Forward

Only

Forward

Only

-55dBm to -40dBm (Note 23, Figure 8)

-0.2

0.2

NOISE

Idle Channel Noise at 2-Wire

C-Message Weighting

10.5

dBrnC

Forward

Only

Forward

Only

Forward and Reverse

Psophometric Weighting (Note 24,
Note 30, Figure 9)

-79.5

-77

dBmp

Idle Channel Noise at 4-Wire

C-Message Weighting

10.5

dBrnC

Forward

Only

Forward

Only

Forward and Reverse

Psophometrical Weighting
(Note 25, Note 30, Figure 9)

-79.5

-77

dBmp

HARMONIC DISTORTION

2-Wire to 4-Wire
Forward and Reverse

0dBm, 0.3kHz to 3.4kHz
(Note 26, Figure 7)

-67

-50

Forward

Only

Forward

Only

4-Wire to 2-Wire
Forward and Reverse

0dBm, 0.3kHz to 3.4kHz
(Note 27, Figure 8)

-67

-50

Forward

Only

Forward

Only

FIGURE 10. CONSTANT LOOP CURRENT TOLERANCE

FIGURE 11. TIPX VOLTAGE

Electrical Specifications

= -40

C to 85

C, V

= +5V

5%, V

= -48V, V

= -24V, PTG = Open, R

= R

= 0

= 120k

, R

LIM

= 38.3k

, R

= 50k

, RDC_RAC = 20k

= 40k

, C

= 0.1

F, C

= 4.7

F, C

RT/REV

= 0.47

F, GND = 0V, RL = 600

. Unless Otherwise Specified.

(·)

Symbol used to indicate the test applies

to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

HC55120

HC55121

HC55130/1

HC55140/1

HC55142/3

HC55150/1

600

TIP

RING

VRX

LIM

38.3k

TIP

RING

VRX

HC55120,

HC55121,

HC55130,

HC55131,

HC55140,

HC55141,

HC55142,

HC55143,

HC55150,

HC55151

4-9

BATTERY FEED CHARACTERISTICS

Constant Loop Current Tolerance

18mA

45mA,

Forward

Only

Forward

Only

= 26.5mA, R

LIM

= 38.3k

Forward and Reverse

(Note 27, Figure 10)

0.92I

1.08I

Tip Open State TIPX Leakage
Current

S = Closed (Figure 11)

-200

Tip Open State RINGX Current

= 0

, V

= -48V, R

LIM

= 38.3k

22.6

26.8

= 2.5k

, V

= -48V (Figure 11)

15.5

17.1

18.2

Tip Open State RINGX Voltage

5mA < I

< 26mA (Figure 11)

42.8

Tip Voltage (Ground Start)

Active State, (S Open) R

= 150

(Figure 11)

-5.3

-4.8

-4.3

Tip Voltage (Ground Start)

Active State, (S Closed) Tip Lead to

-48V Through 7k

, Ring Lead to

Ground Through 150

(Figure 11)

-5.3

-4.8

-4.3

Open Circuit State Loop Current

(Active) R

= 0

-20

LOOP CURRENT DETECTOR

Programmable Threshold

LTh

= (500/ R

)

5mA,

0.9I

LTh

1.1I

LTh

Forward

Only

Forward

Only

Forward and Reverse

LTh

= 8.5mA

= 58.8k

GROUND KEY DETECTOR

Ground Key Detector Threshold
Tip/Ring Current Difference

Tip Open

Active (Note 29, R1 = 2.5k

, Figure 12)

12.5

27.5

LINE VOLTAGE MEASUREMENT

Pulse Width (GKD_LVM)

Pulse Width = (20)(C

REV...

LIM

)

0.32

0.36

0.4

ms/V

RING TRIP DETECTOR (DT, DR)

Ring Trip Comparator Current

Source Res = 2M

Input Common-Mode Range

Source Res = 2M

200

Electrical Specifications

= -40

C to 85

C, V

= +5V

5%, V

= -48V, V

= -24V, PTG = Open, R

= R

= 0

= 120k

, R

LIM

= 38.3k

, R

= 50k

, RDC_RAC = 20k

= 40k

, C

= 0.1

F, C

= 4.7

F, C

RT/REV

= 0.47

F, GND = 0V, RL = 600

. Unless Otherwise Specified.

(·)

Symbol used to indicate the test applies

to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

HC55120

HC55121

HC55130/1

HC55140/1

HC55142/3

HC55150/1

HC55120,

HC55121,

HC55130,

HC55131,

HC55140,

HC55141,

HC55142,

HC55143,

HC55150,

HC55151

4-10

RING RELAY DRIVER

SAT

at 30mA

= 30mA

0.2

0.5

SAT

at 40mA

= 40mA

0.52

0.8

Off State Leakage Current

= 13.2V

0.1

TEST RELAY DRIVER (TRLY1, TRLY2)

SAT

at 30mA

= 30mA

0.3

0.5

NA/

SAT

at 40mA

= 40mA

0.62

0.9

NA/

Off State Leakage Current

= 13.2V

NA/

FIGURE 12. GROUND KEY DETECT

DIGITAL INPUTS (C1, C2, C3)

Input Low Voltage, V

0.8

Input High Voltage, V

2.0

Input Low Current, I

= 0.4V

-10

Input High Current, I

= 2.5V

DETECTOR OUTPUTS (SHD, GKD_LVM)

SHD Output Low Voltage, V

Forward, Reverse

= 1mA

0.5

Forward

Only

Forward

Only

SHD Output High Voltage, V

Forward, Reverse

= 100

2.7

Forward

Only

Forward

Only

GKD_LVM Output Low Voltage,
V

Forward and Tip Open

= 1mA

= 2.5k

(Figure 11)

0.5

GKD

GKD_

LVM

GKD_

LVM

GKD_LVM Output High Voltage,
V

Forward and Tip Open

= 100

2.7

GKD

GKD_

LVM

GKD_

LVM

Internal Pull-Up Resistor

Electrical Specifications

= -40

C to 85

C, V

= +5V

5%, V

= -48V, V

= -24V, PTG = Open, R

= R

= 0

= 120k

, R

LIM

= 38.3k

, R

= 50k

, RDC_RAC = 20k

= 40k

, C

= 0.1

F, C

= 4.7

F, C

RT/REV

= 0.47

F, GND = 0V, RL = 600

. Unless Otherwise Specified.

(·)

Symbol used to indicate the test applies

to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

HC55120

HC55121

HC55130/1

HC55140/1

HC55142/3

HC55150/1

TIP

RING

SHD

2.5k

VRX

HC55120,

HC55121,

HC55130,

HC55131,

HC55140,

HC55141,

HC55142,

HC55143,

HC55150,

HC55151

4-11

POWER DISSIPATION (V

= -48V, V

= -24V)

Open Circuit State

C1, C2, C3 = 0, 0, 0

Forward

Only

Forward

Only

On-Hook, Active

C1, C2, C3 = 0, 1, 0
C1, C2, C3 = 1, 1, 0

Forward and Reverse

= 0mA, Longitudinal

Current = 0mA

Forward

Only

Forward

Only

POWER SUPPLY CURRENTS (V

= -48V, V

= -24V)

Current, I

Open Circuit State

2.25

3.0

Forward

Only

Forward

Only

Current, I

0.3

0.45

Forward

Only

Forward

Only

Current, I

0.022

0.035

Forward

Only

Forward

Only

Current, I

Forward and Reverse

Active State
I

= 0mA, Longitudinal

Current = 0mA

2.7

3.6

Forward

Only

Forward

Only

Current, I

Forward and Reverse

0.8

1.06

Forward

Only

Forward

Only

Current, I

Forward and Reverse

0.01

Forward

Only

Forward

Only

POWER SUPPLY REJECTION RATIOS

to 2 or 4 Wire Port

Forward and Reverse

Active State R

= 600

50Hz < f < 3400Hz, V

=100mV

Forward

Only

Forward

Only

to 2 or 4 Wire Port

Forward and Reverse

Forward

Only

Forward

Only

to 2 or 4 Wire Port

Forward and Reverse

Forward

Only

Forward

Only

TEMPERATURE GUARD

Junction Threshold Temperature

175

Electrical Specifications

= -40

C to 85

C, V

= +5V

5%, V

= -48V, V

= -24V, PTG = Open, R

= R

= 0

= 120k

, R

LIM

= 38.3k

, R

= 50k

, RDC_RAC = 20k

= 40k

, C

= 0.1

F, C

= 4.7

F, C

RT/REV

= 0.47

F, GND = 0V, RL = 600

. Unless Otherwise Specified.

(·)

Symbol used to indicate the test applies

to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

HC55120

HC55121

HC55130/1

HC55140/1

HC55142/3

HC55150/1

HC55120,

HC55121,

HC55130,

HC55131,

HC55140,

HC55141,

HC55142,

HC55143,

HC55150,

HC55151

4-12

Notes

2. Overload Level (Two-Wire Port, Off Hook) - The overload

level is specified at the 2-wire port (V

) with the signal source at

the 4-wire receive port (E

). R

= 600

, I

DCMET

18mA.

Increase the amplitude of E

until 1% THD is measured at V

Reference Figure 1.

3. Overload Level (Two-Wire Port, On Hook) - The overload

level is specified at the 2-wire port (V

) with the signal source at

the 4-wire receive port (E

). R

, I

DCMET

= 0mA. Increase

the amplitude of E

until 1% THD is measured at V

Reference Figure 1.

4. Longitudinal Impedance - The longitudinal impedance is

computed using the following equations, where TIP and RING
voltages are referenced to ground. L

, L

, V

, A

and A

are defined in Figure 2.
(TIP) L

= V

(RING) L

= V

where: E

= 1V

RMS

(0Hz to 100Hz)

5. Longitudinal Current Limit (On-Hook Active) - On-Hook

longitudinal current limit is determined by increasing the (60Hz)
amplitude of E

(Figure 3A) until the 2-wire longitudinal current

is greater than 28mARMS/Wire. Under this condition, SHD pin
remains low (no false detection) and the 2-wire to 4-wire
longitudinal balance is verified to be greater than 45dB
(LB

2-4

= 20log VTX/E

6. Longitudinal Current Limit (Off-Hook Active) - Off-Hook

longitudinal current limit is determined by increasing the (60Hz)
amplitude of E

(Figure 3B) until the 2-wire longitudinal current

is greater than 28mARMS/Wire. Under this condition, SHD pin
remains high (no false detection) and the 2-wire to 4-wire
longitudinal balance is verified to be greater than 45dB
(LB

2-4

= 20log VTX/E

7. Longitudinal to Metallic Balance - The longitudinal to

metallic balance is computed using the following equation:

BLME = 20 log (E

), where: E

and V

are defined in

Figure 4.

8. Metallic to Longitudinal FCC Part 68, Para 68.310 - The

metallic to longitudinal balance is defined in this spec.

9. Longitudinal to Four-Wire Balance - The longitudinal to 4-wire

balance is computed using the following equation:

BLFE = 20 log (E

), E

and V

are defined in Figure 4.

10. Metallic to Longitudinal Balance - The metallic to longitudinal

balance is computed using the following equation:

BMLE = 20 log (E

), E

= 0

where: E

TR,

and E

are defined in Figure 5.

11. Four-Wire to Longitudinal Balance - The 4-wire to longitudinal

balance is computed using the following equation:

BFLE = 20 log (E

), E

= source is removed.

where: E

RX,

and E

are defined in Figure 5.

12. Two-Wire Return Loss - The 2-wire return loss is computed

using the following equation:
r = -20 log (2V

) where: Z

= The desired impedance; e.g.,

the characteristic impedance of the line, nominally 600

(Reference Figure 6).

13. Overload Level (4-Wire Port Off-Hook) - The overload level

is specified at the 4-wire transmit port (V

) with the signal

source (E

) at the 2-wire port, Z

= 20k

= 600

(Reference Figure 7). Increase the amplitude of E

until 1%

THD is measured at V

. Note the PTG pin is open, and the

gain from the 2-wire port to the 4-wire port is equal to 1.

14. Overload Level (4-Wire Port On-Hook) - The overload level is

specified at the 4-wire transmit port (V

) with the signal source

) at the 2-wire port, Z

= 20k

(Reference Figure 7).

Increase the amplitude of E

until 1% THD is measured at V

Note the PTG pin is open, and the gain from the 2-wire port to
the 4-wire port is equal to 1.

15. Output Offset Voltage - The output offset voltage is specified

with the following conditions: E

= 0, R

= 600

, Z

and is

measured at V

. E

, R

, V

and Z

are defined in Figure 7.

16. Two-Wire to Four-Wire Frequency Response - The 2-wire to

4-wire frequency response is measured with respect to
E

= 0dBm at 1.0kHz, E

= 0V (VRX input floating), R

= 600

The frequency response is computed using the following equation:

2-4

= 20 log (V

), vary frequency from 300Hz to 3.4kHz

and compare to 1kHz reading.

, V

, R

and E

are defined in Figure 8.

17. Four-Wire to Two-Wire Frequency Response - The 4-wire to 2-

wire frequency response is measured with respect to E

= 0dBm

at 1.0kHz, E

source removed from circuit, R

= 600

. The

frequency response is computed using the following equation:

4-2

= 20 log (V

), vary frequency from 300Hz to 3.4kHz

and compare to 1kHz reading.

, R

and E

are defined in Figure 8.

18. Four-Wire to Four-Wire Frequency Response - The 4-wire

to 4-wire frequency response is measured with respect to
E

= 0dBm at 1.0kHz, E

source removed from circuit,

= 600

. The frequency response is computed using the

following equation:

4-4

= 20 log (V

), vary frequency from 300Hz to 3.4kHz

and compare to 1kHz reading.

TX ,

and E

are defined in Figure 8.

19. Two-Wire to Four-Wire Insertion Loss (PTG = Open) - The

2-wire to 4-wire insertion loss is measured with respect to
E

= 0dBm at 1.0kHz input signal, E

= 0 (VRX input floating),

= 600

and is computed using the following equation:

2-4

= 20 log (V

)

where: V

, V

, R

and E

are defined in Figure 8. (Note:

The fuse resistors, R

, impact the insertion loss. The specified

insertion loss is for R

= R

= 0).

20. Two-Wire to Four-Wire Insertion Loss (PTG = AGND) - The

2-wire to 4-wire insertion loss is measured with respect to E

0dBm at 1.0kHz input signal, E

= 0 (VRX input floating), R

600

and is computed using the following equation:

2-4

= 20 log (V

)

where: V

, V

, R

and E

are defined in Figure 8. (Note:

The fuse resistors, R

, impact the insertion loss. The specified

insertion loss is for R

= R

= 0).

21. Four-Wire to Two-Wire Insertion Loss - The 4-wire to 2-wire

insertion loss is measured based upon E

= 0dBm, 1.0kHz

input signal, E

source removed from circuit, R

= 600

and is

computed using the following equation:

4-2

= 20 log (V

)

where: V

, R

and E

are defined in Figure 8.

22. Two-Wire to Four-Wire Gain Tracking - The 2-wire to 4-wire

gain tracking is referenced to measurements taken for
E

= -10dBm, 1.0kHz signal, E

= 0 (VRX output floating),

= 600

and is computed using the following equation.

2-4

= 20

log (V

) vary amplitude -40dBm to +3dBm, or

-55dBm to -40dBm and compare to -10dBm reading.

, R

and V

are defined in Figure 8.

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

4-13

23. Four-Wire to Two-Wire Gain Tracking - The 4-wire to 2-wire

gain tracking is referenced to measurements taken for
E

= -10dBm, 1.0kHz signal, E

source removed from circuit,

= 600

and is computed using the following equation:

4-2

= 20

log (V

) vary amplitude -40dBm to +3dBm,

or -55dBm to -40dBm and compare to -10dBm reading.

, R

and E

are defined in Figure 8. The level is specified at

the 4-wire receive port and referenced to a 600

impedance level.

24. Two-Wire Idle Channel Noise - The 2-wire idle channel noise

at V

is specified with the 2-wire port terminated in 600

)

and with the 4-wire receive port (VTX) floating (Reference
Figure 9).

25. Four-Wire Idle Channel Noise - The 4-wire idle channel noise

at V

is specified with the 2-wire port terminated in 600

The noise specification is with respect to a 600

impedance

level at V

. The 4-wire receive port (VTX) floating (Reference

Figure 9).

26. Harmonic Distortion (2-Wire to 4-Wire) - The harmonic

distortion is measured within the voice band with the following
conditions. E

= 0dBm at 1kHz, R

= 600

. Measurement

taken at V

. (Reference Figure 7).

27. Harmonic Distortion (4-Wire to 2-Wire) - The harmonic

distortion is measured within the voice band with the following
conditions. E

= 0dBm0. Vary frequency between 300Hz and

3.4kHz, R

= 600

. Measurement taken at V

. (Reference

Figure 8).

28. Constant Loop Current - The constant loop current is

calculated using the following equation:

= 1000/R

LIM

= V

/600 (Reference Figure 10).

29. Ground Key Detector - (TRIGGER) Ground the Ring pin

through a 2.5k

resistor and verify that GKD goes low.

(RESET) Disconnect the Ring pin and verify that GKD goes
high.

(Hysteresis) Compare difference between trigger and reset.

30. Electrical Test - Not tested in production at -40

Circuit Operation and Design Information

The UniSLIC14 family of SLICs are voltage feed current
sense Subscriber Line Interface Circuits (SLIC). For short
loop applications, the voltage between the tip and ring
terminals varies to maintain a constant loop current. For long
loop applications, the voltage between the tip and ring
terminals are relatively constant and the loop current varies
in proportion to the load.

The tip and ring voltages for various loop resistances are
shown in Figure 13. The tip voltage remains relatively
constant as the ring voltage moves to limit the loop current
for short loops.

The loop current for various loop resistances are shown in
Figure 14. For short loops, the loop current is limited to the
programmed current limit, set by RILIM. For long loop
applications, the loop current varies in accordance with
Ohms law for the given tip to ring voltage and the loop
resistance.

The following discussion separates the SLIC's operation into
its DC and AC paths, then follows up with additional circuit
and design information.

DC Feed Curve

The DC feed curve for the UniSLIC14 family is user
programmable. The user defines the on hook and off hook
overhead voltages (including the overhead voltage for off
hook pulse metering if applicable), the maximum and
minimum loop current limits, the switch hook detect
threshold and the battery voltage. From these requirements,
the DC feed curve is customized for optimum operation in
any given application. An Excel spread sheet to calculate the
external components can be downloaded off our web site
www.intersil.com/telecom/unislic14.xls.

FIGURE 13. TIP AND RING VOLTAGES vs LOOP RESISTANCE

TIP AND RING V

GES (V)

LOOP RESISTANCE (

)

-5

-10

-15

-20

-25

-30

-35

-50

-40

-45

200

600

1000 1400 1800 2000

10K

CONSTANT

LOOP CURRENT

REGION

VBH = -48V
RD = 41.2k

ROH = 38.3k

RDC_RAC = 19.6k

RILim = 33.2k

CONSTANT TIP TO RING

VOLTAGE REGION

-44.5V

-2.5V

TIP

RING

FIGURE 14. LOOP CURRENT vs LOOP RESISTANCE

LOOP CURRENT (mA)

LOOP RESISTANCE (

)

200

600

1.4K 1.8K

2.2K 2.6K

3.8K

3.0K 3.4K

CONSTANT

LOOP CURRENT

REGION

VBH = -48V
RD = 41.2k

ROH = 38.3k

RDC_RAC = 19.6k

RILim = 33.2k

CONSTANT TIP TO RING

VOLTAGE REGION

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

4-14

On Hook Overhead Voltage

The on hook overhead voltage
at the load (V

(on) at Load)

is independent of the V

battery voltage. Once set, the
on hook voltage remains
constant as the V

battery

voltage changes. The on hook
voltage also remains constant
over temperature and line
leakages up to 0.6 times the

Switch Hook Detect threshold (I

SHD

). The maximum loop

current for a constant on hook overhead voltage is defined
as ISH-.

The on hook overhead voltage, required for a given signal
level at the load, must take into account the AC voltage drop
across the 2 external protection resistors (R

) and the 2

internal sense resistors (R

) as shown in Figure 16. The AC

on hook overload voltage is calculated using Equation 1.

where

OH(on) at Load

= On hook overhead voltage at load

sp(on)

= Required on hook transmission for speech

= Protection Resistors (Typically 30

)

= Internal Sense Resistors (40

)

= AC load impedance for (600

)

1.5V = Additional on hook overhead voltage requirement

To account for any process and temperature variations in the
performance of the SLIC, 1.5V is added to the overhead
voltage requirement for the on hook case in Equation 1 and
2.0V for the off hook case in Equation 3. Note the 2.5V
overhead is automatically generated in the SLIC and is not
part of the external overhead programming.

Off Hook Overhead Voltage

The off hook overhead
voltage V

(off) at Load is

also independent of the V

battery voltage and remains
constant over temperature.
The required off hook
overhead voltage is the sum
of the AC and DC voltage
drops across the internal
sense resistors (R

, the

Internal overhead voltage automatically generated by the SLIC.

FIGURE 15. UniSLIC14 DC FEED CURVE

VBH

2.5V

VOH(off) AT LOAD

ISH-

ILOOP(min)

ILOOP(max)

60k

SLOPE

RLOOP(max)

SLIC SELF PROGRAMMING

TIP T

RING ABSOLUTE V

GE (V)

LOOP CURRENT (mA)

IOH

CONSTANT
CURRENT
REGION

SAT

VOH(on) AT LOAD

SHD

OH(on)

2.5V

ON HOOK

ISH-

TIP T

RING V

LOOP CURRENT

DC FEED CURVE

OVERHEAD

ISH- = I

SHD

(0.6)

SHD

(EQ. 1)

OH on

(

)

at Load

sp on

(

)

------------------------------

1.5V

FIGURE 16. OVERHEAD VOLTAGE OF THE TIP AND RING

AMPLIFIERS

TIP AND RING

INTERNAL SENSE

EXTERNAL PROTECTION
RESISTOR

AMPLIFIERS

OVERHEAD VOLTAGE

RESISTORS

Where:

REQUIRED

(ON, OFF)

is the required on hook or offhook

transmission delivered to the load.

(LOAD)

UniSLIC14

OH ON OFF

(

)

------------------------------

SAT

OH(off)

2.5V

OFF HOOK

TIP T

RING V

LOOP CURRENT

LOOP(min)

DC FEED CURVE

OVER HEAD

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

4-15

protection resistors (R

), the required (peak) off hook

voltage for speech (V

sp(off)

) and the required (peak) off hook

voltage for the pulse metering (V

pm(off)

), if applicable.

The off hook overhead voltage is defined in Equation 2 and
calculated using Equation 3.

where:

OH(off) at Load

= Off hook overhead voltage at load

sense

) = Required overhead for the DC voltage drop

across sense resistors (2R

x Iloop

(max)

)

sp(off)

= Required (peak) off hook AC voltage for speech

pm(off)

= Required (peak) off hook AC voltage for pulse

metering

where:

80 = 2R

+ 2R

INT

(reference Figure 17)

= Pulse metering load impedance (typically 200

2.0V = Additional off hook overhead voltage requirement

SAT

Resistance Calculation

The R

SAT

resistance of the DC feed curve is used to

determine the value of the RDC_RAC resistor (Equation 6).
The value of this resistor has an effect on both the on hook
and off hook overheads. In most applications the off hook
condition will dominate the overhead requirements.
Therefore, we'll start by calculating the R

SAT

value for the off

hook conditions and then verify that the on hook conditions
are also satisfied.

When considering the Off
hook condition, R

SAT

is equal

to V

OH(off) at Load

divided by

Iloop

(min)

(Equation 4).

For the given system
requirements (recommended
application circuit in back of
data sheet): Iloop (min) =
20mA, Iloop (max) = 30mA,
V

sp(off)

= 3.2V

PEAK

spm(off)

= 0V

PEAK

OH(off) at Load

= 8.34V the

value of R

SAT(off)

is equal to 417

as calculated in Equation 4.

Before using this R

SAT

value, to calculate the RDC_RAC

resistor, we need to verify that the on hook requirements will
also be met.

The on hook overhead voltage
calculated with the off hook
R

SAT

SAT(off)

), is given in

Equation 5 and equals 3.0V.
The on hook overhead
calculated with Equation 1
equals 2.85V for the given
system requirements
(recommended application
circuit in back of data sheet):
Switch Hook Detect threshold
= 12mA, ISH- = (0.6)12mA =
7.2mA, V

sp(on)

= 0.775V

RMS

Thus, the on hook overhead
requirements of 2.85V will be

met if we use the R

SAT(off)

value.

If the on hook overhead requirement is not met, then we
need to use the R

SAT(on)

value to determine the RDC_RAC

resistor value. The external saturation guard resistor
RDC_RAC is equal to 50 times R

SAT

In the example above R

SAT

would equal 417

and

RDC_RAC would then equal to 20.85k

(closest standard

value is 21k

The Switch Hook Detect threshold current is set by resistor
R

and is calculated using Equation 7. For the above

example R

is calculated to be 41.6k

(500/12mA). The

next closest standard value is 41.2k

The true value of ISH-, for the selected value of R

is given

by Equation 8:

For the example above, ISH- equals 7.28mA (500 x 0.6/ 41.2K).
Verify that the value of ISH- is above the suspected line
leakage of the application. The UniSLIC family will provide a
constant on hook voltage level for leakage currents up to this
value of line leakage.

(EQ. 2)

OH off

(

)

at Load

OH Rsense

(

)

sp off

(

)

pm off

(

)

(EQ. 3)

OH(off) at Load

LOOP max

(

)

sp off

(

)

------------------------------

+ V

pm off

(

)

------------------------------

2.0V

SAT

OH(off)

2.5V

TIP T

RING V

LOOP CURRENT

LOOP(min)

OH(off) AT LOAD

LOOP(min)

SAT

DC FEED CURVE

SAT(off)

OH(off) at Load

LOOP(min)

----------------------------------------

8.34V

20mA

----------------

417

(EQ. 4)

OH(on) AT LOAD

ISH-

(min)

SAT

OH(on)

2.5V

ISH-(min)

LOOP CURRENT

DC FEED CURVE

TIP T

RING V

SAT on

(

)

2.85V

7.2mA

------------------

395

SAT

OH on

(

)

ISH-

(

)

SAT off

(

)

(

)

(EQ. 5)

OH on

(

)

7.2mA

417

OH on

(

)

3.0V

RDC_RAC = 50 x R

SAT

(EQ. 6)

500

SHD

------------

(EQ. 7)

ISH- =

500

----------

(0.6)

(EQ. 8)

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

4-16

The R

resistor, which

is used to set the offhook
overhead voltage, is
calculated using
Equations 9 and 10.

is defined as the

difference between the
I

LOOP(min)

and ISH-.

Substituting Equation 8

for ISH- into Equation 9 and solving for R

defines R

terms of I

LOOP(min)

and R

Equation 10 can be used to determine the actual ISH- value
resulting from the R

resistor selected. The value of R

should be the next standard value that is lower than that
calculated. This will insure meeting the I

LOOP(min)

requirement. ROH for the above example equals 39.1k

The current limit is set by a single resistor and is calculated
using Equation 11.

The maximum loop
resistance is calculated
using Equation 12. The
resistance of the
protection resistors
(2R

) is subtracted out

to obtain the maximum
loop length to meet the
required off hook

overhead voltage. If R

LOOP(MAX)

meets the loop length

requirements you are done. If the loop length needs to be
longer, then consider adjusting one of the following: 1) the
SHD threshold, 2) minimum loop current requirement or 3)
the on and off hook signal levels.

SLIC in the Active Mode

Figure 17 shows a simplified AC transmission model. Circuit
analysis yields the following design equations:

Substitute Equation 14 into Equation 15

Substitute Equation 16 into Equation 17

Substitute Equation 18 into Equation 19

Substituting -V

into Equation 20 for I

and rearranging

to solve for V

results in Equation 21

where:

= The input voltage at the VRX pin.

= An internal node voltage that is a function of the loop

current detector and the impedance matching networks.

= Internal current in the SLIC that is the difference

between the input receive current and the feedback current.

= The AC metallic current.

= A protection resistor (typical 30

= An external resistor/network for matching the line

impedance.

= The tip to ring voltage at the output pins of the SLIC.

= The tip to ring voltage including the voltage across the

protection resistors.

= The line impedance.

= The input impedance of the SLIC including the

protection resistors.

(AC) 4-Wire to 2-Wire Gain

The 4-wire to 2-wire gain is equal to V

From Equation 21 and the relationship Z

= 200(Z

-2R

Notice that the phase of the 4-wire to 2-wire signal is 180

out of phase with the input signal.

SAT

OH(off)

2.5V

OFF HOOK

TIP T

RING V

LOOP CURRENT

LOOP(min)

DC FEED CURVE

ISH-

OVER HEAD

500
I

----------

500

LOOP(min)

- ISH-

--------------------------------------------

(EQ. 9)

500

LOOP(min)

- 500(.6)

------------------------------------------------------------

(EQ. 10)

LIM

1000

LOOP(max)

-----------------------------

(EQ. 11)

SAT

OH(off)

2.5V

TIP T

RING V

LOOP CURRENT

LOOP(min)

DC FEED CURVE

LOOP(MAX)

LOOP(max)

SAT

OH off

(

)

[

]

LOOP(min)

-------------------------------------------------------------------------------

-2R

(EQ. 12)

= I

80k

----------

200

(

)

(EQ. 13)

-------

(

)

(EQ. 14)

500k

-------------

500k

-------------

= I

Node Equation

(EQ. 15)

500k

-------------

(

)

1000k

-----------------------------------------

(EQ. 16)

500k - V

+ I

500k = 0

Loop Equation

(EQ. 17)

(

)

(EQ. 18)

-I

+ V

= 0

Loop Equation

(EQ. 19)

(EQ. 20)

-----------

(EQ. 21)

4-2

-----------

= -2

+ Z

-------------------------

200

----------

----------------------------------------------

(EQ. 22)

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

4-17

(AC) 2-Wire to 4-Wire Gain

The 2-wire to 4-wire gain is equal to V

with V

= 0

From Equation 18 with V

= 0

Substituting Equation 24 into Equation 23 and simplifying.

By design, VTX = -VTX´, therefore

A more useful form of the equation is rewritten in terms of
V

. A voltage divider equation is written to convert

from E

to V

as shown in Equation 27.

Rearranging Equation 27 in terms of E

, and substituting

into Equation 26 results in an equation for 2-wire to 4-wire
gain that's a function of the synthesized input impedance of
the SLIC (Z

) and the protection resistors (R

Notice that the phase of the 2-wire to 4-wire signal is in
phase with the input signal.

(AC) 4-Wire to 4-Wire Gain

The 4-wire to 4-wire gain is equal to V

, E

= 0.

From Equation 18.

Substituting -V

into Equation 29 for I

results in

Equation 30.

Substituting Equation 21 for V

in Equation 30 and

simplifying results in Equation 31.

(AC) 2-Wire Impedance

The AC 2-wire impedance (Z

) is the impedance looking

into the SLIC, including the fuse resistors. The formula to
calculate the proper Z

for matching the 2-wire impedance is

shown in Equation 32.

Equation 32 can now be used to match the SLIC's
impedance to any known line impedance (Z

TIP

RING

UniSLIC14

FIGURE 17. SIMPLIFIED AC TRANSMISSION CIRCUIT

500K

PTG

= I

-2R

)

1/80K

= 200 (Z

- 2R

)

A = 1

INT

Loop Equation

(EQ. 23)

(

)

(EQ. 24)

(

)

(EQ. 25)

2-4

----------

(

)

(

)

----------------------------------------

(

)

(

)

---------------------------------

(EQ. 26)

------------------------

(EQ. 27)

2-4

-----------

- 2R

-----------------------------

(EQ. 28)

(

)

(EQ. 29)

(

)

---------------------------------------------

(EQ. 30)

-----------

+ 2R

------------------------

(EQ. 31)

200

(

)

(EQ. 32)

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

4-18

EXAMPLE:

Calculate Z

to make Z

= 600

in series with 2.16

= 30

= 114k

in series with 0.0108

Note: Some impedance models, with a series capacitor, will
cause the op-amp feedback to behave as an open circuit
DC. A resistor with a value of about 10 times the reactance
of the Z

capacitor (2.16

F/200 = 10.8nF) at the low

frequency of interest (200Hz for example) can be placed in
parallel with the capacitor in order to solve the problem
(736k

for a 10.8nF capacitor).

Calculating Tip and Ring Voltages

The on hook tip to ground voltage is calculated using
Equation 34. The minus 1.0 volt results from the SLIC self
programming. ISH- is the maximum loop current for a
constant on hook overhead voltage (ISH- = I

SHD

(0.6)) and

the value of R

SAT(off)

is calculated in Equation 4.

On hook Tip Voltage

The off hook tip to ground voltage is calculated using
Equation 35. I

LOOP(min)

is the minimum loop current

allowed by the design and the value of R

SAT(off)

is calculated

in Equation 4.

Off hook Tip Voltage

The on hook ring to ground voltage is calculated using
Equation 36. The 1.5 volt results from the SLIC self
programming. ISH- is the maximum loop current for a
constant on hook overhead voltage (ISH- = I

SHD

(0.6)) and

the value of R

SAT(off)

is calculated in Equation 4.

On hook Ring Voltage

The calculation of the ring voltage with respect to ground in
the off hook condition is dependent upon whether the SLIC
is in current limit or not.

The off hook ring to ground voltage (in current limit) is
calculated using Equation 37. I

LIM

is the programmed loop

current limit and R

is the load resistance across tip and

ring. The minus 0.2V is a correction factor for the 60k

slope

in Figure 15.

Off hook Ring Voltage in Current Limit

The off hook ring to ground voltage (not in current limit) is
calculated using Equation 38. The 1.5V results from the
SLIC self programming. I

LOOP(min)

is the minimum loop

current allowed by the design and the value of R

SAT(off)

calculated in Equation 4.

Off hook Ring Voltage not in Current Limit

Layout Considerations

Systems with Dual Supplies (V

and V

)

If the V

supply is not derived from the V

supply, it is

recommended that an additional diode be placed in series
with the V

supply. The orientation of this diode is anode

on pin 8 of the device and cathode to the external supply.
This external diode will inhibit large currents and potential
damage to the SLIC, in the event the V

supply is shorted

to GND. If V

is derived from V

then this diode is not

required.

Floating the PTG Pin

The PTG pin is a high impedance pin (500k

) that is used to

program the 2-wire to 4-wire gain to either 0dB or -6dB.

If 0dB is required, it is necessary to float the PTG pin. The
PC board interconnect should be as short as possible to
minimize stray capacitance on this pin. Stray capacitance on
this pin forms a low pass filter and will cause the 2-wire to
4-wire gain to roll off at the higher frequencies.

If a 2-wire to 4-wire gain of -6dB is required, the PTG pin
should be grounded as close to the device as possible.

SPM Pin

For optimum performance, the PC board interconnect the
SPM pin should be as short as possible. If pulses metering
is not being used, then this pin should be grounded as close
to the device pin as possible.

RLIM Pin

The current limiting resistor R

LIM

needs to be as close to the

RLIM pin as possible.

Layout of the 2-Wire Impedance Matching
Resistor Z

Proper connection to the ZT pin is to have the external Z

network as close to the device pin as possible.

The ZT pin is a high impedance pin that is used to set the
proper feedback for matching the impedance of the 2-wire
side. This will eliminate circuit board capacitance on this pin
to maintain the 2-wire return loss across frequency.

200 600

2.16X10

-----------------------------------

( )

(EQ. 33)

TIP onhook

(

)

1.0V

ISH-

(

)

SAToff

----------------------

(EQ. 34)

TIP offhook

(

)

LOOP min

(

)

(

)

SAT off

(

)

--------------------------

(EQ. 35)

LOOP MAX

(

)

RING onhook

(

)

1.5V

ISH

(

)

SAT off

(

)

--------------------------

(EQ. 36)

RING CL

(

)

TIP offhook

(

)

LOOP MAX

(

)

0.2V

(EQ. 37)

RING NCL

(

)

1.5V

LOOP min

(

)

(

)

SAT off

(

)

--------------------------

(EQ. 38)

LOOP MIN

(

)

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

4-19

Digital Logic Inputs

Table 1 is the logic truth table for the 3V to 5V logic input
pins. A combination of the control pins C3, C2 and C1 select
1 of the possible 6 operating states. The 8th state listed is
Thermal Shutdown. Thermal Shutdown protection is invoked
if a fault condition on the tip or ring causes the junction
temperature of the die to exceed 175

C. A description of

each operating state and the control logic follows:

Open Circuit State (C3 = 0, C2 = 0, C1 = 0)

In this state, the tip and ring outputs are in a high impedance
condition (>1M

). No supervisory functions are available

and SHD and GKD outputs are at a TTL high level.

4-wire loopback testing can be performed in this state. With
the PTG pin floating, the signal on the V

output is 180

out

of phase and approximately 2 times the V

input signal. If

the PTG pin is grounded, then the amplitude will be
approximately the same as its input and 180

out of phase.

Ringing State (C3 = 0, C2 = 0, C1 = 1)

In this state, the output of the ring relay driver pin (RRLY)
goes low (energizing the ring relay to connect the ringing
signal to the phone) if either of the following two conditions
are satisfied:

(1) The RSYNC_REV pin is grounded through a resistor -
This connection enables the RRLY pin to go low the instant
the ringing state is invoked, without any regard for the ringing
voltage (90V

RMS

-120V

RMS

) across the relay contacts. The

resistor (34.8k

to 70k

) is required to limit the current into

the RSYNC_REV pin.

(2) A ring sync pulse is applied to the RSYNC_REV pin -
This connection enables the RRLY pin to go low at the
command of a ring sync pulse. A ring sync pulse should go
low at zero voltage crossing of the ring signal. This pulse
should have a rise and fall time <400

s and a minimum

pulse width of 2ms.

Zero ring current detection is performed automatically
inside the SLIC. This feature de-energizes the ring relay
slightly before zero current occurs to partially compensate
for the delay in the opening of the relay.

The SHD output will go low when the subscriber goes off
hook. Once SHD is activated, an internal latch will prohibit
the re-ringing of the line until the ringing code is removed
and then reapplied.

The state prior to ringing the phone, can not be the Reverse
Active State. In the reverse active state the polarity of the
voltage on the CRT_REV_LVM capacitor, will make it appear
as if the subscriber is off hook. This subsequently will
activate an internal latch prohibiting the ringing of the line.

TABLE 1. DETECTOR STATES

STATE

SLIC OPERATING STATE

ACTIVE DETECTOR

OUTPUT

SHD

GKD_ LVM

Open Circuit State

4 wire loopback test capability

HIGH

Ringing State
(Previous State cannot be Reverse
Active State)

Ring Trip Detector

HIGH

Forward Active State

Loop Current Detector

Ground Key Detector

Test Active State
Requires previous state to be in the
Forward Active state to determine the
On hook or Off hook status of the line.

On Hook Loopback Detector

LOW

Ground Key Detector

HIGH

Off Hook Loop Current Detector

LOW

Line Voltage Detector

Tip Open - Ground Start State

Ground Key Detector

Reserved

N/A

Reverse Active State

Loop Current Detector

Ground Key Detector

Test Reversal Active State
Requires previous state to be in the
Reverse Active state to determine the
On hook or Off hook status of the line.

On Hook Loop Current Detector

HIGH

Off Hook Loop Current Detector

LOW

Line Voltage Detector

Thermal Shutdown

LOW

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

4-20

The GKD_LVM output is disabled (TTL high level) during the
ringing state. Reference the Section titled "Ringing the
Phone" for more information.

Forward Active State (C3 = 0, C2 = 1, C1 = 0)

In this state, the SLIC is fully functional. The tip voltage is more
positive than the ring voltage. The tip and ring output voltages
are an unbalanced DC feed, reference Figure 13. Both SHD
and GKD supervisory functions are active. Reference the
section titled "DC Feed Curve" for more information.

Test Active State (C3 = 0, C2 = 1, C1 = 1)

Proper operation of the Test Active State requires the
previous state be the Forward Active state to determine the
on hook or off hook status of the line. In this state, the SLIC
can perform two different tests.

If the subscriber is on hook when the state is entered, a
loopback test is performed by switching an internal 600

resistor between tip and ring. The current flows through the
internal 600

is unidirectional via blocking diodes. (Cannot be

used in reverse.) When the loopback current flows, the SHD
output will go low and remain there until the state is exited. This
is intended to be a short test since the ability to detect
subscriber off hook is lost during loopback testing. Reference
the section titled "Loopback Tests" for more information.

If the subscriber is off hook when the state is entered, a Line
Voltage Measurement test is performed. The output of the
GKD_LVM pin is a pulse train. The pulse width of the active low
portion of the signal is proportional to the voltage across the tip
and ring pins. If the loop length is such that the SLIC is
operating in constant current, the tip to ring voltage can be used
to determine the length of the line under test. The longer the
line, the larger the tip to ring voltage and the wider the pulse.
This relationship can determine the length of the line for setting
gains in the system. Reference the section titled "Operation of
Line Voltage Measurement" for more information.

Tip Open State (C3 = 1, C2 = 0, C1 = 0)

In this state, the tip output is in a high impedance state
(>250k

)

and the ring output is capable of full operation, i.e.

has full longitudinal current capability. The Tip Open/Ground
Start state is used to interface to a PBX incoming 2-wire
trunk line. When a ground is applied through a resistor to the
ring lead, this current is detected and presented as a TTL
logic low on the SHD and GKD_LVM output pins.

Reserved (C3 = 1, C2 = 0, C1 = 1)

This state is undefined and reserved for future use.

Reverse Active State (C3 = 1, C2 = 1, C1 = 0)

In this state, the SLIC is fully functional. The ring voltage is
more positive than the tip voltage. The tip and ring output
voltages are an unbalanced DC feed, reference Figure 13.
The polarity reversal time is determined by the RC time
constant of the RSYNC_REV resistor and the
CRT_REV_LVM capacitor. Capacitor CRT_REV_LVM

performs three different functions: Ring trip filtering, polarity
reversal time and line voltage measurement. It is
recommended that programming of the reversal time be
accomplished by changing the value of RSYNC_REV resistor
(see Figure 18). The value of RSYNC_REV resistor is limited
between 34.8K (10ms) and 73.2k (21ms). Equation 39 gives
the formula for programming the reversal time.

Both SHD and GKD supervisory functions are active.
Reference the section titled "Polarity Reversal" for more
information.

Test Reversal Active State (C3 = 1, C2 = 1, C1 = 1)

Proper operation of the Test Reversal Active State requires
the previous state be the Reverse Active state to determine
the on hook or off hook status of the line.

If the subscriber is on hook when the state is entered, the
SLIC's tip and ring voltages are the same as the Reverse
Active state. The SHD output will go low when the subscriber
goes off hook and the GKD_LVM output is disabled (TTL
level high). (Note: operation is the same as the Reverse
Active state with the GKD_LVM output disabled.)

If the subscriber is off hook when the state is entered, a
Line Voltage Measurement test is performed.

The output of the GKD_LVM pin is a pulse train. The pulse width
of the active low portion of the signal is proportional to the voltage
across the tip and ring pins. If the loop length is such that the
SLIC is operating in constant current mode, the tip to ring voltage
can be used to determine the length of the line under test. The
longer the line, the larger the tip to ring voltage and the wider the
pulse. This relationship can determine the length of the line for
setting gains in the system. Reference the section titled
"Operation of Line Voltage Measurement" for more information.

Thermal Shutdown

The UniSLIC14's thermal shutdown protection is invoked if a
fault condition causes the junction temperature of the die to
exceed about 175

C. Once the thermal limit is exceeded,

both detector outputs go low (SHD and GKD_LVM) and one
of two things can happen.

For marginal faults where loop current is flowing during the
time of the over-temperature condition, foldback loop current
limiting reduces the loop current by reducing the tip to ring
voltage. An equilibrium condition will exist that maintains the
junction temperature at about 175

C until the fault condition

is removed.

For short circuit faults (tip or ring to ground, or to a supply,
etc.) that result in an over-temperature condition, the
foldback current limiting will try to maintain an equilibrium at
about 175

C. If the junction temperature keeps rising, the

device will thermally shutdown and disconnect tip and ring
until the junction temperature falls to approximately 150

RSYNC

REV

3.47k

ReversalTime ms

(

)

(EQ. 39)

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

4-21

Supervisory Functions

Switch Hook Detect Threshold

The Switch Hook Detect Threshold is programmed with a
single external resistor (R

). The output of the SHD pin goes

low when an off hook condition is detected.

Ground Key Detect Threshold

The Ground Key Detect Threshold is set internally and is not
user programmable.

Ringing the Phone

The UniSLIC14 family handles all the popular ringing
formats with high or low side ring trip detection. High side
detection is possible because of the high common mode
range on the ring signal detect input pins (DT, DR). To
minimize power drain from the ring generator, when the
phone is not being rung, the sense resistors are typically
2M

. This reduces the current draw from the ring generator

to just a few microamps.

When the subscriber goes off hook during ringing, the
UniSLIC14 family automatically releases the ring relay and
DC feed is applied to the loop. The UniSLIC14 family has
very low power dissipation in the on hook active mode. This
enables the SLIC (during the ring cadence) to be powered
up in the active state, avoiding unnecessary powering up
and down of the SLIC. The control logic is designed to
facilitate easy implementation of the ring cadence, requiring
only one bit change to go from active to ringing and back
again.

DT, DR AND RRLY INPUTS

Ring trip detection will occur when the DR pin goes more
positive than DT by approximately 4V.

The ring relay driver pin, RRLY, has an internal clamp
between it's output and ground. This eliminates the need to
place an external snubber diode across the ring relay.

Reducing Impulse Noise During Ringing

With an increase in digital data lines being installed next to
analog lines, the threat from impulse noise on analog lines is
increasing. Impulse noise can cause large blocks of high
speed data to be lost, defeating most error correcting
techniques. The UniSLIC14 family has the capability to
reduce impulse noise by closing the ring relay at zero
voltage and opening the ring relay at zero current.

CLOSING THE RING RELAY AT ZERO VOLTAGE

Closing the ring relay at zero voltage is accomplished by
providing a ring sync pulse to the RSYNC_REV pin. The ring
sync pulse is synchronized to go low at the zero voltage
crossing of the ring signal. The resistor R1 in Figure 18 limits
the current into the RSYNC_REV pin. If a particular polarity
reversal time is required, then make R1 equal to the
calculated value in Equation 39. If a specific polarity reversal
time is not desired, R1 equal to 50k

is suggested.

The RSYNC_REV pin is designed to allow the ring sync
pulse to be present at all times. There is no need to gate the
ring sync pulse on and off. The logic control for the
RSYNC_REV pin cannot be an open collector. It must be
high (push-pull logic output stage / pull up resistor to VCC),
low or being clocked by the ring sync pulse. When the
RSYNC_REV pin is high the ring relay pin is disabled. When
the RSYNC_REV pin is low the ring relay pin is activated the
instant the logic code for ringing is applied.

OPENING THE RING RELAY AT ZERO CURRENT

The ring relay is automatically opened at zero current by the
SLIC. The SLIC logic requires zero ringing current in the
loop and either a valid switch hook detect (SHD) or a change
in the operating mode (cadence of the ringing signal) to
release the ring relay.

If the subscriber goes off hook during ringing, the SHD
output will go low. An internal latch will sense SHD is low and
disable the ring relay at zero ringing current. This prevents
the ring signal from being reapplied to the line. To ring the
line again, the SLIC must toggle between logic states. (Note:
The previous state can not be the Reverse Active State. In
the reverse state, the voltage on the CRT_REV_LVM
capacitor will activate an internal latch prohibiting the ringing
of the line.

Figure 19 shows the sequence of events from ringing the
phone to ring trip. The ring relay turns on when both the
ringing code and ring sync pulse are present (A). SHD is
high at this point. When the subscriber goes off hook the
SHD pin goes low and stays low until the ringing control
code is removed (B). This prevents the SHD output from
pulsing after ring trip occurs. At the next zero current
crossing of the ring signal, ring trip occurs and the ring relay
releases the line to allow loop current to flow in the loop (C).

FIGURE 18. REDUCING IMPULSE NOISE USING THE

RSYNC_REV PIN AND SETTING THE POLARITY
REVERSAL TIME

RSYNC_REV

INPUT FOR THE
RING SYNC PULSE

UniSLIC14

50k

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

4-22

Operation of Line Voltage Measurement

A few of the SLICs in the UniSLIC14 family feature Line
Voltage Measurement (LVM) capability. This feature provides
a pulse on the GKD_LVM output pin that is proportional to
the loop voltage. Knowing the loop voltage and thus the loop
length, other basic cable characteristics such as attenuation
and capacitance can be inferred. Decisions can be made
about gain switching in the CODEC to overcome line losses
and verification of the 2-wire circuit integrity.

The LVM function can only be activated in the off hook
condition in either the forward or reverse operating states.
The LVM uses the ring signal supplied to the SLIC as a
timebase generator. The loop resistance is determined by
monitoring the pulse width of the output signal on the
GKD_LVM pin. The output signal on the GKD_LVM pin is a
square wave for which the average duration of the low state
is proportional to the average voltage between the tip and
ring terminals. The loop resistance is determined by the tip
to ring voltage and the constant loop current. Reference
Figure 20.

Although the logic state changes to the Test Active State
when performing this test, the SLIC is still powered up in the
active state (forward or reverse) and the subscriber is
unaware the measurement is being taken.

Polarity Reversal

Most of the SLICs in the UniSLIC14 family feature full
polarity reversal. Full polarity reversal means that the SLIC
can: transmit, determine the status of the line (on hook and
off hook) and provide "silent" polarity reversal. The value of
RSYNC_REV resistor is limited between 34.8k (10ms) and
73.2k (21ms). Reference Equation 39 to program the polarity
reversal time.

Transhybrid Balance

If a low cost CODEC is chosen that does not have a transmit
op-amp, the UniSLIC14 family of SLICs can solve this
problem without the need for an additional op-amp. The
solution is to use the Programmable Transmit Gain pin (PTG)
as an input for the receive signal (V

). When the PTG pin is

connected to a divider network (R1 and R2 Figure 21) and the
value of R1 and R2 is much less than the internal 500k

resistors, two things happen. First the transmit gain from V

to V

is reduced by half. This is the result of shorting out the

bottom 500k

resistor with the much smaller external resistor.

And second, the input signal from V

is also decreased in

half by resistors R1 and R2. Transhybrid balance occurs when
these two, equal but opposite in phase, signals are cancelled
at the input to the output buffer.

Loopback Tests

4-Wire Loopback Test

This feature can be very useful in the testing of line cards
during the manufacturing process and in field use. The test
is unobtrusive, allowing it to be used in live systems.
Reference Figure 22.

Most systems do not provide 4-wire loopback test
capability because of costly relays needed to switch in
external loads. All the SLICs in the UniSLIC14 family can
easily provide this function when configured in the Open
Circuit logic state. With the PTG pin floating, the signal on
the V

output is 180

out of phase and approximately 2

times the V

input signal. If the PTG pin is grounded, then

the amplitude will be approximately the same as the input
signal and 180

out of phase.

FIGURE 19. RINGING SEQUENCE

OFF

RELAY DRIVER

RINGING CURRENT

IN LINE

SHD OUTPUT

RINGING CODE

APPLIED

RING SYNC

PULSE

RINGING VOLTAGE

(A)

(B)

(C)

FIGURE 20. OPERATION OF THE LINE VOLTAGE

MEASUREMENT CIRCUIT

TIP

RING

GEN

GKD_LVM

RING

GEN

FREQ

PULSE WIDTH
PROPORTIONAL TO
LOOP LENGTH

PULSE

LOOP LENGTH

WIDTH

UniSLIC14

FIGURE 21. TRANSHYBRID BALANCE USING THE PTG PIN

500K

PTG

A = 1

500K

UniSLIC14

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

4-23

2-Wire Loopback Test

Most of the SLICs in the UniSLIC14 family feature 2-Wire
loopback testing. This loopback function is only activated
when the subscriber is on hook and the logic command to
the SLIC is in the Test Active State. (Note: if the subscriber is
off hook and in the Test Active State, the function performed
is the Line Voltage Measurement.)

During the 2-wire loopback test, a 2k

internal resistor is

switched across the tip and ring terminals of the SLIC. This
allows the SHD function and the 4-wire to 4-wire AC
transmission, right up to the subscriber loop, to be tested.
Together with the 4-wire loopback test in the Open Circuit
logic state, this 2-wire loopback test allows the complete
network (including SLIC) to be tested up to the subscriber
loop.

Pulse Metering

The HC55121, HC55142 and the HC55150 are designed to
support pulse metering. They offer solutions to the following
pulse metering design issues:

1) Providing adequate signal gain and current drive to the
subscriber metering equipment to overcome the attenuation
of this (12kHz, 16kHz) out of band signal.

2) Attenuating the pulse metering transhybrid signal without
severely attenuating the voice band signal to avoid clipping
in the CODEC/Filter.

3) Tailoring the overload levels in the SLIC to avoid clipping
of the combined voiceband and pulse metering signal.

4) Having the provision of silent polarity reversal as a backup
in the case where the loop attenuates the out of band signal
too much for it to be detected by the subscriber's metering
equipment.

Adequate Signal Gain

Adequate signal gain and current drive to the subscriber's
metering equipment is made easier by the network shown in
Figure 23. The pulse metering signal is supplied to a
dedicated high impedance input pin called SPM. The circuit
in Figure 23 shows the connection of a network that sets the
2-wire impedance (Z

), at the pulse metering frequencies,

to be approximately 200

. If the line impedance (Z

) is equal

to 200

at the pulse metering frequencies, then the 4-Wire

to 2-wire gain (V

/ SPM) is equal 4. Thereby lowering the

input signal requirements of the pulse metering signal.

Note: The automatic pulse metering 2-wire impedance
matching is independent of the programmed 2-wire
impedance matching at voiceband frequencies.

Calculation of the pulse metering gain is achieved by
replacing V

/500k in Equation 15 with SPM/125k and

following the same process through to Equation 21. The
UniSLIC14 sets the 2-wire input impedance of the SLIC
(Z

), including the protection resistors, equal to 200

. The

results are shown in Equation 40.

Avoiding Clipping in the CODEC/Filter

The amplitude of the returning pulse metering signal is often
very large and could easily over drive the input to the
CODEC/Filter. By using the same method discussed in
section "Transhybrid Balance", most if not all of the pulse
metering signal can be canceled out before it reaches the
input to the CODEC/Filter. This connection is shown in
Figure 23.

Overload Levels and Silent Polarity Reversal

The pulse metering signal and voice are simultaneously
transmitted, and therefore require additional overhead to
prevent distortion of the signal. Reference section "Off hook
Overhead Voltage" to account for the additional pulse
metering signal requirements.

Most of the SLICs in the UniSLIC14 family feature full
polarity reversal. Full polarity reversal means that the SLIC
can: transmit, determine the status of the line (on hook and
off hook) and provide "silent" polarity reversal. Reference
Equation 39 to program the polarity reversal time.

FIGURE 22. 4-WIRE AND 2-WIRE LOOPBACK TESTS

TIP

RING

4-WIRE LOOPBACK

UniSLIC14

600

DUAL SUPPLY

CODEC/FILTER

INTERNAL

2-WIRE LOOPBACK

PTG

4-2

SPM

-------------

= 8

+ Z

-------------------------

200

200 + 200

---------------------------

(EQ. 40)

FIGURE 23. PULSE METERING WITH TRANSHYBRID

BALANCE

= 0

500K

PTG

A = 1

500K

UniSLIC14

1/80K

125K

SPM

12/16kHz
PULSE METERING
INPUT SIGNAL

SETS 2-WIRE

IMPEDANCE

AT 12-16kHz

EQUAL TO

200

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

4-24

Interface to Dual and Single Supply
CODECs

Great care has been taken to minimize the number of external
components required with the UniSLIC14 family while still
providing the maximum flexibility. Figures 24A, 24B) shows
the connection of the UniSLIC14 to both a dual supply
CODEC/Filter and a single supply DSP CODEC/Filter.

To eliminate the DC blocking capacitors between the SLIC
and the CODEC/Filter when using a dual supply
CODEC/Filter, both the receive and transmit leads of the
SLIC are referenced to ground. This leads to a very simple
SLIC to CODEC/Filter interface, as shown in Figure 24A.

When using a single supply DSP CODEC/Filter the output
and input of the CODEC/Filter are no longer referenced to
ground. To achieve maximum voltage swing with a single
supply, both the output and input of the CODEC/Filter are
referenced to its own V

/2 reference. Thus, DC blocking

capacitors are once again required. By using the PTG pin of
the UniSLIC14 and the externally supplied V

/2 reference

of the CODEC/Filter, one of the DC blocking capacitors can
be eliminated (Figure 24B).

Power Management

The UniSLIC14 family provides two distinct power
management capabilities:

Power Sharing and Battery Selection

Power Sharing

Power sharing is a method of redistributing the power away
from the SLIC in short loop applications. The total system
power is the same, but the die temperature of the SLIC is
much lower. Power sharing becomes important if the
application has a single battery supply (-48V on hook
requirements for faxes and modems) and the possibility of
high loop currents (reference Figure 25). This technique
would prevent the SLIC from getting too hot and thermally
shutting down on short loops.

The power dissipation in the SLIC is the sum of the smaller
quiescent supply power and the much larger power that
results from the loop current. The power that results from the
loop current is the loop current times the voltage across the
SLIC. The power sharing resistor (R

) reduces the voltage

across the SLIC, and thereby the on-chip power dissipation.
The voltage across the SLIC is reduced by the voltage drop
across R

. This occurs because R

is in series with the

loop current and the negative supply.

A mathematical verification follows:

Given: V

= V

= -48V, Loop current = 30mA, R

(load

across tip and ring) = 600

, Quiescent battery power =

(48V) (0.8mA) = 38.4mW, Quiescent VCC power = (5V)
(2.7mA) = 13.5mW, Power sharing resistor = 600

1. Without power sharing, the on-chip power dissipation

would be 952mW (Equation 41).

2. With power sharing, the on-chip power dissipation is

412mW (Equation 42). A power redistribution of 540mW.

On-chip power dissipation without power sharing resistor.

On-chip power dissipation with 600

power sharing resistor.

The design trade-off in using the power sharing resistor is
loop length vs on-chip power dissipation.

FIGURE 24A.

FIGURE 24B.

FIGURE 24. INTERFACE TO DUAL AND SINGLE SUPPLY

CODECs

A = 1

UniSLIC14

OUT

DUAL SUPPLY

CODEC/FILTER

GND

-5V

500K

PTG

A = 1

500K

UniSLIC14

SINGLE SUPPLY

CODEC/FILTER

GND

DSP

OUT

REF

(

)

30mA

(

)

38.4mW

13.5mW

(

)

30mA

(

)

(EQ. 41)

952mW

(

)

30mA

(

)

38.4mW

13.5mW

(EQ. 42)

(

)

30mA

(

)

(

)

30mA

(

)

412mW

FIGURE 25. POWER SHARING (SINGLE SUPPLY SYSTEMS)

UniSLIC14

TIP

RING

-48V

ON SHORT LOOPS, THE
MAJORITY OF CURRENT
FLOWS OUT THE V

PIN

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

4-25

Battery Selection

Battery selection is a technique, for a two battery supply
system, where the SLIC automatically diverts the loop
current to the most appropriate supply for a given loop
length. This results in significant power savings and lowers
the total power consumption on short loops. This technique
is particularly useful if most of the lines are short, and the on
hook condition requires a -48V battery. In Figure 26, it can
be seen that for long loops the majority of the current comes
from the high battery supply (V

) and for short loops from

the low battery supply (V

FIGURE 26. BATTERY SELECTION (DUAL SUPPLY SYSTEMS)

LOOP CURRENT (mA)

1000

900

800

600

700

575

550

525

500

475

450

400

350

300

250

200

150

2000

LOOP RESISTANCE (

)

100

VBH = -48V
VBL = -24V
RILim = 33.2k

Pinouts - 28 Lead PLCC Packages

HC55120

(28 LEAD PLCC)

TOP VIEW

HC55121

(28 LEAD PLCC)

TOP VIEW

HC55130

(28 LEAD PLCC)

TOP VIEW

HC55140

(28 LEAD PLCC)

TOP VIEW

SHD

CDC

RRL

PTG

VTX

VRX

RSYNC

ILIM

ROH

AGND

GKD

BGND

TIP

VBH

VBL

RING

CRT

RDC_RAC

SHD

CDC

RRL

PTG

VTX

SPM

VRX

RSYNC_REV

ILIM

ROH

AGND

GKD

BGND

TIP

VBH

VBL

RING

CRT_REV

RDC_RAC

SHD

CDC

RRL

PTG

VTX

VRX

RSYNC

ILIM

ROH

AGND

BGND

TIP

VBH

VBL

RING

CRT

RDC_RAC

SHD

CDC

RRL

PTG

VTX

VRX

RSYNC_REV

ILIM

ROH

AGND

GKD_LVM

BGND

TIP

VBH

VBL

RING

CRT_REV_

RDC_RAC

LVM

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

4-26

HC55142

(28 LEAD PLCC)

TOP VIEW

HC55150

(28 LEAD PLCC)

TOP VIEW

Pinouts - 32 Lead PLCC Packages

HC55120

(32 LEAD PLCC)

TOP VIEW

HC55121

(32 LEAD PLCC)

TOP VIEW

Pinouts - 28 Lead PLCC Packages

(Continued)

SHD

CDC

RRL

PTG

VTX

SPM

VRX

RSYNC_REV

ILIM

ROH

AGND

GKD_LVM

BGND

TIP

VBH

VBL

RING

CRT_REV_

RDC_RAC

LVM

SHD

CDC

RRL

PTG

VTX

SPM

VRX

RSYNC_REV

ILIM

ROH

AGND

LVM

BGND

TIP

VBH

VBL

RING

CRT_REV_

RDC_RAC

LVM

SHD

CDC

RRL

PTG

VTX

VRX

RSYNC

ILIM

ROH

AGND

GKD

BGND

TIP

VBH

VBL

RING

CRT

RDC_RAC

TRL

SHD

CDC

RRL

PTG

VTX

VRX

RSYNC_REV

ILIM

ROH

AGND

GKD

BGND

TIP

VBH

VBL

RING

CRT_REV

RDC_RAC

TRL

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

4-27

HC55130

(32 LEAD PLCC)

TOP VIEW

HC55140

(32 LEAD PLCC)

TOP VIEW

HC55142

(32 LEAD PLCC)

TOP VIEW

HC55150

(32 LEAD PLCC)

TOP VIEW

Pinouts - 32 Lead PLCC Packages

SHD

CDC

RRL

PTG

VTX

VRX

RSYNC

ILIM

ROH

AGND

BGND

TIP

VBH

VBL

RING

CRT

RDC_RAC

TRL

SHD

CDC

RRL

PTG

VTX

VRX

RSYNC_REV

ILIM

ROH

AGND

GKD_LVM

BGND

TIP

VBH

VBL

RING

CRT_REV_LVM

RDC_RAC

TRL

SHD

CDC

RRL

PTG

VTX

VRX

RSYNC_REV

ILIM

ROH

AGND

GKD_LVM

BGND

TIP

VBH

VBL

RING

CRT_REV_

RDC_RAC

SPM

TRL

LVM

SHD

CDC

RRL

PTG

VTX

VRX

RSYNC_REV

ILIM

ROH

AGND

LVM

BGND

TIP

VBH

VBL

RING

CRT_REV_

RDC_RAC

SPM

TRL

LVM

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

4-28

Pinouts - 28 Lead SOIC Packages

HC55120

(28 LEAD SOIC)

TOP VIEW

HC55121

(28 LEAD SOIC)

TOP VIEW

HC55130

(28 LEAD SOIC)

TOP VIEW

HC55140

(28 LEAD SOIC)

TOP VIEW

PTG

RRLY

RING

BGND

TIP

VBH

VBL

RDC_RAC

CDC

CRT

AGND

VRX

RSYNC

ILIM

SHD

GKD

VTX

ROH

PTG

RRLY

RING

BGND

TIP

VBH

VBL

RDC_RAC

CDC

CRT_REV

AGND

SPM

VRX

RSYNC_REV

ILIM

SHD

GKD

VTX

ROH

PTG

RRLY

RING

BGND

TIP

VBH

VBL

RDC_RAC

CDC

CRT

AGND

VRX

RSYNC

ILIM

SHD

VTX

ROH

PTG

RRLY

RING

BGND

TIP

VBH

VBL

RDC_RAC

CDC

CRT_REV_LVM

AGND

VRX

RSYNC_REV

ILIM

SHD

GKD_LVM

VTX

ROH

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

4-29

HC55142

(28 LEAD SOIC)

TOP VIEW

HC55150

(28 LEAD SOIC)

TOP VIEW

Pinouts - 28 Lead SOIC Packages

(Continued)

PTG

RRLY

RING

BGND

TIP

VBH

VBL

RDC_RAC

CDC

CRT_REV_LVM

AGND

SPM

VRX

RSYNC_REV

ILIM

SHD

GKD_LVM

VTX

ROH

PTG

RRLY

RING

BGND

TIP

VBH

VBL

RDC_RAC

CDC

CRT_REV_LVM

AGND

SPM

VRX

RSYNC_REV

ILIM

SHD

LVM

VTX

ROH

Pin Descriptions

PIN

PLCC

PIN

PLCC

PIN

SOIC

SYMBOL

DESCRIPTION

PTG

Programmable Transmit Gain - The 2-wire to 4-wire transmission gain is 0dB if this pin is left floating
and -6.02dB if tied to ground. The -6.02dB gain option is useful in systems where Pulse Metering is
used. See Figure 23.

RRLY

Ring Relay Driver Output - The relay coil may be connected to a maximum of 14V.

AC/DC Separation Capacitor - CH is required to properly process the AC current from the DC loop
current. Recommended value 0.1

2-Wire Impedance Matching Pin - Impedance matching of the 2-wire side is accomplished by placing
an impedance between the ZT pin and ground. See Equation 32.

RING

Connects via protection resistor R

to ring wire of subscriber pair.

BGND

Battery ground.

TIP

Connects via protection resistor R

to tip wire of subscriber pair.

High Battery Supply (negative with respect to GND).

Low Battery Supply (negative with respect to GND, magnitude

RDC_RAC

Resistive Feed/Anti Clipping - Performs anti clipping function on constant current application and sets
the slope of the resistive feed curve for constant voltage applications.

CRT_REV

_LVM

Ring Trip, Soft Polarity Reversal and Line Voltage Measurement - A capacitor when placed between the
CRT_REV_LVM pin and +5V performs 3 mutually exclusive functions. When the SLIC is configured in the
Ringing mode it provides filtering of the ringing signal to prevent false detect. When the SLIC is transitioning
between the Forward Active State and Reverse Active State it provides Soft Polarity Reversal and performs
charge storage in the Line Voltage Measurement State. Recommended value 0.47

CDC

Filter Capacitor- The CDC Capacitor removes the VF signals from the battery feed control loop.

Tip side of Ring Trip Detector - Ring trip detection is accomplished by connecting an external network
to a detector in the SLIC with inputs DT and DR. Ring trip occurs when the voltage on DT is more
negative than the voltage on DR.

Ring Side of Ring Trip Detector - Ring trip detection is accomplished by connecting an external
network to a detector in the SLIC with inputs DT and DR. Ring trip occurs when the voltage on DR is
more positive than the voltage on DT.

Activates Test Relay TRLY2.

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

4-30

Activates Test Relay TRLY1.

TTL Compatible Logic Input. The logic states of C1, C2 and C3 determine the operating states of the
SLIC. Reference Table 1 for details.

SHD

Switch Hook Detect - Active during off hook, ground key and loopback. Reference Table 1 for details.

GKD_LVM

Ground Key Detector and Line Voltage Measurement - Reference Table 1 for details.

5V Supply.

Loop Current Threshold Programming Pin - A resistor between this pin and ground will determine the
trigger level for the loop current detect circuit. See Equation 7.

ROH

Off Hook Overload Setting Resistor - Used to set combined overhead for voice and pulse metering
signals. See Equation 10.

ILIM

Current Limit Programming Pin - A resistor between this pin and ground will determine the constant
current limit of the feed curve. See Equation 11.

RSYNC_REV

Ring Synchronization Input and Reversal Time Setting. A resistor between this pin and GND
determines the polarity reversal time. Synchronization of the closing of the relay at zero voltage is
achieved via a ring sync pulse (5V to 0V) synchronized to the ring signal zero voltage crossing
(Reference Figure 18).

AGND

Analog ground

VRX

Receive Input - Ground referenced 4-wire side.

SPM

Pulse Metering Signal Input. If pulse metering is not used, then this pin should be grounded as close
to the device pin as possible.

VTX

Transmit Output - Ground referenced 4-wire side.

TRLY2

Test Relay Driver 2.

TRLY1

Test Relay Driver 1.

Pin Descriptions

(Continued)

PIN

PLCC

PIN

PLCC

PIN

SOIC

SYMBOL

DESCRIPTION

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

4-31

Basic Application Circuit

Voice Only 28 Lead PLCC Package

TIP

RING

FIGURE 27. UniSLIC14 VOICE ONLY BASIC APPLICATION CIRCUIT

RSYNC_REV

ILIM

ROH

SHD

GKD_LVM

RRLY

BGND

VBH

VBL

RDC_RAC

CDC

CRT_REV_LVM

+5V

+5V OR

RELAY

-24V

-48V

RING

TIP

VBAT

RING

CONTROL LOGIC

CODEC/FILTER

PTG

GENERATOR

+5V

AGND

SPM

+12V

OPTIONAL

PERFORM TRANSHYBRID BALANCE

WHEN USING A NON-DSP CODEC.

NOT REQUIRED FOR

C10

C11

NON-DSP CODEC's.

NOT REQUIRED FOR DSP CODEC.

REQUIRED FOR DSP CODEC's

TABLE 2. BASIC APPLICATION CIRCUIT COMPONENT LIST

COMPONENT

VALUE

TOLERANCE

RATING

U1 - SLIC

UniSLIC14 Family

N/A

U2 - Dual Asymmetrical Transient Voltage Suppressor

TISP1072F3

N/A

RP (Line Feed Resistors)

Matched 1%

2.0W

R1 (RDC_RAC Resistor)

21k

1/16W

R2, R3

1/16W

R4 (RD Resistor)

41.2k

1/16W

R5 (ROH Resistor)

38.3k

1/16W

R6 (RILIM Resistor)

33.2k

1/16W

R7 (RSYNC_REV Resistor)

34.8k

1/16W

R8 (RZT Resistor)

107k

1/16W

R9, R10, R11

20k

1/16W

R12

400

C1 (Supply Decoupling), C2

0.1

20%

10V

C5 (Supply Decoupling)

0.1

20%

50V

C6 (Supply Decoupling)

0.1

20%

100V

C4, C7, C10, C11

0.47

20%

10V

4.7

20%

50V

C8, C9

2200pF

20%

100V

D1, Recommended if the VBL supply is not derived from the VBH Supply

1N4004

Design Parameters: Maximum on hook voltage = 0.775V

RMS

, Maximum Off hook Voice = 3.2V

PEAK

, Switch Hook Threshold = 12mA, Loop

Current Limit = 31mA, Synthesize Device Impedance = 540

(600 - 60), with 30

protection resistors, impedance across Tip and Ring terminals =

600

. Where applicable, these component values apply to the Basic Application Circuits for the HC55120, HC55121, HC55130/1, HC55140/1,

HC55142/3 and HC55150/1. Pins not shown in the Basic Application Circuit are no connect (NC) pins.

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

4-32

Basic Application Circuit

Pulse Metering 28 Lead PLCC Package

FIGURE 28. UniSLIC14 PULSE METERING BASIC APPLICATION CIRCUIT

VRX

RSYNC_REV

ILIM

SHD

GKD_LVM

RRLY

VBH

VBL

RDC_RAC

CDC

CRT_REV_LVM

+5V

RELAY

RING

TIP

BAT

RING

CONTROL LOGIC

CODEC/FILTER

PTG

AGND

SPM

12/16kHz
PULSE METERING
INPUT SIGNAL

GENERATOR

+5V

-24V

-48V

TIP

RING

BGND

+5V OR

+12V

OPTIONAL

C10

C11

PERFORM TRANSHYBRID BALANCE

WHEN USING A NON-DSP CODEC.

NOT REQUIRED FOR
NON-DSP CODEC's.

NOT REQUIRED FOR DSP CODEC.

REQUIRED FOR DSP CODEC's

TABLE 3. BASIC APPLICATION CIRCUIT COMPONENT LIST

COMPONENT

VALUE

TOLERANCE

RATING

U1 - SLIC

UniSLIC14 Family

N/A

U2 - Dual Asymmetrical Transient Voltage Suppressor

TISP1072F3

N/A

RP (Line Feed Resistors)

Matched 1%

2.0W

R1 (RDC_RAC Resistor)

26.1k

1/16W

R2, R3

1/16W

R4 (RD Resistor)

41.2k

1/16W

R5 (ROH Resistor)

38.3k

1/16W

R6 (RILIM Resistor)

33.2k

1/16W

R7 (RSYNC_REV Resistor)

34.8k

1/16W

R8 (RZT Resistor)

107k

1/16W

R9, R10, R11

20k

1/16W

R12

400

C1 (Supply Decoupling), C2

0.1

20%

10V

C5 (Supply Decoupling)

0.1

20%

50V

C6 (Supply Decoupling)

0.1

20%

100V

C4, C7, C10, C11

0.47

20%

10V

4.7

20%

50V

C8, C9

2200pF

20%

100V

D1, Recommended if the VBL supply is not derived from the VBH Supply

1N4004

Design Parameters: Maximum on hook voltage = 0.775V

RMS

, Maximum off hook voice = 1.1V

PEAK

, Maximum simultaneous pulse metering

signal = 2.2V

RMS

, Switch Hook Threshold = 12mA, Loop Current Limit = 31mA, Synthesize Device Impedance = 540

(600 - 60), with 30

protection resistors, impedance across Tip and Ring terminals = 600

. Where applicable, these component values apply to the Basic Application

Circuits for the HC55120, HC55121, HC55130/1, HC55140/1, HC55142/3 and HC55150/1. Pins not shown in the Basic Application Circuit are
no connect (NC) pins.

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

4-33

Basic Application Circuit

Voice Only 28 Lead SOIC Package

FIGURE 29. UniSLIC14 VOICE ONLY BASIC APPLICATION CIRCUIT

RSYNC_REV

ILIM

SHD

GKD_LVM

RRLY

RDC_RAC

CDC

CRT_REV_LVM

+5V

RELAY

RING

TIP

BAT

RING

CONTROL LOGIC

CODEC/FILTER

GENERATOR

+5V

-24V

-48V

AGND

TIP

RING

BGND

SPM

+5V OR

+12V

OPTIONAL

C10

C11

PERFORM TRANSHYBRID BALANCE

WHEN USING A NON-DSP CODEC.

NOT REQUIRED FOR
NON-DSP CODEC's.

NOT REQUIRED FOR DSP CODEC.

REQUIRED FOR DSP CODEC's

TABLE 4. BASIC APPLICATION CIRCUIT COMPONENT LIST

COMPONENT

VALUE

TOLERANCE

RATING

U1 - SLIC

UniSLIC14 Family

N/A

U2 - Dual Asymmetrical Transient Voltage Suppressor

TISP1072F3

N/A

RP (Line Feed Resistors)

Matched 1%

2.0W

R1 (RDC_RAC Resistor)

21k

1/16W

R2, R3

1/16W

R4 (RD Resistor)

41.2k

1/16W

R5 (ROH Resistor)

38.3k

1/16W

R6 (RILIM Resistor)

33.2k

1/16W

R7 (RSYNC_REV Resistor)

34.8k

1/16W

R8 (RZT Resistor)

107k

1/16W

R9, R10, R11

20k

1/16W

R12

400

C1 (Supply Decoupling), C2

0.1

20%

10V

C5 (Supply Decoupling)

0.1

20%

50V

C6 (Supply Decoupling)

0.1

20%

100V

C4, C7, C10, C11

0.47

20%

10V

4.7

20%

50V

C8, C9

2200pF

20%

100V

D1, Recommended if the VBL supply is not derived from the VBH Supply

1N4004

Design Parameters: Maximum on hook voltage = 0.775V

RMS

, Maximum Off hook Voice = 3.2V

PEAK

, Switch Hook Threshold = 12mA, Loop

Current Limit = 31mA, Synthesize Device Impedance = 540

(600 - 60), with 30

protection resistors, impedance across Tip and Ring terminals =

600

. Where applicable, these component values apply to the Basic Application Circuits for the HC55120, HC55121, HC55130/1, HC55140/1,

HC55142/3 and HC55150/1. Pins not shown in the Basic Application Circuit are no connect (NC) pins.

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

4-34

Basic Application Circuit

Pulse Metering 28 Lead SOIC Package

FIGURE 30. UniSLIC14 PULSE METERING BASIC APPLICATION CIRCUIT

RSYNC_REV

ILIM

SHD

GKD_LVM

RRLY

RDC_RAC

CDC

CRT_REV_LVM

PTG

AGND

SPM

CONTROL LOGIC

CODEC/FILTER

12/16KHz
PULSE METERING
INPUT SIGNAL

+5V

RELAY

RING

TIP

VBAT

RING

GENERATOR

+5V

-24V

-48V

TIP

RING

BGND

+5V OR

+12V

OPTIONAL

C10

C11

PERFORM TRANSHYBRID BALANCE

WHEN USING A NON-DSP CODEC.

NOT REQUIRED FOR
NON-DSP CODEC's.

NOT REQUIRED FOR DSP CODEC.

REQUIRED FOR DSP CODEC's

TABLE 5. BASIC APPLICATION CIRCUIT COMPONENT LIST

COMPONENT

VALUE

TOLERANCE

RATING

U1 - SLIC

UniSLIC14 Family

N/A

U2 - Dual Asymmetrical Transient Voltage Suppressor

TISP1072F3

N/A

RP (Line Feed Resistors)

Matched 1%

2.0W

R1 (RDC_RAC Resistor)

26.1k

1/16W

R2, R3

1/16W

R4 (RD Resistor)

41.2k

1/16W

R5 (ROH Resistor)

38.3k

1/16W

R6 (RILIM Resistor)

33.2k

1/16W

R7 (RSYNC_REV Resistor)

34.8k

1/16W

R8 (RZT Resistor)

107k

1/16W

R9, R10, R11

20k

1/16W

R12

400

C1 (Supply Decoupling), C2

0.1

20%

10V

C5 (Supply Decoupling)

0.1

20%

50V

C6 (Supply Decoupling)

0.1

20%

100V

C4, C7, C10, C11

0.47

20%

10V

4.7

20%

50V

C8, C9

2200pF

20%

100V

D1, Recommended if the VBL supply is not derived from the VBH Supply

1N4004

Design Parameters: Maximum on hook voltage = 0.775V

RMS

, Maximum off hook voice = 1.1V

PEAK

, Maximum simultaneous pulse metering signal

= 2.2V

RMS

, Switch Hook Threshold = 12mA, Loop Current Limit = 31mA, Synthesize Device Impedance = 540

(600 - 60), with 30

protection

resistors, impedance across Tip and Ring terminals = 600

. Where applicable, these component values apply to the Basic Application Circuits for

the HC55120, HC55121, HC55130/1, HC55140/1, HC55142/3 and HC55150/1. Pins not shown in the Basic Application Circuit are no connect (NC)
pins.

HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

4-35

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

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HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HC55131IM

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HC55131IM