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Электронный компонент: HC5515CM

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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright Intersil Corporation 1999
HC5515
ITU CO/PABX SLIC with Low Power
Standby
The HC5515 is a subscriber line interface circuit which is
interchangeable with Ericsson's PBL3860 for distributed
central office applications. Enhancements include immunity
to circuit latch-up during hot plug and absence of false
signaling in the presence of longitudinal currents.
The HC5515 is fabricated in a High Voltage Dielectrically
Isolated (DI) Bipolar Process that eliminates leakage
currents and device latch-up problems normally associated
with junction isolated ICs. The elimination of the leakage
currents results in improved circuit performance for wide
temperature extremes. The latch free benefit of the DI
process guarantees operation under adverse transient
conditions. This process feature makes the HC5515 ideally
suited for use in harsh outdoor environments.
Features
DI Monolithic High Voltage Process
Programmable Current Feed (20mA to 60mA)
Programmable Loop Current Detector Threshold and
Battery Feed Characteristics
Ring Trip Detection
Compatible with Ericsson's PBL3860
Thermal Shutdown
On-Hook Transmission
Wide Battery Voltage Range (-24V to -58V)
Low Standby Power
-40
o
C to 85
o
C Ambient Temperature Range
Applications
Digital Loop Carrier Systems
Pair Gain
Fiber-In-The-Loop ONUs
POTS
Wireless Local Loop
PABX
Hybrid Fiber Coax
Related Literature
- AN9632, Operation of the HC5523/15 Evaluation Board
Block Diagram
Ordering Information
PART NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG.
NO.
HC5515CM
0 to 70
28 Ld PLCC
N28.45
HC5515CP
0 to 70
22 Ld PDIP
E22.4
HC5515IM
-40 to 85
28 Ld PLCC
N28.45
HC5515IP
-40 to 85
22 Ld PDIP
E22.4
RINGRLY
DT
DR
TIP
RING
HPT
HPR
V
BAT
V
CC
V
EE
AGND
BGND
V
TX
RSN
E0
C1
C2
DET
RING RELAY
DRIVER
4-WIRE
INTERFACE
VF SIGNAL
PATH
LOOP CURRENT
DETECTOR
R
DC
RSG
BIAS
DIGITAL
MULTIPLEXER
RING TRIP
DETECTOR
2-WIRE
INTERFACE
R
D
Data Sheet
October 1998
File Number
4235.4
56
Absolute Maximum Ratings
Thermal Information
Temperature, Humidity
Storage Temperature Range . . . . . . . . . . . . . . . . -65
o
C to 150
o
C
Operating Temperature Range . . . . . . . . . . . . . . . -40
o
C to 110
o
C
Operating Junction Temperature Range. . . . . . . . -40
o
C to 150
o
C
Power Supply (-40
o
C
T
A
85
o
C)
Supply Voltage V
CC
to GND . . . . . . . . . . . . . . . . . . . . 0.5V to 7V
Supply Voltage V
EE
to GND. . . . . . . . . . . . . . . . . . . . . -7V to 0.5V
Supply Voltage V
BAT
to GND . . . . . . . . . . . . . . . . . . . -80V to 0.5V
Ground
Voltage between AGND and BGND . . . . . . . . . . . . . -0.3V to 0.3V
Relay Driver
Ring Relay Supply Voltage . . . . . . . . . . . . . . . . 0V to V
BAT
+75V
Ring Relay Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Ring Trip Comparator
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
BAT
to 0V
Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5mA to 5mA
Digital Inputs, Outputs (C1, C2, E0, DET)
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to V
CC
Output Voltage (DET Not Active) . . . . . . . . . . . . . . . . . .0V to V
CC
Output Current (DET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Tipx and Ringx Terminals (-40
o
C
T
A
85
o
C)
Tipx or Ringx Voltage, Continuous (Referenced to GND)V
BAT
to +2V
Tipx or Ringx, Pulse < 10ms, T
REP
> 10s . . . . V
BAT
-20V to +5V
Tipx or Ringx, Pulse < 10
s, T
REP
> 10s . . . V
BAT
-40V to +10V
Tipx or Ringx, Pulse < 250ns, T
REP
> 10s. . . V
BAT
-70V to +15V
Tipx or Ringx Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70mA
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500V
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
22 Lead PDIP Package . . . . . . . . . . . . . . . . . . . . . .
53
28 Lead PLCC Package . . . . . . . . . . . . . . . . . . . . . .
53
Continuous Power Dissipation at 70
o
C
22 Lead PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5W
28 Lead PLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5W
Package Power Dissipation at 70
o
C, t < 100ms, t
REP
> 1s
22 Lead PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4W
28 Lead PLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4W
Derate above . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
o
C
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.8mW/
o
C
PLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.8mW/
o
C
Maximum Junction Temperature Range . . . . . . . . . -40
o
C to 150
o
C
Maximum Storage Temeprature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
(PLCC - Lead Tips Only)
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . .543 Transistors, 51 Diodes
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
Typical Operating Conditions
These represent the conditions under which the part was developed and are suggested as guidelines.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Case Temperature
-40
-
100
o
C
V
CC
with Respect to AGND
-40
o
C to 85
o
C
4.75
-
5.25
V
V
EE
with Respect to AGND
-40
o
C to 85
o
C
-5.25
-
-4.75
V
V
BAT
with Respect to BGND
-40
o
C to 85
o
C
-58
-
-24
V
Electrical Specifications
T
A
= -40
o
C to 85
o
C, V
CC
= +5V
5%, V
EE
= -5V
5%, V
BAT
= -48V, AGND = BGND = 0V, R
DC1
= R
DC2
= 41.2k
,
R
D
= 39k
, R
SG
= 0
, R
F1
= R
F2
= 0
, C
HP
= 10nF, C
DC
= 1.5
F, Z
L
= 600
, Unless Otherwise Specified. All pin
number references in the figures refer to the 28 lead PLCC package.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Overload Level
1% THD, Z
L
= 600
, (Note 2, Figure 1)
3.1
-
-
V
PEAK
Longitudinal Impedance (Tip/Ring)
0 < f < 100Hz (Note 3, Figure 2)
-
20
35
/Wire
FIGURE 1. OVERLOAD LEVEL (TWO-WIRE PORT)
FIGURE 2. LONGITUDINAL IMPEDANCE
TIP
27
V
TX
19
RING
28
RSN
16
I
DCMET
R
T
R
RX
E
RX
R
L
V
TRO
600k
300k
600
23mA
E
L
V
T
C
0 < f < 100Hz
V
R
LZ
T
= V
T
/A
T
LZ
R
= V
R
/A
R
1V
RMS
300
300
2.16
F
TIP
27
V
TX
19
RING
28
RSN
16
R
T
R
RX
600k
300k
A
T
A
R
HC5515
57
LONGITUDINAL CURRENT LIMIT (TIP/RING)
Off-Hook (Active)
No False Detections, (Loop Current),
LB > 45dB (Note 4, Figure 3A)
20
-
-
mA
PEAK
/
Wire
On-Hook (Standby), R
L
=
No False Detections (Loop Current) (Note 5,
Figure 3B)
5
-
-
mA
PEAK
/
Wire
FIGURE 3A. OFF-HOOK
FIGURE 3B. ON-HOOK
FIGURE 3. LONGITUDINAL CURRENT LIMIT
OFF-HOOK LONGITUDINAL BALANCE
Longitudinal to Metallic
IEEE 455 - 1985, R
LR
, R
LT
= 368
0.2kHz < f < 4.0kHz (Note 6, Figure 4)
53
70
-
dB
Longitudinal to Metallic
R
LR
, R
LT
= 300
, 0.2kHz < f < 4.0kHz
(Note 6, Figure 4)
53
70
-
dB
Metallic to Longitudinal
FCC Part 68, Para 68.310
0.2kHz < f < 1.0kHz
50
55
-
dB
1.0kHz < f < 4.0kHz (Note 7)
50
55
-
dB
Longitudinal to 4-Wire
0.2kHz < f < 4.0kHz (Note 8, Figure 4)
53
70
-
dB
Metallic to Longitudinal
R
LR
, R
LT
= 300
, 0.2kHz < f < 4.0kHz
(Note 9, Figure 5)
50
55
-
dB
4-Wire to Longitudinal
0.2kHz < f < 4.0kHz (Note 10, Figure 5)
50
55
-
dB
FIGURE 4. LONGITUDINAL TO METALLIC AND
LONGITUDINAL TO 4-WIRE BALANCE
FIGURE 5. METALLIC TO LONGITUDINAL AND 4-WIRE TO
LONGITUDINAL BALANCE
2-Wire Return Loss
C
HP
= 20nF
0.2kHz to 0.5kHz (Note 11, Figure 6)
25
-
-
dB
0.5kHz to 1.0kHz (Note 11, Figure 6)
27
-
-
dB
1.0kHz to 3.4kHz (Note 11, Figure 6)
23
-
-
dB
TIP IDLE VOLTAGE
Active, I
L
= 0
-
-1.5
-
V
Standby, I
L
= 0
-
<0
-
V
RING IDLE VOLTAGE
Active, I
L
= 0
-
-46.5
-
V
Electrical Specifications
T
A
= -40
o
C to 85
o
C, V
CC
= +5V
5%, V
EE
= -5V
5%, V
BAT
= -48V, AGND = BGND = 0V, R
DC1
= R
DC2
= 41.2k
,
R
D
= 39k
, R
SG
= 0
, R
F1
= R
F2
= 0
, C
HP
= 10nF, C
DC
= 1.5
F, Z
L
= 600
, Unless Otherwise Specified. All pin
number references in the figures refer to the 28 lead PLCC package. (Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
R
DC2
41.2k
R
DC1
41.2k
C
DC
1.5
F
E
L
-5V
39k
368
368
C
2.16
F
A
TIP
27
RSN
16
RING
28
R
DC
14
DET
R
D
A
R
DC2
41.2k
R
DC1
41.2k
C
DC
1.5
F
E
L
-5V
39k
368
368
A
TIP
27
RSN
16
RING
28
R
DC
14
DET
R
D
C
2.16
F
C
2.16
F
A
R
T
R
RX
E
L
V
TR
600k
300k
C
R
LT
R
LR
V
TX
2.16
F
TIP
27
V
TX
19
RING
28
RSN
16
R
T
R
RX
E
TR
V
L
600k
300k
C
R
LT
R
LR
E
RX
300
300
2.16
F
TIP
27
V
TX
19
RING
28
RSN
16
HC5515
58
Standby, I
L
= 0
-
>-48
-
V
TIP-RING Open Loop Metallic Voltage, V
TR
V
BAT
= -52V, R
SG
= 0
43
-
47
V
4-WIRE TRANSMIT PORT (V
TX
)
Overload Level
Z
L
> 20k
, 1% THD (Note 12, Figure 7)
3.1
-
-
V
PEAK
Output Offset Voltage
E
G
= 0, Z
L
=
(Note 13, Figure 7)
-60
-
60
mV
Output Impedance (Guaranteed by Design)
0.2kHz < f < 03.4kHz
-
5
20
2-Wire to 4-Wire (Metallic to V
TX
) Voltage Gain
0.3kHz < f < 03.4kHz (Note 14, Figure 7)
0.98
1.0
1.02
V/V
FIGURE 6. TWO-WIRE RETURN LOSS
FIGURE 7. OVERLOAD LEVEL (4-WIRE TRANSMIT PORT),
OUTPUT OFFSET VOLTAGE, 2-WIRE TO 4-WIRE
VOLTAGE GAIN AND HARMONIC DISTORTION
4-WIRE RECEIVE PORT (RSN)
DC Voltage
I
RSN
= 0mA
-
0
-
V
R
X
Sum Node Impedance (Gtd by Design)
0.2kHz < f < 3.4kHz
-
-
20
Current Gain-RSN to Metallic
0.3kHz < f < 3.4kHz (Note 15, Figure 8)
900
1000
1100
Ratio
FREQUENCY RESPONSE (OFF-HOOK)
2-Wire to 4-Wire
0dBm at 1.0kHz, E
RX
= 0V
0.3kHz < f < 3.4kHz (Note 16, Figure 9)
-0.2
-
0.2
dB
4-Wire to 2-Wire
0dBm at 1.0kHz, E
G
= 0V
0.3kHz < f < 3.4kHz (Note 17, Figure 9)
-0.2
-
0.2
dB
4-Wire to 4-Wire
0dBm at 1.0kHz, E
G
= 0V
0.3kHz < f < 3.4kHz (Note 18, Figure 9)
-0.2
-
0.2
dB
INSERTION LOSS
2-Wire to 4-Wire
0dBm, 1kHz (Note 19, Figure 9)
-0.2
-
0.2
dB
4-Wire to 2-Wire
0dBm, 1kHz (Note 20, Figure 9)
-0.2
-
0.2
dB
GAIN TRACKING (Ref = -10dBm, at 1.0kHz)
2-Wire to 4-Wire
+3dBm to +7dBm (Note 21, Figure 9)
-0.15
-
0.15
dB
2-Wire to 4-Wire
-40dBm to +3dBm (Note 21, Figure 9)
-0.1
-
0.1
dB
2-Wire to 4-Wire
-55dBm to -40dBm (Note 21, Figure 9)
-0.2
-
0.2
dB
4-Wire to 2-Wire
-40dBm to +7dBm (Note 22, Figure 9)
-0.1
-
0.1
dB
Electrical Specifications
T
A
= -40
o
C to 85
o
C, V
CC
= +5V
5%, V
EE
= -5V
5%, V
BAT
= -48V, AGND = BGND = 0V, R
DC1
= R
DC2
= 41.2k
,
R
D
= 39k
, R
SG
= 0
, R
F1
= R
F2
= 0
, C
HP
= 10nF, C
DC
= 1.5
F, Z
L
= 600
, Unless Otherwise Specified. All pin
number references in the figures refer to the 28 lead PLCC package. (Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
R
RX
V
S
300k
Z
D
R
LR
R
T
600k
R
R
Z
IN
V
M
TIP
27
V
TX
19
RING
28
RSN
16
R
T
R
RX
I
DCMET
600k
300k
C
E
G
R
L
V
TXO
600
Z
L
V
TR
23mA
2.16
F
V
TX
TIP
27
V
TX
19
RING
28
RSN
16
HC5515
59
4-Wire to 2-Wire
-55dBm to -40dBm (Note 22, Figure 9)
-0.2
-
0.2
dB
FIGURE 8. CURRENT GAIN-RSN TO METALLIC
FIGURE 9. FREQUENCY RESPONSE, INSERTION LOSS,
GAIN TRACKING AND HARMONIC DISTORTION
NOISE
Idle Channel Noise at 2-Wire
C-Message Weighting (Note 23, Figure 10)
-
8.5
-
dBrnC
Psophometrical Weighting
(Note 23, Figure 10)
-
-81.5
-
dBrnp
Idle Channel Noise at 4-Wire
C-Message Weighting (Note 24, Figure 10)
-
8.5
-
dBrnC
Psophometrical Weighting
(Note 23, Figure 10)
-
-81.5
-
dBrnp
HARMONIC DISTORTION
2-Wire to 4-Wire
0dBm, 1kHz (Note 25, Figure 7)
-
-65
-54
dB
4-Wire to 2-Wire
0dBm, 0.3kHz to 3.4kHz (Note 26, Figure 9)
-
-65
-54
dB
BATTERY FEED CHARACTERISTICS
Constant Loop Current Tolerance
R
DCX
= 41.2k
I
L
= 2500/(R
DC1
+ R
DC2
),
-40
o
C to 85
o
C (Note 27)
0.85I
L
I
L
1.15I
L
mA
Loop Current Tolerance (Standby)
I
L
= (V
BAT
-3)/(R
L
+1800),
-40
o
C to 85
o
C (Note 28)
0.75I
L
I
L
1.25I
L
mA
Open Circuit Voltage (V
TIP
- V
RING
)
-40
o
C to 85
o
C, (Active) R
SG
=
14
16.67
20
V
LOOP CURRENT DETECTOR
On-Hook to Off-Hook
R
D
= 33k
,
-40
o
C to 85
o
C
11
465/R
D
17.2
mA
Off-Hook to On-Hook
R
D
= 33k
,
-40
o
C to 85
o
C
9.5
405/R
D
15.0
mA
Loop Current Hysteresis
R
D
= 33k
,
-40
o
C to 85
o
C
-
60/R
D
-
mA
FIGURE 10. IDLE CHANNEL NOISE
Electrical Specifications
T
A
= -40
o
C to 85
o
C, V
CC
= +5V
5%, V
EE
= -5V
5%, V
BAT
= -48V, AGND = BGND = 0V, R
DC1
= R
DC2
= 41.2k
,
R
D
= 39k
, R
SG
= 0
, R
F1
= R
F2
= 0
, C
HP
= 10nF, C
DC
= 1.5
F, Z
L
= 600
, Unless Otherwise Specified. All pin
number references in the figures refer to the 28 lead PLCC package. (Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
R
DC2
41.2k
R
DC1
41.2k
C
DC
1.5
F
R
L
600
TIP
27
RING
28
R
DC
14
RSN
16
R
RX
300k
V
RSN
= 0V
V
RSN
= -3V
GRX = ((V
TR1
- V
TR2
)(300k))/(-3)(600)
Where: V
TR1
is the Tip to Ring Voltage with V
RSN
= 0V
V
TR
and V
TR2
is the Tip to Ring Voltage with V
RSN
= -3V
R
T
R
RX
I
DCMET
600k
300k
C
1/
C < R
L
E
G
R
L
V
TX
600
V
TR
E
RX
TIP
27
V
TX
19
RING
28
RSN
16
R
T
R
RX
600k
300k
600
V
TR
V
TX
R
L
TIP
27
V
TX
19
RING
28
RSN
16
HC5515
60
RING TRIP DETECTOR (DT, DR)
Offset Voltage
Source Res = 0
-20
-
20
mV
Input Bias Current
Source Res = 0
-360
-
360
nA
Input Common-Mode Range
Source Res = 0
V
BAT
+1
-
0
V
Input Resistance
Source Res = 0, Unbalanced
1
-
-
M
Source Res = 0, Balanced
3
-
-
M
RING RELAY DRIVER
V
SAT
at 25mA
I
OL
= 25mA
-
0.2
0.6
V
Off-State Leakage Current
V
OH
= 12V
-
-
10
A
DIGITAL INPUTS (E0, C1, C2)
Input Low Voltage, V
IL
0
-
0.8
V
Input High Voltage, V
IH
2
-
V
CC
V
Input Low Current, I
IL
: C1, C2
V
IL
= 0.4V
-200
-
-
A
Input Low Current, I
IL
: E0
V
IL
= 0.4V
-100
-
-
A
Input High Current
V
IH
= 2.4V
-
-
40
A
DETECTOR OUTPUT (DET)
Output Low Voltage, V
OL
I
OL
= 2mA
-
-
0.45
V
Output High Voltage, V
OH
I
OH
= 100
A
2.7
-
-
V
Internal Pull-Up Resistor
8
15
25
k
POWER DISSIPATION (V
BAT
= -48V)
Open Circuit State
C1 = C2 = 0
-
26.3
70
mW
On-Hook, Standby
C1 = C2 = 1
-
37.5
85
mW
On-Hook, Active
C1 = 0, C2 = 1, R
L
= High Impedance
-
110
300
mW
Off-Hook, Active
C1 = 0, C2 = 1, R
L
= 600
-
1.1
1.4
W
TEMPERATURE GUARD
Thermal Shutdown
150
-
180
o
C
SUPPLY CURRENTS (V
BAT
= -28V)
Open Circuit State (C1, 2 = 0, 0)
On-Hook
I
CC
-
1.3
2.8
mA
I
EE
-
0.6
2.0
mA
I
BAT
-
0.35
1.2
mA
Standby State (C1, 2 = 1, 1)
On-Hook
I
CC
-
1.6
3.5
mA
I
EE
-
0.62
2.0
mA
I
BAT
-
0.55
1.6
mA
Active State (C1, 2 = 0, 1)
On-Hook
I
CC
-
3.7
9.5
mA
I
EE
-
1.1
4.0
mA
I
BAT
-
2.2
5.2
mA
PSRR
V
CC
to 2 or 4-Wire Port
(Note 29, Figure 11)
-
40
-
dB
V
EE
to 2 or 4-Wire Port
(Note 29, Figure 11)
-
40
-
dB
Electrical Specifications
T
A
= -40
o
C to 85
o
C, V
CC
= +5V
5%, V
EE
= -5V
5%, V
BAT
= -48V, AGND = BGND = 0V, R
DC1
= R
DC2
= 41.2k
,
R
D
= 39k
, R
SG
= 0
, R
F1
= R
F2
= 0
, C
HP
= 10nF, C
DC
= 1.5
F, Z
L
= 600
, Unless Otherwise Specified. All pin
number references in the figures refer to the 28 lead PLCC package. (Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
HC5515
61
Circuit Operation and Design Information
The HC5515 is a current feed voltage sense Subscriber Line
Interface Circuit (SLIC). This means that for short loop
applications the SLIC provides a programed constant current to
the tip and ring terminals while sensing the tip to ring voltage.
The following discussion separates the SLIC's operation into
its DC and AC paths, then follows up with additional circuit
and design information.
Constant Loop Current (DC) Path
SLIC in the Active Mode
The DC path establishes a constant loop current that flows
out of tip and into the ring terminal. The loop current is
programmed by resistors R
DC1
, R
DC2
and the voltage on
the R
DC
pin (Figure 12). The R
DC
voltage is determined by
the voltage across R
1
in the saturation guard circuit. Under
constant current feed conditions, the voltage drop across R
1
sets the R
DC
voltage to -2.5V. This occurs when current
flows through R
1
into the current source I
2
. The R
DC
voltage
establishes a current (I
RSN
) that is equal to V
RDC
/(R
DC1
+R
DC2
). This current is then multiplied by 1000, in the loop
current circuit, to become the tip and ring loop currents.
For the purpose of the following discussion, the saturation
guard voltage is defined as the maximum tip to ring voltage
at which the SLIC can provide a constant current for a given
battery and overhead voltage.
For loop resistances that result in a tip to ring voltage less than
the saturation guard voltage the loop current is defined as:
where: I
L
= Constant loop current, and
R
DC1
and R
DC2
= Loop current programming resistors.
Capacitor C
DC
between R
DC1
and R
DC2
removes the VF
signals from the battery feed control loop. The value of C
DC
is determined by Equation 2:
where T = 30ms.
NOTE: The minimum C
DC
value is obtained if R
DC1
= R
DC2
.
Figure 13 illustrates the relationship between the tip to ring
voltage and the loop resistance. For a 0
loop resistance
both tip and ring are at V
BAT
/2. As the loop resistance
increases, so does the voltage differential between tip and
ring. When this differential voltage becomes equal to the
saturation guard voltage, the operation of the SLIC's loop
feed changes from a constant current feed to a resistive
feed. The loop current in the resistive feed region is no
longer constant but varies as a function of the loop
resistance.
V
BAT
to 2 or 4-Wire Port
(Note 29, Figure 11)
-
40
-
dB
FIGURE 11. POWER SUPPLY REJECTION RATIO
Electrical Specifications
T
A
= -40
o
C to 85
o
C, V
CC
= +5V
5%, V
EE
= -5V
5%, V
BAT
= -48V, AGND = BGND = 0V, R
DC1
= R
DC2
= 41.2k
,
R
D
= 39k
, R
SG
= 0
, R
F1
= R
F2
= 0
, C
HP
= 10nF, C
DC
= 1.5
F, Z
L
= 600
, Unless Otherwise Specified. All pin
number references in the figures refer to the 28 lead PLCC package. (Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
R
T
R
RX
600k
300k
R
L
V
TX
600
100mV
RMS
, 50Hz TO 4kHz
-48V SUPPLY
+5V SUPPLY
-5V SUPPLY
PSRR = 20 log (V
T X
/V
IN
)
TIP
27
V
TX
19
RING
28
RSN
16
I
L
2.5V
R
DC1
R
DC2
+
--------------------------------------
1000
=
(EQ. 1)
C
DC
T
1
R
DC1
---------------
1
R
DC2
---------------
+
=
(EQ. 2)
HC5515
62
Figure 14 shows the relationship between the saturation
guard voltage, the loop current and the loop resistance.
Notice from Figure 14 that for a loop resistance <1.2k
(R
SG
= 4.0k
) the SLIC is operating in the constant current
feed region and for resistances >1.2k
the SLIC is operating
in the resistive feed region. Operation in the resistive feed
region allows long loop and off-hook transmission by
keeping the tip and ring voltages off the rails. Operation in
this region is transparent to the customer.
The Saturation Guard circuit (Figure 12) monitors the tip to
ring voltage via the transconductance amplifier A
1
. A
1
generates a current that is proportional to the tip to ring
voltage difference. I
1
is internally set to sink all of A
1
's
current until the tip to ring voltage exceeds 12.5V. When the
tip to ring voltage exceeds 12.5V (with no R
SG
resistor) A
1
supplies more current than I
1
can sink. When this happens
A
2
amplifies its input current by a factor of 12 and the current
through R
1
becomes the difference between I
2
and the
output current from A
2
. As the current from A
2
increases, the
voltage across R
1
decreases and the output voltage on R
DC
decreases. This results in a corresponding decrease in the
loop current. The R
SG
pin provides the ability to increase the
saturation guard reference voltage beyond 12.5V. Equation 3
gives the relationship between the R
SG
resistor value and
the programmable saturation guard reference voltage:
where:
V
SGREF
= Saturation Guard reference voltage, and
R
SG
= Saturation Guard programming resistor.
When the Saturation guard reference voltage is exceeded,
the tip to ring voltage is calculated using Equation 4:
where:
V
TR
= Voltage differential between tip and ring, and
R
L
= Loop resistance.
For on-hook transmission R
L
=
, Equation 4 reduces to:
The value of R
SG
should be calculated to allow maximum
loop length operation. This requires that the saturation guard
reference voltage be set as high as possible without clipping
the incoming or outgoing VF signal. A voltage margin of -4V
HC5515
V
TX
R
RX
R
DC1
R
DC2
C
DC
RSN
R
DC
I
RSN
TIP
RING
-2.5V
I
RING
I
TIP
A
2
I
TIP
I
RING
R
SG
R
SG
-5V
LOOP CURRENT
CIRCUIT
SATURATION GUARD
CIRCUIT
A
1
I
1
I
2
R
1
+
-
+
-
+
-
+
-
FIGURE 12. DC LOOP CURRENT
-5V
-5V
17.3k
0
1.2K
-50
-40
-30
-20
-10
0
V
BAT
= -48V, I
L
= 23mA, R
SG
= 4.0k
LOOP RESISTANCE (
)
V
TIP
V
RING
RESISTIVE FEED
REGION
TIP T
O
RING V
O
L
T
A
GE (V)
CONSTANT CURRENT
FEED REGION
SATURATION
GUARD VOLTAGE
SATURATION
GUARD VOLTAGE
FIGURE 13. V
TR
vs R
L
0
10
20
30
0
10
20
30
40
50
LOOP CURRENT (mA)
TIP TO RING VOLTAGE (V)
V
BAT
= -24V, R
SG
=
V
BAT
= -48V, R
SG
= 4.0k
SATURATION GUARD
RESISTIVE FEED
REGION
CONSTANT CURRENT
FEED REGION
R
SG
= 4.0k
100k
100k
4k
1.5k
2k
700
<400
<1.2k
R
L
R
L
R
SG
=
VOLTAGE, V
TR
= 38V
SATURATION GUARD
VOLTAGE, V
TR
= 13V
FIGURE 14. V
TR
vs I
L
and R
L
V
SGREF
12.5
5
10
5
R
SG
17300
+
-----------------------------------
+
=
(EQ. 3)
V
TR
R
L
16.66
5
10
5
R
SG
17300
+
(
)
/
+
R
L
R
DC1
R
DC2
+
(
)
600
/
+
------------------------------------------------------------------------------------
=
(EQ. 4)
V
TR
16.66
5
10
5
R
SG
17300
+
-----------------------------------
+
=
(EQ. 5)
HC5515
63
on tip and -4V on ring, for a total of -8V margin, is
recommended as a general guideline. The value of R
SG
is
calculated using Equation 6:
where:
V
BAT
= Battery voltage, and
V
MAR
= Voltage Margin. Recommended value of -8V to
allow a maximum overload level of 3.1V
PEAK
.
For on-hook transmission R
L
=
, Equation 6 reduces to:
SLIC in the Standby Mode
Overall system power is saved by configuring the SLIC in the
standby state when not in use. In the standby state the tip
and ring amplifiers are disabled and internal resistors are
connected between tip to ground and ring to V
BAT
. This
connection enables a loop current to flow when the phone
goes off-hook. The loop current detector then detects this
current and the SLIC is configured in the active mode for
voice transmission. The loop current in standby state is
calculated as follows:
where:
I
L
= Loop current in the standby state,
R
L
= Loop resistance, and
V
BAT
= Battery voltage.
(AC) Transmission Path
SLIC in the Active Mode
Figure 15 shows a simplified AC transmission model. Circuit
analysis yields the following design equations:
where:
V
TR
= Is the AC metallic voltage between tip and ring,
including the voltage drop across the fuse resistors R
F
,
V
TX
= Is the AC metallic voltage. Either at the ground
referenced 4-wire side or the SLIC tip and ring terminals,
I
M
= Is the AC metallic current,
R
F
= Is a fuse resistor,
Z
T
= Is used to set the SLIC's 2-wire impedance,
V
RX
= Is the analog ground referenced receive signal,
Z
RX
= Is used to set the 4-wire to 2-wire gain,
E
G
= Is the AC open circuit voltage, and
Z
L
= Is the line impedance.
(AC) 2-Wire Impedance
The AC 2-wire impedance (Z
TR
) is the impedance looking
into the SLIC, including the fuse resistors, and is calculated
as follows:
Let V
RX
= 0. Then from Equation 10:
Z
TR
is defined as:
Substituting in Equation 9 for V
TR
:
Substituting in Equation 12 for V
TX
:
Therefore:
Equation 16 can now be used to match the SLIC's
impedance to any known line impedance (Z
TR
).
Example:
Calculate Z
T
to make Z
TR
= 600
in series with 2.16
F.
R
F
= 20
.
Z
T
= 560k
in series with 2.16nF.
(AC) 2-Wire to 4-Wire Gain
The 2-wire to 4-wire gain is equal to V
TX
/ V
TR
.
From Equations 9 and 10 with V
RX
= 0:
(AC) 4-Wire to 2-Wire Gain
The 4-wire to 2-wire gain is equal to V
TR
/V
RX
.
From Equations 9, 10 and 11 with E
G
= 0:
R
SG
5
10
5
V
BAT
V
MAR
(
)
1
R
DC1
R
DC2
+
(
)
600R
L
----------------------------------------------
+
16.66V
----------------------------------------------------------------------------------------------------------------------------------------------
17300
=
(EQ. 6)
R
SG
5
10
5
V
BAT
V
MAR
16.66V
------------------------------------------------------------------
17300
=
(EQ. 7)
I
L
V
BAT
3V
R
L
1800
+
--------------------------------
(EQ. 8)
V
TR
V
TX
I
M
2R
F
+
=
(EQ. 9)
V
TX
Z
T
-----------
V
RX
Z
RX
-----------
+
I
M
1000
-------------
=
(EQ. 10)
V
TR
E
G
I
M
Z
L
=
(EQ. 11)
V
TX
Z
T
I
M
1000
-------------
=
(EQ. 12)
Z
TR
V
TR
I
M
-----------
=
(EQ. 13)
Z
TR
V
TX
I
M
-----------
2R
F
I
M
I
M
-----------------------
+
=
(EQ. 14)
Z
TR
Z
T
1000
-------------
2R
F
+
=
(EQ. 15)
Z
T
1000
Z
TR
2R
F
(
)
=
(EQ. 16)
Z
T
1000
600
1
j
2.16
10
6
-----------------------------------------
2
20
+
=
A
2
4
V
TX
V
TR
-----------
Z
T
1000
/
Z
T
1000
/
2R
F
+
------------------------------------------
=
=
(EQ. 17)
A
4
2
V
TR
V
RX
-----------
Z
T
Z
RX
-----------
Z
L
Z
T
1000
-------------
2R
F
Z
L
+
+
--------------------------------------------
=
=
(EQ. 18)
HC5515
64
For applications where the 2-wire impedance (Z
TR
,
Equation 15) is chosen to equal the line impedance (Z
L
), the
expression for A
4-2
simplifies to:
(AC) 4-Wire to 4-Wire Gain
The 4-wire to 4-wire gain is equal to V
TX
/V
RX
.
From Equations 9, 10 and 11 with E
G
= 0:
Transhybrid Circuit
The purpose of the transhybrid circuit is to remove the
receive signal (V
RX
) from the transmit signal (V
TX
), thereby
preventing an echo on the transmit side. This is
accomplished by using an external op amp (usually part of
the CODEC) and by the inversion of the signal from the
4-wire receive port (RSN) to the 4-wire transmit port (V
TX
).
Figure 16 shows the transhybrid circuit. The input signal will
be subtracted from the output signal if I
1
equals I
2
. Node
analysis yields the following equation:
The value of Z
B
is then:
Where V
RX
/V
TX
equals 1/ A
4-4
.
Therefore:
Example:
Given: R
TX
= 20k
, Z
RX
= 280k
, Z
T
= 562k
(standard
value), R
F
= 20
and Z = 600
,
The value of Z
B
= 18.7k
Supervisory Functions
The loop current and the ring trip detector outputs are
multiplexed to a single logic output pin called DET. See Table
1 to determine the active detector for a given logic input. For
further discussion of the logic circuitry see section titled
"Digital Logic Inputs".
Before proceeding with an explanation of the loop current
detector and the longitudinal impedance, it is important to
understand the difference between a "metallic" and
"longitudinal" loop currents. Figure 17 illustrates 3 different
types of loop current encountered.
Case 1 illustrates the metallic loop current. The definition of
a metallic loop current is when equal currents flow out of tip
and into ring. Loop current is a metallic current.
V
TX
RSN
TIP
RING
I
M
Z
TR
V
TR
E
G
V
TX
I
M
1000
V
TX
Z
RX
1
HC5515
R
F
R
F
A = 4
+
-
+
-
+
-
+
-
Z
T
+
-
V
RX
+
-
A = 250
A = 250
I
M
Z
L
FIGURE 15. SIMPLIFIED AC TRANSMISSION CIRCUIT
A
4
2
Z
T
Z
RX
-----------
1
2
---
=
(EQ. 19)
A
4
4
V
TX
V
RX
-----------
Z
T
Z
RX
-----------
Z
L
2R
F
+
Z
T
1000
-------------
2R
F
Z
L
+
+
--------------------------------------------
=
=
(EQ. 20)
V
TX
R
TX
-----------
V
RX
Z
B
-----------
+
0
=
(EQ. 21)
Z
B
R
TX
V
RX
V
TX
-----------
=
(EQ. 22)
Z
B
R
TX
Z
RX
Z
T
-----------
Z
T
1000
-------------
2R
F
Z
L
+
+
Z
L
2R
F
+
--------------------------------------------
=
(EQ. 23)
HC5515
V
TX
RSN
R
TX
R
FB
CODEC/
FILTER
I
1
I
2
V
TX
Z
RX
Z
T
+
-
Z
B
V
RX
+
-
+
-
FIGURE 16. TRANSHYBRID CIRCUIT
HC5515
65
Cases 2 and 3 illustrate the longitudinal loop current. The
definition of a longitudinal loop current is a common mode
current, that flows either out of or into tip and ring
simultaneously. Longitudinal currents in the on-hook state
result in equal currents flowing through the sense resistors
R
1
and R
2
(Figure 17). And longitudinal currents in the off-
hook state result in unequal currents flowing through the
sense resistors R
1
and R
2
. Notice that for case 2,
longitudinal currents flowing away from the SLIC, the current
through R
1
is the metallic loop current plus the longitudinal
current; whereas the current through R
2
is the metallic loop
current minus the longitudinal current. Longitudinal currents
are generated when the phone line is influenced by
magnetic fields (e.g. power lines).
Loop Current Detector
Figure 17 shows a simplified schematic of the loop current
detector. The loop current detector works by sensing the
metallic current flowing through resistors R
1
and R
2
. This
results in a current (I
RD
) out of the transconductance
amplifier (gm
1
) that is equal to the product of gm
1
and the
metallic loop current. I
RD
then flows out the R
D
pin and
through resistor R
D
to V
EE
. The value of I
RD
is equal to:
The I
RD
current results in a voltage drop across R
D
that is
compared to an internal 1.25V reference voltage. When the
voltage drop across R
D
exceeds 1.25V, and the logic is
configured for loop current detection, the DET pin goes low.
The hysteresis resistor R
H
adds an additional voltage
effectively across R
D
, causing the on-hook to off-hook
threshold to be slightly higher than the off-hook to on-hook
threshold.
Taking into account the hysteresis voltage, the typical value
of R
D
for the on-hook to off-hook condition is:
Taking into account the hysteresis voltage, the typical value
of R
D
for the off-hook to on-hook condition is:
A filter capacitor (C
D
) in parallel with R
D
will improve the
accuracy of the trip point in a noisy environment. The value
of this capacitor is calculated using the following Equation:
where: T = 0.5ms.
Ring Trip Detector
Ring trip detection is accomplished with the internal ring trip
comparator and the external circuitry shown in Figure 18.
The process of ring trip is initiated when the logic input pins
are in the following states: E0 = 0, C1 = 1 and C2 = 0. This
logic condition connects the ring trip comparator to the DET
output, and causes the Ringrly pin to energize the ring relay.
The ring relay connects the tip and ring of the phone to the
external circuitry in Figure 18. When the phone is on-hook
the DT pin is more positive than the DR pin and the DET
output is high. For off-hook conditions DR is more positive
than DT and DET goes low. When DET goes low, indicating
that the phone has gone off-hook, the SLIC is commanded
by the logic inputs to go into the active state. In the active
state, tip and ring are once again connected to the phone
and normal operation ensues.
Figure 18 illustrates battery backed unbalanced ring injected
ringing. For tip injected ringing just reverse the leads to the
phone. The ringing source could also be balanced.
NOTE: The DET output will toggle at 20Hz because the DT input is
not completely filtered by C
RT
. Software can examine the duty cycle
and determine if the DET pin is low for more that half the time, if so
the off-hook condition is indicated.
I
RD
I
TIP
I
RING
600
------------------------------------
I
L
300
----------
=
=
(EQ. 24)
R
D
465
I
ON
HOOK to OFF
HOOK
--------------------------------------------------------------------------
=
(EQ. 25)
R
D
375
I
OFF
HOOK to ON
HOOK
--------------------------------------------------------------------------
=
(EQ. 26)
C
D
T
R
D
--------
=
(EQ. 27)
HC5515
DET
R
D
R
2
gm
1
gm
1
(I
METALLIC
)
R
D
C
D
V
REF
+
-
CURRENT
LOOP
V
EE
-5V
I
RD
R
H
RING
TIP
+
-
R
1
+
-
CASE 1
CASE 2
CASE 3
I
METAL-
LIC
I
LONGITUDI-
NAL
I
LONGITUDI-
NAL
COMPARATOR
DIGITAL MULTIPLEXER
1.25V
+
-
FIGURE 17. LOOP CURRENT DETECTOR
HC5515
66
Longitudinal Impedance
The feedback loop described in Figure 19(A, B) realizes the
desired longitudinal impedances from tip to ground and from
ring to ground. Nominal longitudinal impedance is resistive
and in the order of 22
.
In the presence of longitudinal currents this circuit
attenuates the voltages that would otherwise appear at the
tip and ring terminals, to levels well within the common mode
range of the SLIC. In fact, longitudinal currents may exceed
the programmed DC loop current without disturbing the
SLIC's VF transmission capabilities.
The function of this circuit is to maintain the tip and ring
voltages symmetrically around V
BAT
/2, in the presence of
longitudinal currents. The differential transconductance
amplifiers G
T
and G
R
accomplish this by sourcing or sinking
the required current to maintain V
C
at V
BAT
/2.
When a longitudinal current is injected onto the tip and ring
inputs, the voltage at VC moves from it's equilibrium value
VBAT/2. When VC changes by the amount DVC, this change
appears between the input terminals of the differential
transconductance amplifiers GT and GR. The output of GT
and GR are the differential currents DI1 and DI2, which in
turn feed the differential inputs of current sources IT and IR
respectively. IT and IR have current gains of 250 single
ended and 500 differentially, thus leading to a change in IT
and IR that is equal to 500(DI) and 500(DI2).
The circuit shown in Figure 19(B) illustrates the tip side of
the longitudinal network. The advantages of a differential
input current source are: improved noise since the noise due
to current source 2I
O
is now correlated, power savings due
to differential current gain and minimized offset error at the
Operational Amplifier inputs via the two 5k
resistors.
Digital Logic Inputs
Table 1 is the logic truth table for the TTL compatible logic
input pins. The HC5515 has an enable input pin (E0) and
two control inputs pins (C1, C2).
The enable pin E0 is used to enable or disable the DET
output pin. The DET pin is enabled if E0 is at a logic level 0
and disabled if E0 is at a logic level 1.
A combination of the control pins C1 and C2 is used to
select 1 of the 4 possible operating states. A description of
each operating state and the control logic follow:
Open Circuit State (C1 = 0, C2 = 0)
In this state the SLIC is effectively off. All detectors and
both the tip and ring line drive amplifiers are powered
down, presenting a high impedance to the line. Power
dissipation is at a minimum.
Active State (C1 = 0, C2 = 1)
The tip output is capable of sourcing loop current and for
open circuit conditions is about -4V from ground. The ring
output is capable of sinking loop current and for open circuit
conditions is about V
BAT
+4V. VF signal transmission is
normal. The loop current detector is active, E0 determines if
the detector is gated to the DET output.
TIP
RING
HC5515
R
RT
V
BAT
E
RG
R
3
R
4
R
2
R
1
DR
DT
RING TRIP
COMPARATOR
DET
C
RT
RINGRLY
RING
RELAY
+
-
FIGURE 18. RING TRIP CIRCUIT FOR BATTERY BACKED
RINGING
TIP
RING
V
BAT
/2
G
T
G
R
I
1
I
1
I
2
I
2
I
T
I
R
R
LARGE
R
LARGE
V
T
+
-
I
LONG
I
LONG
HC5515
I
LONG
I
LONG
V
R
+
-
V
C
+
-
V
BAT
/2
V
C
R
LARGE
R
LARGE
TIP
RING
5k
5k
20
+
-
2I
0
I
1
I
1
TIP CURRENT SOURCE
WITH DIFFERENTIAL INPUTS
TIP DIFFERENTIAL
TRANSCONDUCTANCE
AMPLIFIER
FIGURE 19A.
FIGURE 19B.
FIGURE 19. LONGITUDINAL IMPEDANCE NETWORK
HC5515
67
Ringing State (C1 = 1, C2 = 0)
The ring relay driver and the ring trip detector are activated.
Both the tip and ring line drive amplifiers are powered down.
Both tip and ring are disconnected from the line via the
external ring relay.
Standby State (C1 = 1, C2 = 1)
Both the tip and ring line drive amplifiers are powered down.
Internal resistors are connected between tip to ground and ring
to V
BAT
to allow loop current detect in an off-hook condition.
The loop current and ground key detectors are both active, E0
determines if the detector is gated to the DET output.
AC Transmission Circuit Stability
To ensure stability of the AC transmission feedback loop two
compensation capacitors C
TC
and C
RC
are required.
Figure 20 (Application Circuit) illustrates their use.
Recommended value is 2200pF.
AC-DC Separation Capacitor, C
HP
The high pass filter capacitor connected between pins HPT
and HPR provides the separation between circuits sensing
tip to ring DC conditions and circuits processing AC signals.
A 10nf C
HP
will position the low end frequency response
3dB break point at 48Hz. Where:
where R
HP
= 330k
.
Thermal Shutdown Protection
The HC5515's thermal shutdown protection is invoked if a
fault condition on the tip or ring causes the temperature of
the die to exceed 160
o
C. If this happens, the SLIC goes into
a high impedance state and will remain there until the
temperature of the die cools down by about 20
o
C. The SLIC
will return back to its normal operating mode, providing the
fault condition has been removed.
Surge Voltage Protection
The HC5515 must be protected against surge voltages and
power crosses. Refer to "Maximum Ratings" TIPX and
RINGX terminals for maximum allowable transient tip and
ring voltages. The protection circuit shown in Figure 20
utilizes diodes together with a clamping device to protect tip
and ring against high voltage transients.
Positive transients on tip or ring are clamped to within a
couple of volts above ground via diodes D
1
and D
2
. Under
normal operating conditions D
1
and D
2
are reverse biased
and out of the circuit.
Negative transients on tip and ring are clamped to within a
couple of volts below ground via diodes D
3
and D
4
with the
help of a Surgector. The Surgector is required to block
conduction through diodes D
3
and D
4
under normal
operating conditions and allows negative surges to be
returned to system ground.
The fuse resistors (R
F
) serve a dual purpose of being
nondestructive power dissipaters during surge and fuses
when the line in exposed to a power cross.
Power-Up Sequence
The HC5515 has no required power-up sequence. This is a
result of the Dielectrically Isolated (DI) process used in the
fabrication of the part. By using the DI process, care is no
longer required to insure that the substrate be kept at the
most negative potential as with junction isolated ICs.
Printed Circuit Board Layout
Care in the printed circuit board layout is essential for proper
operation. All connections to the RSN pin should be made as
close to the device pin as possible, to limit the interference
that might be injected into the RSN terminal. It is good
practice to surround the RSN pin with a ground plane.
The analog and digital grounds should be tied together at
the device.
SLIC Operating States
f
3dB
1
2
R
HP
C
HP
(
)
-----------------------------------------------------
=
(EQ. 28)
TABLE 1. LOGIC TRUTH TABLE
E0
C1
C2
SLIC OPERATING STATE
ACTIVE DETECTOR
DET OUTPUT
0
0
0
Open Circuit
No Active Detector
Logic Level High
0
0
1
Active
Loop Current Detector
Loop Current Status
0
1
0
Ringing
Ring Trip Detector
Ring Trip Status
0
1
1
Standby
Loop Current Detector
Loop Current Status
1
0
0
Open Circuit
No Active Detector
Logic Level High
1
0
1
Active
Loop Current Detector
1
1
0
Ringing
Ring Trip Detector
1
1
1
Standby
Loop Current Detector
HC5515
68
Notes
2. Overload Level (Two-Wire port) - The
overload
level
is
specified at the 2-wire port (V
TR0
) with the signal source at the
4-wire receive port (E
RX
). I
DCMET
= 30mA, R
SG
= 4k
,
increase the amplitude of E
RX
until 1% THD is measured at
V
TRO
. Reference Figure 1.
3. Longitudinal Impedance - The
longitudinal
impedance
is
computed using the following equations, where TIP and RING
voltages are referenced to ground. L
ZT
, L
ZR
, V
T
, V
R
, A
R
and
A
T
are defined in Figure 2.
(TIP) L
ZT
= V
T
/A
T
,
(RING) L
ZR
= V
R
/A
R
,
where: E
L
= 1V
RMS
(0Hz to 100Hz).
4. Longitudinal Current Limit (Off-Hook Active) - Off-Hook
(Active, C
1
= 1, C
2
= 0) longitudinal current limit is determined
by increasing the amplitude of E
L
(Figure 3A) until the 2-wire
longitudinal balance drops below 45dB. DET pin remains low
(no false detection).
5. Longitudinal Current Limit (On-Hook Standby) - On-Hook
(Active, C
1
= 1, C
2
= 1) longitudinal current limit is determined
by increasing the amplitude of E
L
(Figure 3B) until the 2-wire
longitudinal balance drops below 45dB. DET pin remains high
(no false detection).
6. Longitudinal to Metallic Balance - The longitudinal to metallic
balance is computed using the following equation:
BLME = 20
log (E
L
/V
TR
), where: E
L
and V
TR
are defined in
Figure 4.
7. Metallic to Longitudinal FCC Part 68, Para 68.310 - The
metallic to longitudinal balance is defined in this spec.
8. Longitudinal to Four-Wire Balance - The longitudinal to 4-wire
balance is computed using the following equation:
BLFE = 20
log (E
L
/V
TX
),: E
L
and V
TX
are defined in Figure 4.
9. Metallic to Longitudinal Balance - The metallic to longitudi-
nal balance is computed using the following equation:
BMLE = 20
log (E
TR
/V
L
), E
RX
= 0,
where: E
TR
, V
L
and E
RX
are defined in Figure 5.
10. Four-Wire to Longitudinal Balance - The 4-wire to longitudinal
balance is computed using the following equation:
BFLE = 20
log (E
RX
/V
L
), E
TR
= source is removed.
where: E
RX
, V
L
and E
TR
are defined in Figure 5.
11. Two-Wire Return Loss - The 2-wire return loss is computed
using the following equation:
r = -20
log (2V
M
/V
S
).
where: Z
D
= The desired impedance; e.g., the characteristic
impedance of the line, nominally 600
.
(Reference Figure 6).
12. Overload Level (4-Wire port) - The overload level is specified
at the 4-wire transmit port (V
TXO
) with the signal source (E
G
) at
the 2-wire port, I
DCMET
= 23mA, Z
L
= 20k
, R
SG
= 4k
(Refer-
ence Figure 7). Increase the amplitude of E
G
until 1% THD is
measured at V
TXO
. Note that the gain from the 2-wire port to
the 4-wire port is equal to 1.
13. Output Offset Voltage - The output offset voltage is specified
with the following conditions: E
G
= 0, I
DCMET
= 23mA, Z
L
=
and is measured at V
TX
. E
G
, I
DCMET
, V
TX
and Z
L
are defined
in Figure 7. Note: I
DCMET
is established with a series 600
resistor between tip and ring.
14. Two-Wire to Four-Wire (Metallic to V
TX
) Voltage Gain - The
2-wire to 4-wire (metallic to V
TX
) voltage gain is computed
using the following equation.
G
2-4
= (V
TX
/V
TR
), E
G
= 0dBm0, V
TX
, V
TR
, and E
G
are defined
in Figure 7.
15. Current Gain RSN to Metallic - The current gain RSN to
Metallic is computed using the following equation:
K = I
M
[(R
DC1
+ R
DC2
)/(V
RDC
- V
RSN
)]
K, I
M
, R
DC1
, R
DC2
,
V
RDC
and V
RSN
are defined in Figure 8.
16. Two-Wire to Four-Wire Frequency Response - The 2-wire to
4-wire frequency response is measured with respect to
E
G
= 0dBm at 1.0kHz, E
RX
= 0V, I
DCMET
= 23mA. The fre-
quency response is computed using the following equation:
F
2-4
= 20
log (V
TX
/V
TR
), vary frequency from 300Hz to
3.4kHz and compare to 1kHz reading.
V
TX
, V
TR
, and E
G
are defined in Figure 9.
17. Four-Wire to Two-Wire Frequency Response - The 4-wire to
2-wire frequency response is measured with respect to
E
RX
= 0dBm at 1.0kHz, E
G
= 0V, I
DCMET
= 23mA. The
frequency response is computed using the following equation:
F
4-2
= 20
log (V
TR
/E
RX
), vary frequency from 300Hz to
3.4kHz and compare to 1kHz reading.
V
TR
and E
RX
are defined in Figure 9.
18. Four-Wire to Four-Wire Frequency Response - The
4-wire
to 4-wire frequency response is measured with respect to
E
RX
= 0dBm at 1.0kHz, E
G
= 0V, I
DCMET
= 23mA. The
frequency response is computed using the following equation:
F
4-4
= 20
log (V
TX
/E
RX
), vary frequency from 300Hz to
3.4kHz and compare to 1kHz reading.
V
TX
and E
RX
are defined in Figure 9.
19. Two-Wire to Four-Wire Insertion Loss - The 2-wire to 4-wire
insertion loss is measured with respect to E
G
= 0dBm at 1.0kHz
input signal, E
RX
= 0, I
DCMET
= 23mA and is computed using
the following equation:
L
2-4
= 20
log (V
TX
/V
TR
)
where: V
TX
, V
TR
, and E
G
are defined in Figure 9. (Note: The
fuse resistors, R
F
, impact the insertion loss. The specified
insertion loss is for R
F
= 0).
20. Four-Wire to Two-Wire Insertion Loss - The 4-wire to 2-wire
insertion loss is measured based upon E
RX
= 0dBm, 1.0kHz
input signal, E
G
= 0, I
DCMET
= 23mA and is computed using
the following equation:
L
4-2
= 20
log (V
TR
/E
RX
),
where: V
TR
and E
RX
are defined in Figure 9.
21. Two-Wire to Four-Wire Gain Tracking - The 2-wire to 4-wire
gain tracking is referenced to measurements taken for
E
G
= -10dBm, 1.0kHz signal, E
RX
= 0, I
DCMET
= 23mA and is
computed using the following equation.
G
2-4
= 20
log (V
TX
/V
TR
) vary amplitude -40dBm to +3dBm, or
-55dBm to -40dBm and compare to -10dBm reading.
V
TX
and V
TR
are defined in Figure 9.
22. Four-Wire to Two-Wire Gain Tracking - The 4-wire to 2-wire
gain tracking is referenced to measurements taken for
HC5515
69
E
RX
= -10dBm, 1.0kHz signal, E
G
= 0, I
DCMET
= 23mA and is
computed using the following equation:
G
4-2
= 20
log (V
TR
/E
RX
) vary amplitude -40dBm to +3dBm,
or -55dBm to -40dBm and compare to -10dBm reading.
V
TR
and E
RX
are defined in Figure 9. The level is specified at
the 4-wire receive port and referenced to a 600
impedance
level.
23. Two-Wire Idle Channel Noise - The 2-wire idle channel noise
at V
TR
is specified with the 2-wire port terminated in 600
(R
L
)
and with the 4-wire receive port grounded (Reference Figure 10).
24. Four-Wire Idle Channel Noise - The 4-wire idle channel noise
at V
TX
is specified with the 2-wire port terminated in 600
(R
L
).
The noise specification is with respect to a 600
impedance
level at V
TX
. The 4-wire receive port is grounded (Reference
Figure 10).
25. Harmonic Distortion (2-Wire to 4-Wire) - The harmonic dis-
tortion is measured with the following conditions. E
G
= 0dBm
at 1kHz, I
DCMET
= 23mA. Measurement taken at V
TX
.
(Reference Figure 7).
26. Harmonic Distortion (4-Wire to 2-Wire) - The harmonic dis-
tortion is measured with the following conditions. E
RX
= 0dBm0.
Vary frequency between 300Hz and 3.4kHz, I
DCMET
= 23mA.
Measurement taken at V
TR
. (Reference Figure 9).
27. Constant Loop Current - The
constant
loop
current
is
calculated using the following equation:
I
L
= 2500 / (R
DC1
+ R
DC2
).
28. Standby State Loop Current - The standby state loop current
is calculated using the following equation:
I
L
= [|V
BAT
| - 3] / [R
L
+1800], T
A
= 25
o
C.
29. Power Supply Rejection Ratio - Inject a 100mV
RMS
signal
(50Hz to 4kHz) on V
BAT
, V
CC
and V
EE
supplies. PSRR is
computed using the following equation:
PSRR = 20
log (V
TX
/V
IN
). V
TX
and V
IN
are defined in Figure 11.
Pin Descriptions
PLCC
PDIP
SYMBOL
DESCRIPTION
1
RING
SENSE
Internally connected to output of RING power amplifier.
2
7
BGND
Battery Ground - To be connected to zero potential. All loop current and longitudinal current flow from this ground.
Internally separate from AGND but it is recommended that it is connected to the same potential as AGND.
4
8
V
CC
+5V power supply.
5
9
RINGRLY
Ring relay driver output.
6
10
V
BAT
Battery supply voltage, -24V to -56V.
7
11
R
SG
Saturation guard programming resistor pin.
8
12
NC
This pin is used during manufacturing.This pin is to be left open for proper SLIC operation .
9
13
E0
TTL compatible logic input. Enables the DET output when set to logic level zero and disables DET output when set to
a logic level one.
11
14
DET
Detector output. TTL compatible logic output. A zero logic level indicates that the selected detector was triggered (see
Truth Table for selection of Ground Key detector, Loop Current detector or the Ring Trip detector). The DET output is
an open collector with an internal pull-up of approximately 15k
to VCC.
12
15
C2
TTL compatible logic input. The logic states of C1 and C2 determine the operating states (Open Circuit, Active, Ringing
or Standby) of the SLIC.
13
16
C1
TTL compatible logic input. The logic states of C1 and C2 determine the operating states (Open Circuit, Active, Ringing
or Standby) of the SLIC.
14
17
R
DC
DC feed current programming resistor pin. Constant current feed is programmed by resistors R
DC1
and R
DC2
connected in series from this pin to the receive summing node (RSN). The resistor junction point is decoupled to AGND
to isolate the AC signal components.
15
18
AGND
Analog ground.
16
19
RSN
Receive Summing Node. The AC and DC current flowing into this pin establishes the metallic loop current that flows
between tip and ring. The magnitude of the metallic loop current is 1000 times greater than the current into the RSN
pin. The constant current programming resistors and the networks for program receive gain and 2-wire impedance all
connect to this pin.
18
20
V
EE
-5V power supply.
19
21
V
TX
Transmit audio output. This output is equivalent to the TIP to RING metallic voltage. The network for programming the
2-wire input impedance connects between this pin and RSN.
HC5515
70
20
22
HPR
RING side of AC/DC separation capacitor C
HP
. C
HP
is required to properly separate the ring AC current from the DC
loop current. The other end of C
HP
is connected to HPT.
21
1
HPT
TIP side of AC/DC separation capacitor C
HP
. C
HP
is required to properly separate the tip AC current from the DC loop
current. The other end of C
HP
is connected to HPR.
22
2
RD
Loop current programming resistor. Resistor R
D
sets the trigger level for the loop current detect circuit. A filter capacitor
C
D
is also connected between this pin and V
EE
.
23
3
DT
Input to ring trip comparator. Ring trip detection is accomplished by connecting an external network to a comparator
in the SLIC with inputs DT and DR.
25
4
DR
Input to ring trip comparator. Ring trip detection is accomplished by connecting an external network to a comparator
in the SLIC with inputs DT and DR.
26
TIP
SENSE
Internally connected to output of tip power amplifier.
27
5
TIPX
Output of tip power amplifier.
28
6
RINGX
Output of ring power amplifier.
3, 10
17, 24
N/C
No internal connection.
Pin Descriptions
(Continued)
PLCC
PDIP
SYMBOL
DESCRIPTION
Pinouts
HC5515
(PLCC)
TOP VIEW
HC5515
(PDIP)
TOP VIEW
R
DC
A
GND
RSN
N/C
V
EE
C2
C1
BGND
RING
SENSE
RINGX
TIPX
TIP
SENSE
V
CC
N/C
N/C
DT
RD
HPT
DR
V
TX
HPR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
BAT
R
SG
NC
E0
RINGRLY
DET
N/C
1
11
10
9
8
7
6
5
3
2
4
22
12
13
14
15
16
17
18
19
21
20
RD
DT
DR
TIPX
RINGX
BGND
RINGRLY
V
CC
V
BAT
R
SG
V
TX
RSN
AGND
R
DC
V
EE
C1
C2
DET
E0
NC
HPT
HPR
HC5515
71
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Application Circuit
21 HPT
22 RD
23 DT
25 DR
27 TIPX
28 RINGX
2 BGND
4 V
CC
5 RINGRLY
6 V
BAT
7 R
SG
HPR 20
V
TX
19
V
EE
18
RSN 16
AGND 15
R
DC
14
C1 13
C2 12
DET 11
E
O
9
E
1
8
TIP
RING
V
BAT
R
3
R
RT
R
2
-5V
R
D
R
F1
R
F2
C
RC
C
TC
RINGING
(V
BAT
+ 90V
RMS
)
V
BAT
C
HP
(NOTE 32)
-5V
R
TX
R
T
R
B
R
DC1
C
DC
R
DC2
R
FB
CODEC/FILTER
U
2
U
1
R
RX
-
+
C
RT
R
1
R
4
NOTE 31
-5V
R
SG
U1 SLIC (Subscriber Line Interface Circuit)
HC5515
U2 Combination CODEC/Filter e.g.
CD22354A or Programmable CODEC/
Filter, e.g. SLAC
C
DC
1.5
F, 20%, 10V
C
HP
10nF, 20%, 100V (Note 2)
C
RT
0.39
F, 20%, 100V
C
TC
, C
RC
2200pF, 20%, 100V
Relay Relay, 2C Contacts, 5V or 12V Coil
D
1
- D
5
IN4007 Diode
Surgector SGT27S10
PTC Polyswitch TR600-150
D
6
Diode, 1N4454
R
F1
, R
F2
Line Resistor, 20
, 1% Match, 2 W
Carbon column resistor or thick film on
ceramic
R
1
, R
3
200k
, 5%, 1/4W
R
2
910k
, 5%, 1/4W
R
4
1.2M
, 5%, 1/4W
R
B
18.7k
,1%, 1/4W
R
D
39k
, 5%, 1/4W
R
DC1
, R
DC2
41.2k
, 5%, 1/4W
R
FB
20.0k
, 1%, 1/4W
R
RX
280k
, 1%, 1/4W
R
T
562k
, 1%, 1/4W
R
TX
20k
, 1%, 1/4W
R
RT
150
, 5%, 2W
R
SG
V
BAT
= -28V, R
SG
=
V
BAT
= -48V, R
SG
= 4.0k
, 1/4W 5%
NOTES:
30. It is recommended that the anodes of D
3
and D
4
be shorted to ground through a battery referenced surgector (SGT27S10).
31. To meet the specified 25dB 2-wire return loss at 200Hz, C
HP
needs to be 20nF, 20%, 100V.
FIGURE 20. APPLICATION CIRCUIT
+5V
RELAY
D
6
OR
12V
PTC
PTC
Surgector
A
K
G
D
3
D
1
D
2
D
4
D
5
HC5515