69
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HC-5560
PCM Transcoder
The HC-5560 digital line transcoder provides encoding and
decoding of pseudo ternary line code substitution schemes.
Unlike other industry standard transcoders, the HC-5560
provides four worldwide compatible mode selectable code
substitution schemes, including HDB3 (High Density Bipolar
3), B6ZS, B8ZS (Bipolar with 6 or 8 Zero Substitution) and
AMI (Alternate Mark Inversion).
The HC-5560 is fabricated in CMOS and operates from a
single 5V supply. All inputs and outputs are TTL compatible.
Application Note #573, "The HC-5560 Digital Line
Transcoder," by D.J. Donovan is available.
Pinout
HC-5560
(PDIP)
TOP VIEW
Features
Single 5V Supply . . . . . . . . . . . . . . . . . . . . . . .10mA (Typ)
Mode Selectable Coding Including:
- AMI (T1, T1C)
- B8ZS (T1)
- HDB3 (PCM30)
North American and European Compatibility
Simultaneous Encoding and Decoding
Asynchronous Operation
Loop Back Control
Transmission Error Detection
Alarm Indication Signal
Replaces MJ1440, MJ1471 and TCM2201 Transcoders
Applications
North American and European PCM Transmission Lines
where Pseudo Ternary Line Code Substitution Schemes
are Desired
Any Equipment that Interfaces T1, T1C, T2 or PCM30
Lines Including Multiplexers, Channel Service Units,
(CSUs) Echo Cancellors, Digital Cross-Connects (DSXs),
T1 Compressors, etc.
Related Literature
- AN573, The HC-5560 Digital Line Transcoder
Functional Diagram
Ordering Information
PART
NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
PKG. NO.
HC3-5560-5
0 to 70
20 Ld PDIP
E20.3
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
FORCE AIS
MODE SELECT 1
NRZ DATA IN
CLK ENC
MODE SELECT 2
NRZ DATA OUT
RESET AIS
CLK DEC
AIS
V
SS
V
DD
RESET
OUT1
OUT2
OUTPUT ENABLE
B
IN
LOOP TEST ENABLE
A
IN
CLOCK
ERROR
TRANSMITTER/
ENCODER
SWITCH
RECEIVER/
DECODER
AIS
DETECT
ERROR
DETECT
V
SS
V
DD
CLOCK
OUT 1
OUT 2
NRZ DATA
OUT
ERROR
AIS
MODE
SELECT
NRZ DATA IN
CLK ENC
OUTPUT
ENABLE
LOOP TEST
ENABLE
A
IN
B
IN
FORCE AIS
RESET
CLK DEC
RESET AIS
1
2
Data Sheet
January 1997
File Number
2887.2
70
Absolute Maximum Ratings
Thermal Information
Voltage at Any Pin . . . . . . . . . . . . . . . . . . . . GND -0.3V to V
DD
0.3V
Maximum V
DD
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . . . . . 0
o
C to 70
o
C
Operating V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
5%
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .175
o
C
Maximum Junction Temperature (Plastic Package) . . . . . . . . .150
o
C
Storage Temperature Range . . . . . . . . . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . 300
o
Die Characteristics
Transistor Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4322
Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . .119 mils x 133 mils
Substrate Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+V
Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAJI CMOS
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Unless Otherwise Specified, Typical parameters at 25
o
C, Min-Max parameters are over operating
temperature range. V
DD
= 5V
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
STATIC SPECIFICATIONS
Quiescent Device Current
l
DD
100
A
Operating Device Current
10
mA
OUT1, OUT2 Low (Sink) Current
(V
OL
= 0.4V)
I
OL1
3.2
mA
All Other Outputs Low (Sink) Current
(V
OL
= 0.8V)
I
OL2
2
mA
All Outputs High (Source) Current
(V
OH
= 4V)
I
OH
2
mA
Input Low Current
I
IL
10
A
Input High Current
I
IH
10
A
Input Low Voltage
V
lL
0.8
V
Input High Voltage
V
lH
2.4
V
Input Capacitance
C
lN
8
pF
Electrical Specifications
Unless Otherwise Specified, Typical parameters at 25
o
C, Min-Max parameters are over operating
temperature range. V
DD
= 5V
PARAMETER
SYMBOL
FIGURE
MIN
TYP
MAX
UNITS
DYNAMIC SPECIFICATIONS
CLK ENC, CLK DEC Input Frequency
f
CL
8.5
MHz
CLK ENC,CLK DEC Rise Time (1.544MHz)
t
RCL
1, 2
10
60
ns
Fall Time
t
FCL
1, 2
10
60
ns
Rise Time (2.048MHz)
t
RCL
1, 2
10
40
ns
Fall Time
t
FCL
1, 2
10
40
ns
Rise Time (6.3212MHz)
t
RCL
1, 2
10
30
ns
Fall Time
t
FCL
1, 2
10
30
ns
Rise Time (8.448MHz)
t
RCL
1, 2
5
10
ns
Fall Time
t
FCL
1, 2
5
10
ns
HC-5560
71
NRZ-Data In to CLK ENC Data Setup Time
t
S
1
20
-
-
ns
Data Hold Time
t
H
1
20
-
-
ns
A
IN
, B
IN
to CLK DEC Data Setup Time
t
S
2
15
-
-
ns
Data Hold Time
t
H
2
5
-
-
ns
CLK ENC to OUT1, OUT2
t
DD
1
-
23
80
ns
OUT1, OUT2 Pulse Width (CLK ENC Duty Cycle = 50%)
f
CL
= 1.544MHz
t
W
1
-
324
-
ns
f
CL
= 2.048MHz
t
W
1
-
224
-
ns
f
CL
= 6.3212MHz
t
W
1
-
79
-
ns
f
CL
=
8.448MHz
t
W
1
-
58
-
ns
CLK DEC to NRZ-Data Out
t
DD
2
-
25
54
ns
Setup Time CLK DEC to Reset AlS
t
S2
3
35
-
-
ns
Hold Time of Reset AlS = `0'
t
H2
3
20
-
-
ns
Setup Time Reset AlS = `1' to CLK DEC
t
S2
3
0
-
-
ns
Reset AlS to AIS output
t
PD5
3
-
-
42
ns
CLK DEC to Error output
t
PD4
3
-
-
62
ns
Electrical Specifications
Unless Otherwise Specified, Typical parameters at 25
o
C, Min-Max parameters are over operating
temperature range. V
DD
= 5V (Continued)
PARAMETER
SYMBOL
FIGURE
MIN
TYP
MAX
UNITS
Pin Descriptions
PIN NUMBER
FUNCTION
DESCRIPTION
1
Force AIS
Pin 19 must be at logic `0' to enable this pin. A logic `1' on this pin forces OUT1 and OUT2 to all `1's. A logic
`0' on this pin allows normal operation.
2, 5
Mode Select 1,
Mode Select 2
MS1
MS2
Functions As
0
0
AMI
0
1
B8ZS
1
0
B6ZS
1
1
HDB3
3
NRZ Data In
Input data to be encoded into ternary form. The data is clocked by the negative going edge of CLK ENC.
4
CLK ENC
Clock encoder, clock for encoding data at NRZ Data In.
6
NRZ Data Out
Decoded data from ternary inputs A
IN
and B
IN
.
7
CLK DEC
Clock decoder, clock for decoding ternary data on inputs A
IN
and B
IN
.
8, 9
Reset AIS, AlS
Logic `0' on Reset AIS resets a decoded zero counter and either resets AIS output to zero provided 3 or more
zeros have been decoded in the preceding Reset AIS period or sets AlS to `1' if less than 3 zeros have been
decoded in the preceding two Reset AlS periods. A period of Reset AlS is defined from the bit following the
bit during which Reset AlS makes a high to low transition to the bit during which Reset AIS makes the next
high to low transition.
10
V
SS
Ground reference.
11
Error
A logic `1' indicates that a violation of the line coding scheme has been decoded.
12
Clock
"OR" function of A
IN
and B
IN
for clock regeneration when pin 14 is at logic `0', "OR" function of OUT1 and
OUT2 when pin 14 is at logic `1'.
13, 15
A
IN
, B
IN
Inputs representing the received PCM signal. A
IN
= `1' represents a positive going `1' and B
IN
= `1' represents
a negative going `1'. A
IN
and B
IN
are sampled by the positive going edge of CLK DEC. A
IN
and B
IN
may be
interchanged.
HC-5560
72
Functional Description
The HC-5560 TRANSCODER can be divided into six sec-
tions: transmission (coding), reception (decoding), error
detection, all ones detection, testing functions, and output
controls.
The transmitter codes a non-return to zero (NRZ) binary uni-
polar input signal (NRZ Data In) into two binary unipolar
return to zero (RZ) output signals (OUT1, OUT2). These out-
put signals represent the NRZ data stream modified accord-
ing to the selected encoding scheme (i.e., AMl, B8ZS, B6ZS,
HDB3) and are externally mixed together (usually via a tran-
sistor or transformer network) to create a ternary bipolar sig-
nal for driving transmission lines.
The receiver accepts as its input the ternary data from the
transmission line that has been externally split into two
binary unipolar return to zero signals (A
IN
and B
IN
). These
signals are decoded, according to the rules of the selected
line code into one binary unipolar NRZ output signal (NRz
Data Out).
The encoder and decoder sections of the chip perform inde-
pendently (excluding loopback condition) and may operate
simultaneously.
The Error output signal is active high for one cycle of CLK
DEC upon the detection of any bipolar violation in the
received A
IN
and B
IN
signals that is not part of the selected
line coding scheme. The bipolar violation is not removed,
however, and shows up as a pulse in the NRZ Data Out sig-
nal. In addition, the Error output signal monitors the received
A
IN
and B
IN
signals for a string of zeros that violates the
maximum consecutive zeros allowed for the selected line
coding scheme (i.e., 15 for AMI, 8 for B8ZS, 6 for B6ZS, and
4 for HDB3). ln the event that an excessive amount of zeros
is detected, the Error output signal will be active high for one
cycle of CLK DEC during the zero that exceeds the maxi-
mum number. In the case that a high level should simulta-
neously appear on both received input signals A
IN
and B
IN
a
logical one is assumed and appears on the NRZ Data Out
stream with the Error output active.
An input signal received at inputs A
IN
and B
IN
that consists
of all ones (or marks) is detected and signaled by a high
level at the Alarm Indication Signal (AlS) output. This is also
known as Blue Code. The AlS output is set to a high level
when less than three zeros are received during one period of
Reset AIS immediately followed by another period of Reset
AlS containing less than three zeros. The AIS output is reset
to a low level upon the first period of Reset AlS containing 3
or more zeros.
A logic high level on LTE enables a loopback condition
where OUT1 is internally connected to A
IN
and OUT2 is
internally connected to B
IN
(this disables inputs A
IN
and B
IN
to external signals). In this condition, NRZ Data In appears
at NRZ Data Out (delayed by the amount of clock cycles it
takes to encode and decode the selected line code). A
decode clock must be supplied for this operation.
The output controls are Output Enable and Force AlS. These
pins allow normal operation, force OUT1 and OUT2 to zero,
or force OUT1 and OUT2 to output all ones (AIS condition).
Line Code Descriptions
AMl, Alternate Mark Inversion, is used primarily in North
American T1 (1.544MHz) and T1C (3.152MHz) carriers.
Zeros are coded as the absence of a pulse and ones are
coded alternately as positive or negative pulses. This type of
coding reduces the average voltage level to zero to eliminate
DC spectral components, thereby eliminating DC wander. To
simplify timing recovery, logic 1's are encoded with 50% duty
cycle pulses.
e.g.,
To facilitate timing maintenance at regenerative repeaters
along a transmission path, a minimum pulse density of logic
1s is required. Using AMl, there is a possibility of long strings
of zeros and the required density may not always exist, lead-
ing to timing jitter and therefore higher error rates.
A method for insuring minimum logic 1 density by substituting
bipolar code in place of strings of 0s is called BNZS or Bipolar
14
LTE
Loop Test Enable, this pin selects between normal and loop back operation. A logic `0' selects normal oper-
ation where encode and decode are independent and asynchronous. A logic `1' selects a loop back condition
where OUT1 is internally connected to A
IN
and OUT2 is internally connected to B
IN
. A decode clock must
be supplied.
16, 17
OUT1, OUT2
Outputs representing the ternary encoded NRZ Data In signal for line transmission. OUT1 and OUT2 are in
return to zero form and are clocked out on the positive going edge of CLK ENC. The length of OUT1 and
OUT2 is set by the length of the positive clock pulse.
18
Reset
A logic `0' on this pin resets all internal registers to zero. A logic `1' allows normal operation of all internal
registers.
19
Output Enable
A logic `1' on this pin forces outputs OUT1 and OUT2 to zero. A logic `0' allows normal operation.
20
V
DD
Power to chip.
Pin Descriptions
(Continued)
PIN NUMBER
FUNCTION
DESCRIPTION
0
1
0
0
0
0
0
0
0 0
0
1
1
1
1
1
PCM CODE
AMI CODE
HC-5560
73
with N Zero Substitution. B6ZS is used commonly in North
American T2 (6.3212MHz) carriers. For every string of 6
zeros, bipolar code is substituted according to the following
rule:
If the immediate preceding pulse is of (-) polarity, then
code each group of 6 zeros as 0+- 0+-, and if the
immediate preceding pulse is of (+) polarity, code each
group of 6 zeros as 0+- 0-+.
One can see the consecutive logic 1 pulses of the same
polarity violate the AMI coding scheme.
e.g.,
B8ZS is used commonly in North American T1 (1.544MHz)
and T1C (3.152MHz) carriers. For every string of 8 zeros,
bipolar code is substituted according to the following rules:
1. If the immediate preceding pulse is of (-) polarity, then
code each group of 8 zeros as 000-+ 0+-.
2. If the immediate preceding pulse is of (+) polarity then
code each group of 8 zeros as 000+-0-+.
e.g.,
The BNZS coding schemes, in addition to eliminating DC
wander, minimize timing jitter and allow a line error monitor-
ing capability.
Another coding scheme is HDB3, high density bipolar 3, used
primarily in Europe for 2.048MHz and 8.448MHz carriers. This
code is similar to BNZS in that it substitutes bipolar code for 4
consecutive zeros according to the following rule:
1. If the polarity of the immediate preceding pulse is (-)
and there have been an odd (even) number of logic 1
pulses since the last substitution, each group of 4 con-
secutive zeros is coded as 000-(+00+).
2. If the polarity of the immediate preceding pulse is (+)
then the substitution is 000+(-00-) for odd (even) num-
ber of logic 1 pulses since the last substitution.
e.g.,
The 3 in HDB3 refers to the coding format that precludes
strings of zeros greater than 3. Note that violations are pro-
duced only in the fourth bit location of the substitution code
and that successive substitutions produce alternate polarity
violations.
0
1
0
0
0
0
0
0
0
0
0
1 1 1
1
0
0
-
+
+
-
0
0
+
-
-
+
V
V
V
V
B6ZS (+)
B6ZS (
-
)
PCM CODE
6
V = VIOLATION
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
+
+
-
-
-
+
+
V
V
V
V = VIOLATION
PCM CODE
B8ZS (
-
)
B8ZS (+)
8
PCM CODE
0
1
0
0
0
0
0
0
0 0
0
0
0
0
0
0
0
1
1 1
1
0
0
0
0
0
-
+
-
-
+
+
V = VIOLATION
HDB3 (-)
HDB3 (+)
V
V
V
V
4
4
HC-5560
74
Application Diagram
DIFF
AMP
FROM CODEC OR
TRANSCODER
ENCODER CLOCK
V
DD
NRZ DATA IN
OUT1
CLK ENC
OUT2
FORCE AIS
MS1
LTE
CONTROL
MS2
CLOCK
RESET
ENCODER
OUTPUT
ENABLE
RESET AIS
AIS
ERROR
A
IN
B
IN
CLK DEC
V
SS
NRZ DATA OUT
DECODER
DECODER CLOCK
V+
5V
MODE SELECT
LOGIC INPUTS
CLOCK RECOVERY
ALARM CLOCK
ALARM
ERROR
ERROR
MONITORS
TO CODED OR TRANSCODER
T1, T2, T1C,
PCM 30
LINE OUTPUT
V+
MS1
MS2
SELECTS
0
1
AMI
B8ZS
B6ZS
HDB3
1
1
1
0
0
0
LINE
INPUT
Timing Waveforms
FIGURE 1. TRANSMITTER (CODER) TIMING WAVEFORMS
CLK ENC
NRZ DATA IN
OUT 1, OUT 2
t
RCL
t
FCL
t
S
t
DD
t
H
f
CL
t
W
50%
50%
50%
50%
10%
90%
50%
1
HC-5560
75
FIGURE 2. RECEIVER (DECODER) TIMING WAVEFORMS
FIGURE 3. RESET AIS INPUT, AIS OUTPUT, ERROR OUTPUT
FIGURE 4.
Two consecutive periods of Reset AIS, each containing less than three zeros, sets AIS to a logic `1' and remains in a logic `1' state
until a period of Reset AIS contains three or more zeros.
Timing Waveforms
(Continued)
CLK DEC
A
IN
, B
IN
CLOCK
NRZ DATA OUT
t
FCL
t
RCL
t
S
t
H
t
DD
50%
f
CL
1
10%
90%
50%
50%
50%
CLK DEC
RESET AIS
AIS OUTPUT
ERROR OUTPUT
t
S2
t
PD5
t
S2
t
PD4
t
H2
50%
50%
50%
50%
50%
50%
CLK DEC
RESET AIS
NRZ DATA OUT
AIS
HC-5560
76
FIGURE 5.
Zeros which occur during a high to low transition of Reset AIS are counted with the zeros that occurred before the high to low transi-
tion.
FIGURE 6. ENCODE TIMING AND DELAY
Data is clocked on the negative edge of CLK ENC and appears on OUT1 and OUT2. OUT1 and OUT2 are interchangeable. Bipo-
lar violations and all other pulses inserted by the line coding scheme to encode strings of zeros are labeled with an "S".
Timing Waveforms
(Continued)
CLK DEC
RESET AIS
NRZ DATA OUT
AIS
S
S
S
S
S
S
S
S
S
S
S
S
NRZ DATA IN
CLK ENC
OUT 1
OUT 2
OUT 1
OUT 2
OUT 1
OUT 2
OUT 1
OUT 2
AMI
HDB3
B6ZS
B8ZS
3 1/2 CYCLES
5 1/2 CYCLES
HC-5560
77
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
FIGURE 7. DECODE TIMING AND DELAY
Data that appears on A
IN
and B
IN
is clocked by the positive edge of CLK DEC, decoded, and zeros are inserted for all valid line
code substitutions. The data then appears in non-return to zero to zero form at output NRZ Data Out. A
IN
and B
IN
are
interchangeable.
FIGURE 8.
The ERROR signal indicates bipolar violations that are not part of a valid substitution.
Timing Waveforms
(Continued)
4 CYCLES
6 CYCLES
8 CYCLES
NRZ DATA OUT
B
IN
A
IN
B8ZS
B
IN
A
IN
B
IN
A
IN
B
IN
A
IN
NRZ DATA OUT
NRZ DATA OUT
NRZ DATA OUT
B6ZS
HDB3
AMI
CLK DEC
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
E
E
S
S
S
E
NRZ DATA
OUT
B
IN
A
IN
ERROR
CLK DEC
HC-5560
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