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Электронный компонент: HCTS244DTR

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1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
Satellite Applications FlowTM (SAF) is a trademark of Intersil Corporation.
HCTS244T
Radiation Hardened Octal Buffer/Line
Driver, Three-State
Intersil`s Satellite Applications Flow
TM
(SAF) devices are
fully tested and guaranteed to 100kRAD total dose. These
QML Class T devices are processed to a standard flow
intended to meet the cost and shorter lead-time needs of
large volume satellite manufacturers, while maintaining a
high level of reliability.
The Intersil HCTS244T is a Radiation Hardened Non-
Inverting Octal Buffer/Line Driver, Three-State, with two
active-low output enables.
Specifications
Specifications for Rad Hard QML devices are controlled by
the Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.
Detailed Electrical Specifications for the HCTS244T are
contained in SMD 5962-95744.
A "hot-link" is provided from
our website for downloading.
www.intersil.com/spacedefense/newsafclasst.asp
Intersil`s Quality Management Plan (QM Plan), listing all
Class T screening operations, is also available on our
website.
www.intersil.com/quality/manuals.asp
Features
QML Class T, Per MIL-PRF-38535
Radiation Performance
- Gamma Dose (
) 1 x 10
5
RAD(Si)
- Latch-Up Free Under Any Conditions
- SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
- Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/Bit-Day (Typ)
3 Micron Radiation Hardened CMOS SOS
Fanout (Over Temperature Range)
- Bus Driver Outputs - 15 LSTTL Loads
Significant Power Reduction Compared to LSTTL ICs
DC Operating Voltage Range: 4.5V to 5.5V
LSTTL Input Compatibility
- V
IL
= 0.8V Max
- VI
H
= V
CC/2
Min
Input Current Levels Ii
5mA at V
OL
, V
OH
Pinouts
HCTS244DTR (SBDIP), CDIP2-T20
TOP VIEW
HCTS244KTR (FLATPACK), CDFP4-F20
TOP VIEW
Ordering Information
ORDERING
NUMBER
PART
NUMBER
TEMP.
RANGE
(
o
C)
5962R9574401TRC
HCTS244DTR
-55 to 125
5962R9574401TXC
HCTS244KTR
-55 to 125
NOTE:
Minimum order quantity for -T is 150 units through
distribution, or 450 units direct.
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
OE
A0
Y3
A1
Y2
A2
A3
Y1
Y0
GND
V
CC
Y0
A3
Y1
OE
A2
Y2
A1
Y3
A0
1
1
2
1
2
1
1
2
2
1
2
1
2
2
1
2
1
2
2
3
4
5
6
7
8
1
20
19
18
17
16
15
14
13
9
10
12
11
OE
A0
Y3
A1
Y2
A2
A3
Y1
Y0
GND
V
CC
Y0
A3
Y1
OE
A2
Y2
A1
Y3
A0
1
1
2
1
2
1
1
2
2
1
2
1
2
2
1
2
1
2
Data Sheet
July 1999
File Number
4618.1
2
Functional Diagram
TRUTH TABLE
INPUTS
OUTPUT
1OE, 2OE
A
Y
L
L
L
L
H
H
H
X
Z
H = High Voltage Level.
L = Low Voltage Level.
X = Immaterial.
Z = High Impedance.
N
P
N
P
N
P
N
P
P
N
P
N
P
N
P
N
19
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
3
5
7
9
12
14
16
18
1
1OE
2OE
2
4
6
8
11
13
15
17
1A0
1A1
1A2
1A3
2A0
2A1
2A2
2A3
HCTS244T
3
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Die Characteristics
DIE DIMENSIONS:
(2743
m x 2692
m x 533
m
51
m)
108 x 106 x 21mils
2mil
METALLIZATION:
Type: Al Si
Thickness: 11.0k
1k
SUBSTRATE POTENTIAL:
Unbiased Silicon on Sapphire
BACKSIDE FINISH:
Sapphire
PASSIVATION:
Type: Silox (S
i
O
2
)
Thickness: 13.0k
2.6k
WORST CASE CURRENT DENSITY:
< 2.0e5 A/cm
2
TRANSISTOR COUNT:
264
PROCESS:
CMOS SOS
Metallization Mask Layout
HCTS244T
1OE
(1)
2OE
(19)
V
CC
(20)
1A0
(2)
1A1 (4)
2Y3
(3)
2Y2 (5)
1A2 (6)
2Y1 (7)
(8)
(9)
(10)
(11)
(12)
(13)
1A3
2Y0
GND
2A0
1Y3
2A1
(14) 1Y2
(15) 2A2
(16) 1Y1
(17) 2A3
(18) 1Y0
NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location. The mask
series for the HCTS244 is TA14402A.
HCTS244T