1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
Satellite Applications FlowTM (SAF) is a trademark of Intersil Corporation.
HCTS373T
Radiation Hardened Octal Transparent
Latch, Three-State
Intersil's Satellite Applications Flow
TM
(SAF) devices are fully
tested and guaranteed to 100kRAD total dose. These QML
Class T devices are processed to a standard flow intended
to meet the cost and shorter lead-time needs of large
volume satellite manufacturers, while maintaining a high
level of reliability.
The Intersil HCTS373T is a Radiation Hardened Octal
Transparent Three-State Latch with an active-low output
enable. The outputs are transparent to the inputs when the
Latch Enable (LE) is HIGH. When the Latch Enable (LE)
goes LOW, the data is latched. The Output Enable (OE)
controls the three-state outputs. When the Output Enable
(OE) is HIGH, the outputs are in the high impedance state.
The latch operation is independent of the state of the Output
Enable.
Specifications
Specifications for Rad Hard QML devices are controlled by
the Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.
Detailed Electrical Specifications for the HCTS373T are
contained in SMD 5962-95747. A "hot-link" is provided from
our website for downloading.
www.intersil.com/spacedefense/newsafclasst.asp
Intersil's Quality Management Plan (QM Plan), listing all
Class T screening operations, is also available on our
website.
www.intersil.com/quality/manuals.asp
Features
QML Class T, Per MIL-PRF-38535
Radiation Performance
- Gamma Dose (
) 1 x 10
5
RAD(Si)
- Latch-Up Free Under Any Conditions
- SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
- Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/Bit-Day (Typ)
3 Micron Radiation Hardened CMOS SOS
Fanout (Over Temperature Range)
- Bus Driver Outputs - 15 LSTTL Loads
Significant Power Reduction Compared to LSTTL ICs
DC Operating Voltage Range: 4.5V to 5.5V
LSTTL Input Compatibility
- V
IL
= 0.8V Max
- V
IH
= V
CC/2
Min
Input Current Levels Ii
5mA at V
OL
, V
OH
Pinouts
HCTS373T (SBDIP), CDIP2-T20
TOP VIEW
HCTS373T (FLATPACK), CDFP4-F20
TOP VIEW
Ordering Information
ORDERING
NUMBER
PART
NUMBER
TEMP.
RANGE
(
o
C)
5962R9574701TRC
HCTS373DTR
-55 to 125
5962R9574701TXC
HCTS373KTR
-55 to 125
NOTE:
Minimum order quantity for -T is 150 units through
distribution, or 450 units direct.
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
OE
Q0
D0
D1
Q1
Q2
D3
D2
Q3
GND
V
CC
D7
D6
Q6
Q7
Q5
D5
D4
Q4
LE
2
3
4
5
6
7
8
1
20
19
18
17
16
15
14
13
OE
Q0
D0
D1
Q1
Q2
D2
D3
9
10
12
11
Q3
GND
V
CC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
LE
Data Sheet
July 1999
File Number
4628.1
3
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Die Characteristics
DIE DIMENSIONS:
(2743
m x 2692
m x 533
m
51
m)
108 x 106 x 21mils
2mil
METALLIZATION:
Type: Al Si
Thickness: 11k
1k
SUBSTRATE POTENTIAL:
Unbiased (Silicon on Sapphire)
BACKSIDE FINISH:
Sapphire
PASSIVATION:
Type: Silox (S
i
O
2
)
Thickness: 13k
2.6k
WORST CASE CURRENT DENSITY:
< 2.0e5 A/cm
2
TRANSISTOR COUNT:
376
PROCESS:
CMOS SOS
Metallization Mask Layout
HCTS373T
OE
(1)
Q7
(19)
V
CC
(20)
Q0
(2)
D1 (4)
D0
(3)
Q1 (5)
Q2 (6)
D2 (7)
(8)
(9)
(10)
(11)
(12)
(13)
D3
Q3
GND
LE
Q4
D4
(14) D5
(15) Q5
(16) Q6
(17) D6
(18) D7
NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location. The mask
series for the HCTS373 is TA14403A.
HCTS373T
PDF 
ZIP