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Электронный компонент: HCTS646DMSR

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706
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
Ordering Information
PART NUMBER
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
HCTS646DMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
24 Lead SBDIP
HCTS646KMSR
-55
o
C to +125
o
C
Intersil Class S Equivalent
24 Lead Ceramic Flatpack
HCTS646D/Sample
+25
o
C
Sample
24 Lead SBDIP
HCTS646K/Sample
+25
o
C
Sample
24 Lead Ceramic Flatpack
HCTS646HMSR
+25
o
C
Die
Die
HCTS646MS
Radiation Hardened
Octal Bus Transceiver/Register, Three-State
Pinouts
24 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T24
TOP VIEW
24 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F24
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
CAB
SAB
DIR
A0
A1
A2
A3
A4
A5
A6
A7
GND
16
17
18
19
20
21
22
23
24
15
14
13
VCC
SBA
OE
B0
B1
B3
B5
B6
B7
CBA
B2
B4
24
23
22
21
20
19
18
17
16
15
14
13
2
3
4
5
6
7
8
9
10
11
12
1
CAB
SAB
DIR
A0
A1
A2
A3
A4
A5
A6
A7
GND
VCC
SBA
OE
B0
B1
B3
B5
B6
B7
CBA
B2
B4
Features
3 Micron Radiation Hardened CMOS SOS
Total Dose 200K RAD (Si)
SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/
Bit-Day (Typ)
Dose Rate Survivability: >1 x 10
12
RAD (Si)/s
Dose Rate Upset >10
10
RAD (Si)/s 20ns Pulse
Cosmic Ray Upset Rate 2 x 10
-9
Errors/Bit Day
Latch-Up Free Under Any Conditions
Fanout (Over Temperature Range)
- Bus Driver Outputs - 15 LSTTL Loads
Military Temperature Range: -55
o
C to +125
o
C
Significant Power Reduction Compared to LSTTL ICs
DC Operating Voltage Range: 4.5V to 5.5V
LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2
Input Current Levels Ii
5
A at VOL, VOH
Description
The Intersil HCTS646MS is a Radiation Hardened Three-
State Octal Bus Tranceiver/Register with Non-Inverting
outputs. This device is a bus transceiver with D-type flip-flops
which act as internal storage registers. Data on the A bus or
the B bus can be clocked into the registers on a High-to-Low
transition of either CAB ro CBA clock inputs. Output enable
(OE) and Direction (DIR) inputs control the transceiver func-
tions. Data present at the high impedance output can be
stored in either register or both but only one of the two buses
can be enabled as outputs at any one time. The select con-
trols (SAB and SBA) can multiplex stored and transparent
(real time) data. The direction control determines which data
bus will receive data when the OE pin is LOW. In the high
impedance mode (OE high), A data can be stored in one reg-
ister and B data in the other register. Data at the A or B termi-
nals can be clocked into the storage flip-flops at any time.
The HCTS646MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS646MS is supplied in a 24 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
August 1995
Spec Number
518628
File Number
3074.1
707
HCTS646MS
Functional Diagram
TRUTH TABLE
INPUTS
DATA I/O*
OPERATION OR FUNCTION
OE
DIR
CAB
CBA
SAB
SBA
A0 THRU A7
B0 THRU B7
X
X
X
X
X
Input Not
Specified
Not Specified
Input
Store A, B Unspecified
X
X
X
X
X
Input Not
Specified
Input
Store B, A Unspecified
H
X
X
X
Input
Input
Store A and B Data
H
X
H or L
H or L
X
X
Input
Input
Isolation, Hold Storage
L
L
X
X
X
L
Output
Input
Real-Time B Data to A Bus
L
L
X
H or L
X
H
Output
Input
Stored B Data to A Bus
L
H
X
X
L
X
Input
Output
Real-Time A Data to B Bus
L
H
H or L
X
H
X
Input
Output
Stored A Data to B Bus
P
N
CL
Q
O
FF
4
A0
PAD
P
N
CL
Q
O
FF
20
B0
PAD
22
SBA
PAD
2
SAB
PAD
23
CBA
PAD
1
CAB
PAD
21
OE
PAD
3
DIR
PAD
3
DIR
PAD
12
VSS
PAD
CHANNEL
0
1
2
3
4
5
6
7
PINS
4 - 20
5 - 19
6 - 18
7 - 17
8 - 16
9 - 15
10 - 14
11 - 13
TO CHANNELS
1 THROUGH 7
Spec Number
518628
708
Specifications HCTS646MS
Absolute Maximum Ratings
Reliability Information
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input
. . . . . . . . . . . . . . . . . . . . . . . .
10mA
DC Drain Current, Any One Output
. . . . . . . . . . . . . . . . . . . . . . .
25mA
(All Voltage Reference to the VSS Terminal)
Storage Temperature Range (TSTG) . . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265
o
C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance
JA
JC
SBDIP Package. . . . . . . . . . . . . . . . . . . .
65
o
C/W
25
o
C/W
Ceramic Flatpack Package . . . . . . . . . . .
89
o
C/W
24
o
C/W
Maximum Package Power Dissipation at +125
o
C Ambient
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.77W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.56W
If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.4mW/
o
C
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . 11.2mW/
o
C
CAUTION: As with all semiconductors, stress listed under "Absolute Maximum Ratings" may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under "Electrical Performance Characteristics" are the only conditions recommended for satisfactory device operation.
Operating Conditions
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Input Rise and Fall Times at 4.5V VCC (TR, TF) . . . . . . .500ns Max
Operating Temperature Range (T
A
) . . . . . . . . . . . . -55
o
C to +125
o
C
Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . . . . . . 0.0V to 0.8V
Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . . .VCC/2 to VCC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
(NOTE 1)
CONDITIONS
GROUP
A SUB-
GROUPS
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Quiescent Current
ICC
VCC = 5.5V,
VIN = VCC or GND
1
+25
o
C
-
40
A
2, 3
+125
o
C, -55
o
C
-
750
A
Output Current
(Sink)
IOL
VCC = 4.5V, VIH = 4.5V,
VOUT = 0.4V, VIL = 0V
1
+25
o
C
7.2
-
mA
2, 3
+125
o
C, -55
o
C
6.0
-
mA
Output Current
(Source)
IOH
VCC = 4.5V, VIH = 4.5V,
VOUT = VCC - 0.4V,
VIL = 0V
1
+25
o
C
-7.2
-
mA
2, 3
+125
o
C, -55
o
C
-6.0
-
mA
Output Voltage Low
VOL
VCC = 4.5V, VIH = 2.25V,
IOL = 50
A, VIL = 0.8V
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
-
0.1
V
VCC = 5.5V, VIH = 2.75V,
IOL = 50
A, VIL = 0.8V
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
-
0.1
V
Output Voltage High
VOH
VCC = 4.5V, VIH = 2.25V,
IOH = -50
A, VIL = 0.8V
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
VCC
-0.1
-
V
VCC = 5.5V, VIH = 2.75V,
IOH = -50
A, VIL = 0.8V
1, 2, 3
+25
o
C, +125
o
C, -55
o
C
VCC
-0.1
-
V
Input Leakage
Current
IIN
VCC = 5.5V, VIN = VCC or
GND
1
+25
o
C
-
0.5
A
2, 3
+125
o
C, -55
o
C
-
5.0
A
Three-State Output
Leakage Current
IOZ
Applied Voltage = 0V or
VCC, VCC = 5.5V
1
+25
o
C
-
1
A
2, 3
+125
o
C, -55
o
C
-
50
A
Noise Immunity
Functional Test
FN
VCC = 4.5V, VIH = 2.25V,
VIL = 0.8V (Note 2)
7, 8A, 8B
+25
o
C, +125
o
C, -55
o
C
-
-
-
NOTES:
1. All voltages referenced to device GND.
2. For functional tests, VO
4.0V is recognized as a logic "1", and VO
0.5V is recognized as a logic "0".
Spec Number
518628
709
Specifications HCTS646MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
(NOTES 1, 2)
CONDITIONS
GROUP
A SUB-
GROUPS
TEMPERATURE
LIMITS
UNITS
MIN
MAX
A Data to B Bus
(Store)
TPLH,
TPHL
VCC = 4.5V
9
+25
o
C
2
31
ns
10, 11
+125
o
C, -55
o
C
2
36
ns
B Data to A Bus
(Store)
TPLH,
TPHL
VCC = 4.5V
9
+25
o
C
2
32
ns
10, 11
+125
o
C, -55
o
C
2
37
ns
A Data to B Bus
TPLH,
TPHL
VCC = 4.5V
9
+25
o
C
2
24
ns
10, 11
+125
o
C, -55
o
C
2
27
ns
B Data to A Bus
TPLH,
TPHL
VCC = 4.5V
9
+25
o
C
2
24
ns
10, 11
+125
o
C, -55
o
C
2
27
ns
Select to Data
TPLH,
TPHL
VCC = 4.5V
9
+25
o
C
2
30
ns
10, 11
+125
o
C, -55
o
C
2
34
ns
DIR to Output
TPLZ,
TPHZ
VCC = 4.5V
9
+25
o
C
2
28
ns
10, 11
+125
o
C, -55
o
C
2
31
ns
Enable to Output
TPLZ,
TPHZ
VCC = 4.5V
9
+25
o
C
2
28
ns
10, 11
+125
o
C, -55
o
C
2
31
ns
DIR to Output
TPZL,
TPZH
VCC = 4.5V
9
+25
o
C
2
28
ns
10, 11
+125
o
C, -55
o
C
2
34
ns
Enable to Output
TPZL,
TPZH
VCC = 4.5V
9
+25
o
C
2
30
ns
10, 11
+125
o
C, -55
o
C
2
36
ns
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500
, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Capacitance Power
Dissipation
CPD
VCC = 5.0V, f = 1MHz
1
+25
o
C
-
54
pF
1
+125
o
C, -55
o
C
-
123
pF
Input Capacitance
CIN
VCC = 5.0V, f = 1MHz
1
+25
o
C
-
10
pF
1
+125
o
C
-
10
pF
Output Transition
Time
TTHL,
TTLH
VCC = 4.5V
1
+25
o
C
-
12
ns
1
+125
o
C, -55
o
C
-
18
ns
Max Operating
Frequency
FMAX
VCC = 4.5V
1
+25
o
C
-
25
MHz
1
+125
o
C, -55
o
C
-
17
MHz
Setup Time Data to
Clock
TSU
VCC = 4.5V
1
+25
o
C
12
-
ns
1
+125
o
C, -55
o
C
18
-
ns
Hold Time Data to
Clock
TH
VCC = 4.5V
1
+25
o
C
5
-
ns
1
+125
o
C, -55
o
C
5
-
ns
Pulse Width Clocks
TW
VCC = 4.5V
1
+25
o
C
25
-
ns
1
+125
o
C, -55
o
C
38
-
ns
NOTE:
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
Spec Number
518628
710
Specifications HCTS646MS
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
(NOTES 1, 2)
CONDITIONS
TEMPERATURE
200K RAD
LIMITS
UNITS
MIN
MAX
Quiescent Current
ICC
VCC = 5.5V, VIN = VCC or GND
+25
o
C
-
0.75
mA
Output Current (Sink)
IOL
VCC = 4.5V, VIN = VCC or GND,
VOUT = 0.4V
+25
o
C
6.0
-
mA
Output Current
(Source)
IOH
VCC = 4.5V, VIN = VCC or GND,
VOUT = VCC -0.4V
+25
o
C
-6.0
-
mA
Output Voltage Low
VOL
VCC = 4.5V or 5.5V, VIH = VCC/2,
VIL = 0.8V, IOL = 50
A
+25
o
C
-
0.1
V
Output Voltage High
VOH
VCC = 4.5V or 5.5V, VIH = VCC/2,
VIL = 0.8V, IOH = -50
A
+25
o
C
VCC
-0.1
-
V
Input Leakage
Current
IIN
VCC = 5.5V, VIN = VCC or GND
+25
o
C
-
5
A
Three-State Output
Leakage Current
IOZ
Applied Voltage = 0V or VCC, VCC = 5.5V
+25
o
C
-
50
A
Noise Immunity
Functional Test
FN
VCC = 4.5V, VIH = 2.25V,
VIL = 0.8V, (Note 3)
+25
o
C
-
-
-
A Data to B Bus (Store)
TPLH,
TPHL
VCC = 4.5V
+25
o
C
2
36
ns
B Data to A Bus (Store)
TPLH,
TPHL
VCC = 4.5V
+25
o
C
2
37
ns
A Data to B Bus
TPLH,
TPHL
VCC = 4.5V
+25
o
C
2
27
ns
B Data to A Bus
TPLH,
TPHL
VCC = 4.5V
+25
o
C
2
27
ns
Select to Data
TPLH,
TPHL
VCC = 4.5V
+25
o
C
2
34
ns
DIR to Output
TPLZ,
TPHZ
VCC = 4.5V
+25
o
C
2
31
ns
Enable to Output
TPLZ,
TPHZ
VCC = 4.5V
+25
o
C
2
31
ns
DIR to Output
TPZL,
TPZH
VCC = 4.5V
+25
o
C
2
34
ns
Enable to Output
TPZL,
TPZH
VCC = 4.5V
+25
o
C
2
36
ns
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500
, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V.
3. For functional tests VO
4.0V is recognized as a logic "1", and VO
0.5V is recognized as a logic "0".
TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25
o
C)
PARAMETER
GROUP B
SUBGROUP
DELTA LIMIT
ICC
5
12
A
IOL/IOH
5
-15% of 0 Hour
IOZL/IOZH
5
200nA
Spec Number
518628