5-1

March 1997

HD-6409

CMOS Manchester Encoder-Decoder

Features

· Converter or Repeater Mode

· Independent Manchester Encoder and Decoder

Operation

· Static to One Megabit/sec Data Rate Guaranteed

· Low Bit Error Rate

· Digital PLL Clock Recovery

· On Chip Oscillator

· Low Operating Power: 50mW Typical at +5V

· Available in 20 Lead Dual-In-Line and 20 Pad LCC

Package

Description

The HD-6409 Manchester Encoder-Decoder (MED) is a high
speed, low power device manufactured using self-aligned sil-
icon gate technology. The device is intended for use in serial
data communication, and can be operated in either of two
modes. In the converter mode, the MED converts Non
return-to-Zero code (NRZ) into Manchester code and
decodes Manchester code into Nonreturn-to-Zero code. For
serial data communication, Manchester code does not have
some of the deficiencies inherent in Nonreturn-to-Zero code.
For instance, use of the MED on a serial line eliminates DC
components, provides clock recovery, and gives a relatively
high degree of noise immunity. Because the MED converts
the most commonly used code (NRZ) to Manchester code,
the advantages of using Manchester code are easily realized
in a serial data link.

In the Repeater mode, the MED accepts Manchester code
input and reconstructs it with a recovered clock. This mini-
mizes the effects of noise on a serial data link. A digital
phase lock loop generates the recovered clock. A maximum
data rate of 1MHz requires only 50mW of power.

Manchester code is used in magnetic tape recording and in
fiber optic communication, and generally is used where data
accuracy is imperative. Because it frames blocks of data, the
HD-6409 easily interfaces to protocol controllers.

Pinouts

HD-6409 (CERDIP, PDIP, SOIC)

TOP VIEW

HD-6409 (CLCC)

TOP VIEW

Ordering Information

PACKAGE

TEMPERATURE

RANGE

1 MEGABIT/SEC

PKG.

NO.

PDIP

-40

C to +85

HD3-6409-9

E20.3

SOIC

-40

C to +85

HD9P6409-9

M20.3

CERDIP

-40

C to +85

HD1-6409-9

F20.3

DESC

-55

C to 125

5962-9088801MRA

F20.3

CLCC

-40

C to +85

HD4-6409-9

J20.A

DESC

-55

C to 125

5962-9088801M2A

J20.A

BZI

BOI

UDI

SD/CDS

SDO

SRST

DCLK

NVM

RST

GND

BZO

ECLK

BOO

CTS

SD/CDS

SDO

SRST

NVM

DCLK

UDI

BOI

BZI

BOO

RST

GND

BZO

ECLK

CTS

File Number

2951.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207

Intersil Corporation 1999

5-3

Pin Description

PIN

NUMBER

TYPE

SYMBOL

NAME

DESCRIPTION

BZl

Bipolar Zero Input

Used in conjunction with pin 2, Bipolar One Input (BOl), to input Manchester II
encoded data to the decoder, BZI and BOl are logical complements. When using
pin 3, Unipolar Data Input (UDI) for data input, BZI must be held high.

BOl

Bipolar One Input

Used in conjunction with pin 1, Bipolar Zero Input (BZI), to input Manchester II
encoded data to the decoder, BOI and BZI are logical complements. When using
pin 3, Unipolar Data Input (UDI) for data input, BOl must be held low.

UDI

Unipolar Data Input

An alternate to bipolar input (BZl, BOl), Unipolar Data Input (UDl) is used to input
Manchester II encoded data to the decoder. When using pin 1 (BZl) and pin 2
(BOl) for data input, UDI must be held low.

I/O

SD/CDS

Serial Data/Com-
mand Data Sync

In the converter mode, SD/CDS is an input used to receive serial NRZ data. NRZ
data is accepted synchronously on the falling edge of encoder clock output
(ECLK). In the repeater mode, SD/CDS is an output indicating the status of last
valid sync pattern received. A high indicates a command sync and a low indicates
a data sync pattern.

SDO

Serial Data Out

The decoded serial NRZ data is transmitted out synchronously with the decoder
clock (DCLK). SDO is forced low when RST is low.

SRST

Serial Reset

In the converter mode, SRST follows RST. In the repeater mode, when RST goes
low, SRST goes low and remains low after RST goes high. SRST goes high only
when RST is high, the reset bit is zero, and a valid synchronization sequence is
received.

NVM

Nonvalid Manchester

A low on NVM indicates that the decoder has received invalid Manchester data
and present data on Serial Data Out (SDO) is invalid. A high indicates that the
sync pulse and data were valid and SDO is valid. NVM is set low by a low on RST,
and remains low after RST goes high until valid sync pulse followed by two valid
Manchester bits is received.

DCLK

Decoder Clock

The decoder clock is a 1X clock recovered from BZl and BOl, or UDI to synchro-
nously output received NRZ data (SDO).

RST

Reset

In the converter mode, a low on RST forces SDO, DCLK, NVM, and SRST low.
A high on RST enables SDO and DCLK, and forces SRST high. NVM remains
low after RST goes high until a valid sync pulse followed by two Manchester bits
is received, after which it goes high. In the repeater mode, RST has the same ef-
fect on SDO, DCLK and NVM as in the converter mode. When RST goes low,
SRST goes low and remains low after RST goes high. SRST goes high only
when RST is high, the reset bit is zero and a valid synchronization sequence is
received.

GND

Ground

Clock Output

Buffered output of clock input I

. May be used as clock signal for other peripherals.

Clock Input

is the input for an external clock or, if the internal oscillator is used, I

and O

are used for the connection of the crystal.

Clock Drive

If the internal oscillator is used, O

and I

are used for the connection of the crys-

tal.

Mode Select

MS must be held low for operation in the converter mode, and high for operation
in the repeater mode.

CTS

Clear to Send

In the converter mode, a high disables the encoder, forcing outputs BOO, BZO high

and ECLK low. A high to low transition of CTS initiates transmission of a Command
sync pulse. A low on CTS enables BOO, BZO, and ECLK. In the repeater mode,
the function of CTS is identical to that of the converter mode with the exception that
a transition of CTS does not initiate a synchronization sequence.

ECLK

Encoder Clock

In the converter mode, ECLK is a 1X clock output used to receive serial NRZ data
to SD/CDS. In the repeater mode, ECLK is a 2X clock which is recovered from
BZl and BOl data by the digital phase locked loop.

HD-6409

5-4

Encoder Operation

The encoder uses free running clocks at 1X and 2X the data
rate derived from the system clock l

for internal timing. CTS

is used to control the encoder outputs, ECLK, BOO and
BZO. A free running 1X ECLK is transmitted out of the
encoder to drive the external circuits which supply the NRZ
data to the MED at pin SD/CDS.

A low on CTS enables encoder outputs ECLK, BOO and
BZO, while a high on CTS forces BZO, BOO high and holds
ECLK low. When CTS goes from high to low

, a synchro-

nization sequence is transmitted out on BOO and BZO. A
synchronization sequence consists of eight Manchester "0"

bits followed by a command sync pulse.

A command

sync pulse is a 3-bit wide pulse with the first 1 1/2 bits high
followed by 1 1/2 bits low.

Serial NRZ data is clocked into

the encoder at SD/CDS on the high to low transition of ECLK
during the command sync pulse. The NRZ data received is
encoded into Manchester II data and transmitted out on
BOO and BZO following the command sync pulse.

Fol-

lowing the synchronization sequence, input data is encoded
and transmitted out continuously without parity check or
word framing. The length of the data block encoded is
defined by CTS. Manchester data out is inverted.

Decoder Operation

The decoder requires a single clock with a frequency 16X or
32X the desired data rate. The rate is selected on the speed
select with SS low producing a 16X clock and high a 32X
clock. For long data links the 32X mode should be used as
this permits a wider timing jitter margin. The internal opera-
tion of the decoder utilizes a free running clock synchronized
with incoming data for its clocking.

The Manchester II encoded data can be presented to the
decoder in either of two ways. The Bipolar One and Bipolar

Zero inputs will accept data from differential inputs such as a
comparator sensed transformer coupled bus. The Unipolar
Data input can only accept noninverted Manchester II
encoded data i.e. Bipolar One Out through an inverter to
Unipolar Data Input. The decoder continuously monitors this
data input for valid sync pattern. Note that while the MED
encoder section can generate only a command sync pattern,
the decoder can recognize either a command or data sync
pattern. A data sync is a logically inverted command sync.

Speed Select

A logic high on SS sets the data rate at 1/32 times the clock frequency while a
low sets the data rate at 1/16 times the clock frequency.

BZO

Bipolar Zero Output

BZO and its logical complement BOO are the Manchester data outputs of the en-
coder. The inactive state for these outputs is in the high state.

BOO

Bipolar One Out

See pin 18.

is the +5V power supply pin. A 0.1

F decoupling capacitor from V

(pin-

20) to GND (pin-10) is recommended.

NOTE: (I) Input

(O) Output

Pin Description

PIN

NUMBER

TYPE

SYMBOL

NAME

DESCRIPTION

CTS

ECLK

SD/CDS

BZO

BOO

CE6

CE5

SYNCHRONIZATION SEQUENCE

EIGHT "0's"

COMMAND

SYNC

DON'T CARE

`1'

`0'

`1'

`0' `1'

FIGURE 1. ENCODER OPERATION

HD-6409

5-5

There is a three bit delay between UDI, BOl, or BZI input and
the decoded NRZ data transmitted out of SDO.

Control of the decoder outputs is provided by the RST pin.
When RST is low, SDO, DCLK and NVM are forced low.
When RST is high, SDO is transmitted out synchronously
with the recovered clock DCLK. The NVM output remains
low after a low to high transition on RST until a valid sync
pattern is received.

The decoded data at SDO is in NRZ format. DCLK is pro-
vided so that the decoded bits can be shifted into an external
register on every high to low transition of this clock. Three bit
periods after an invalid Manchester bit is received on UDI, or
BOl, NVM goes low synchronously with the questionable
data output on SDO. FURTHER, THE DECODER DOES
NOT REESTABLISH PROPER DATA DECODING UNTIL
ANOTHER SYNC PATTERN IS RECOGNIZED.

Repeater Operation

Manchester Il data can be presented to the repeater in either
of two ways. The inputs Bipolar One In and Bipolar Zero In
will accept data from differential inputs such as a comparator
or sensed transformer coupled bus. The input Unipolar Data
In accepts only noninverted Manchester II coded data. The
decoder requires a single clock with a frequency 16X or 32X
the desired data rate. This clock is selected to 16X with
Speed Select low and 32X with Speed Select high. For long
data links the 32X mode should be used as this permits a
wider timing jitter margin.

The inputs UDl, or BOl, BZl are delayed approximately 1/2
bit period and repeated as outputs BOO and BZO. The 2X
ECLK is transmitted out of the repeater synchronously with
BOO and BZO.

A low on CTS enables ECLK, BOO, and BZO. In contrast to
the converter mode, a transition on CTS does not initiate a
synchronization sequence of eight 0's and a command sync.
The repeater mode does recognize a command or data sync
pulse. SD/CDS is an output which reflects the state of the
most recent sync pulse received, with high indicating a com-
mand sync and low indicating a data sync.

When RST is low, the outputs SDO, DCLK, and NVM are
low, and SRST is set low. SRST remains low after RST goes
high and is not reset until a sync pulse and two valid
manchester bits are received with the reset bit low. The reset
bit is the first data bit after the sync pulse. With RST high,
NRZ Data is transmitted out of Serial Data Out synchro-
nously with the 1X DCLK.

FIGURE 2. DECODER OPERATION

DCLK

UDI

SDO

RST

NVM

COMMAND

SYNC

FIGURE 3. REPEATER OPERATION

INPUT

COUNT

ECLK

UDI

BZO

BOO

RST

SRST

SYNC PULSE

HD-6409

5-6

Manchester Code

Nonreturn-to-Zero (NRZ) code represents the binary values
logic-O and Iogic-1 with a static level maintained throughout
the data cell. In contrast, Manchester code represents data
with a level transition in the middle of the data cell. Manches-
ter has bandwidth, error detection, and synchronization
advantages over NRZ code.

The Manchester II code Bipolar One and Bipolar Zero shown
below are logical complements. The direction of the transi-
tion indicates the binary value of data. A logic-0 in Bipolar
One is defined as a Low to high transition in the middle of
the data cell, and a logic-1 as a high to low mid bit transition,
Manchester Il is also known as Biphase-L code.

The bandwidth of NRZ is from DC to the clock frequency fc/2,
while that of Manchester is from fc/2 to fc. Thus, Manchester
can be AC or transformer coupled, which has considerable
advantages over DC coupling. Also, the ratio of maximum to
minimum frequency of Manchester extends one octave, while
the ratio for NRZ is the range of 5-10 octaves. It is much eas-
ier to design a narrow band than a wideband amp.

Secondly, the mid bit transition in each data cell provides the
code with an effective error detection scheme. If noise pro-
duces a logic inversion in the data cell such that there is no
transition, an error indiction is given, and synchronization
must be re-established. This places relatively stringent
requirements on the incoming data.

The synchronization advantages of using the HD-6409 and
Manchester code are several fold. One is that Manchester is
a self clocking code. The clock in serial data communication
defines the position of each data cell. Non self clocking
codes, as NRZ, often require an extra clock wire or clock
track (in magnetic recording). Further, there can be a phase
variation between the clock and data track. Crosstalk
between the two may be a problem. In Manchester, the
serial data stream contains both the clock and the data, with
the position of the mid bit transition representing the clock,
and the direction of the transition representing data. There is
no phase variation between the clock and the data.

A second synchronization advantage is a result of the num-
ber of transitions in the data. The decoder resynchronizes on
each transition, or at least once every data cell. In contrast,
receivers using NRZ, which does not necessarily have tran-
sitions, must resynchronize on frame bit transitions, which
occur far less often, usually on a character basis. This more
frequent resynchronization eliminates the cumulative effect
of errors over successive data cells. A final synchronization
advantage concerns the HD-6409's sync pulse used to ini-
tiate synchronization. This three bit wide pattern is suffi-
ciently distinct from Manchester data that a false start by the
receiver is unlikely.

Crystal Oscillator Mode

FIGURE 5. CRYSTAL OSCILLATOR MODE

LC Oscillator Mode

FIGURE 6. LC OSCILLATOR MODE

FIGURE 4. MANCHESTER CODE

BIT PERIOD

BINARY CODE

NONRETURN

TO ZERO

BIPOLAR ONE

BIPOLAR ZERO

16MHz

C1 = 32pF
C0 = CRYSTAL + STRAY
X1 = AT CUT PARALLEL

RESONANCE
FUNDAMENTAL
MODE

(TYP) = 30

R1 = 15M

2C0

--------------------------

-----------------------

C1 = 20pF
C0 = 5pF

HD-6409

5-8

Absolute Maximum Ratings

Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.5V to V

+0.5V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Thermal Resistance (Typical)

CERDIP . . . . . . . . . . . . . . . . . . . . . . . . . .

C/W

CLCC Package . . . . . . . . . . . . . . . . . . . .

C/W

PDIP Package . . . . . . . . . . . . . . . . . . . . .

C/W

N/A

SOIC Package . . . . . . . . . . . . . . . . . . . . .

100

C/W

N/A

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65

C to +150

Maximum Junction Temperature

Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175

Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300

(

Lead Tips Only for Surface Mount Packages)

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Gates

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions

Operating Temperature Range . . . . . . . . . . . . . . . . . -40

C to +85

Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . .50ns Max

Sync. Transition Span (t2) . . . . . . . . . . 1.5 DBP Typical, (Notes 1, 2)
Short Data Transition Span (t4). . . . . . .0.5DBP Typical, (Notes 1, 2)
Long Data Transition Span (t5) . . . . . . .1.0DBP Typical, (Notes 1, 2)
Zero Crossing Tolerance (tCD5) . . . . . . . . . . . . . . . . . . . . . .(Note 3)

NOTES:

1. DBP-Data Bit Period, Clock Rate = 16X, one DBP = 16 Clock Cycles; Clock Rate = 32X, one DBP = 32 Clock Cycles.

2. The input conditions specified are nominal values, the actual input waveforms transition spans may vary by

2 I

clock cycles (16X mode)

6 I

clock cycles (32X mode).

3. The maximum zero crossing tolerance is

2 I

clock cycles (16X mode) or

6 I

clock cycles (32 mode) from the nominal.

DC Electrical Specifications

= 5.0V

10%, T

= -40

C to +85

(HD-6409-9)

SYMBOL

PARAMETER

MIN

MAX

UNITS

(NOTE 1) TEST CONDITIONS

Logical "1" Input Voltage

70% V

= 4.5V

Logical "0" Input Voltage

20% V

= 4.5V

IHR

Logic "1" Input Voltage (Reset)

-0.5

= 5.5V

ILR

Logic "0" Input Voltage (Reset)

GND +0.5

= 4.5V

IHC

Logical "1" Input Voltage (Clock)

-0.5

= 5.5V

ILC

Logical "0" Input Voltage (Clock)

GND +0.5

= 4.5V

Input Leakage Current (Except I

)

-1.0

+1.0

= V

or GND, V

= 5.5V

Input Leakage Current (I

)

-20

+20

= V

or GND, V

= 5.5V

I/O Leakage Current

-10

+10

OUT

= V

or GND, V

= 5.5V

Output HIGH Voltage (All Except O

)

-0.4

= -2.0mA, V

= 4.5V (Note 2)

Output LOW Voltage (All Except O

)

0.4

= +2.0mA, V

= 4.5V (Note 2)

CCSB

Standby Power Supply Current

100

= V

or GND, V

= 5.5V,

Outputs Open

CCOP

Operating Power Supply Current

18.0

f = 16.0MHz, V

= V

or GND

= 5.5V, C

= 50pF

Functional Test

(Note 1)

NOTES:

1. Tested as follows: f = 16MHz, V

= 70% V

, V

= 20% V

, V

/2, and V

/2, V

= 4.5V and 5.5V.

2. Interchanging of force and sense conditions is permitted

Capacitance

= +25

C, Frequency = 1MHz

SYMBOL

PARAMETER

TYP

UNITS

TEST CONDITIONS

Input Capacitance

All measurements are referenced to device GND

OUT

Output Capacitance

HD-6409

5-9

AC Electrical Specifications

= 5.0V

10%, T

= -40

C to +85

C (HD-6409-9)

SYMBOL

PARAMETER

MIN

MAX

UNITS

(NOTE 1) TEST CONDITIONS

Clock Frequency

MHz

Clock Period

1/f

sec

Bipolar Pulse Width

+10

One-Zero Overlap

-10

Clock High Time

f = 16.0MHz

Clock Low Time

f = 16.0MHz

CE1

Serial Data Setup Time

120

CE2

Serial Data Hold Time

CD2

DCLK to SDO, NVM

ECLK to BZO

Output Rise Time (All except Clock)

From 1.0V to 3.5V, C

= 50pF, Note 2

Output Fall Time (All except Clock)

From 3.5V to 1.0V, C

= 50pF, Note 2

Clock Output Rise Time

From 1.0V to 3.5V, C

= 20pF, Note 2

Clock Output Fall Time

From 3.5V to 1.0V, C

= 20pF, Note 2

CE3

ECLK to BZO, BOO

0.5

1.0

DBP

Notes 2, 3

CE4

CTS Low to BZO, BOO Enabled

0.5

1.5

DBP

Notes 2, 3

CE5

CTS Low to ECLK Enabled

10.5

11.5

DBP

Notes 2, 3

CE6

CTS High to ECLK Disabled

1.0

DBP

Notes 2, 3

CE7

CTS High to BZO, BOO Disabled

1.5

2.5

DBP

Notes 2, 3

CD1

UDI to SDO, NVM

2.5

3.0

DBP

Notes 2, 3

CD3

RST Low to CDLK, SDO, NVM Low

0.5

1.5

DBP

Notes 2, 3

CD4

RST High to DCLK, Enabled

0.5

1.5

DBP

Notes 2, 3

UDI to BZO, BOO

0.5

1.0

DBP

Notes 2, 3

UDI to SDO, NVM

2.5

3.0

DBP

Notes 2, 3

NOTES:

1. AC testing as follows: f = 4.0MHz, V

= 70% V

, V

= 20% V

, Speed Select = 16X, V

/2, V

= 4.5V and

5.5V. Input rise and fall times driven at 1ns/V, Output load = 50pF.

2. Guaranteed via characteristics at initial device design and after major process and/or design changes, not tested.

3. DBP-Data Bit Period, Clock Rate = 16X, one DBP = 16 Clock Cycles; Clock Rate = 32X, one DBP = 32 Clock Cycles.

HD-6409

5-11

FIGURE 11. ENCODER TIMING

FIGURE 12. ENCODER TIMING

FIGURE 13. ENCODER TIMING

NOTE: Manchester Data-In is not synchronous with Decoder Clock.

Decoder Clock is synchronous with decoded NRZ out of SDO.

FIGURE 14. DECODER TIMING

FIGURE 15. DECODER TIMING

FIGURE 16. DECODER TIMING

Timing Waveforms

(Continued)

ECLK

SD/CDS

BZO

BOO

CE1

CE2

CE3

CE5

CE4

CTS

BZO

BOO

ECLK

CE6

CTS

BZO

BOO

ECLK

CE7

DCLK

UDI

SDO

NVM

MANCHESTER

LOGIC-1

MANCHESTER

LOGIC-0

MANCHESTER

LOGIC-0

MANCHESTER

LOGIC-1

CD2

CD5

CD2

CD1

NRZ

LOGIC-1

RST

DCLK, SDO,

NVM

50%

CD3

RST

DCLK

50%

CD4

HD-6409

5-12

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

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Test Load Circuit

FIGURE 17. REPEATER TIMING

Timing Waveforms

(Continued)

UDI

ECLK

BZO

SDO

NVM

MANCHESTER `1'

MANCHESTER `0'

MANCHESTER `1'

MANCHESTER `0'

FIGURE 18. TEST LOAD CIRCUIT

DUT

(NOTE)

NOTE: INCLUDES STRAY AND JIG

CAPACITANCE

HD-6409

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