File Number

4270.2

HIP6002

Rectifier (PWM) Controller and Output
Voltage Monitor

The HIP6002 provides complete control and protection for a
DC-DC converter optimized for high-performance
microprocessor applications. It is designed to drive two
N-Channel MOSFETs in a synchronous-rectified buck
topology. The HIP6002 integrates all of the control, output
adjustment, monitoring and protection functions into a single
package.

The output voltage of the converter is easily adjusted and
precisely regulated. The HIP6002 includes a 4-Input
Digital-to-Analog Converter (DAC) that adjusts the output
voltage from 2.0VDC to 3.5VDC in 0.1V increments. The
precision reference and voltage-mode regulator hold the
selected output voltage to within

1% over temperature and

line voltage variations.

The HIP6002 provides simple, single feedback loop, voltage-
mode control with fast transient response. It includes a
200kHz free-running triangle-wave oscillator that is
adjustable from below 50kHz to over 1MHz. The error
amplifier features a 15MHz gain-bandwidth product and
6V/

s slew rate which enables high converter bandwidth for

fast transient performance. The resulting PWM duty ratio
ranges from 0% to 100%.

The HIP6002 monitors the output voltage with a window
comparator that tracks the DAC output and issues a Power
Good signal when the output is within

10%. The HIP6002

protects against over-current conditions by inhibiting PWM
operation. Built-in over-voltage protection triggers an
external SCR to crowbar the input supply. The HIP6002
monitors the current by using the r

DS(ON)

of the upper

MOSFET which eliminates the need for a current sensing
resistor.

Pinout

HIP6002 (SOIC)

TOP VIEW

Features

· Drives Two N-Channel MOSFETs

· Operates From +5V or +12V Input

· Simple Single-Loop Control Design

- Voltage-Mode PWM Control

· Fast Transient Response

- High-Bandwidth Error Amplifier

- Full 0% to 100% Duty Ratio

· Excellent Output Voltage Regulation

1% Over Line Voltage and Temperature

· 4-Bit Digital-to-Analog Output Voltage Selection

- Wide Range . . . . . . . . . . . . . . . . . . .2.0VDC to 3.5VDC

- 0.1V Binary Steps

· Power-Good Output Voltage Monitor

· Over-Voltage and Over-Current Fault Monitors

- Does Not Require Extra Current Sensing Element

- Uses MOSFET's r

DS(ON)

· Small Converter Size

- Constant Frequency Operation

- 200kHz Free-Running Oscillator Programmable from

50kHz to Over 1MHz

Applications

· Power Supply for Pentium®, Pentium Pro, PowerPCTM and

AlphaTM Microprocessors

· High-Power 5V to 3.xV DC-DC Regulators

· Low-Voltage Distributed Power Supplies

Alpha MicroTM is a trademark of Digital Computer Equipment Corporation.

Pentium® is a registered trademark of Intel Corporation.

PowerPCTM is a registered trademark of IBM.

VSEN

OCSET

VID0

VID1

VID2

VID3

COMP

VCC

LGATE

PGND

OVP

BOOT

UGATE

PHASE

PGOOD

GND

Ordering Information

PART NUMBER

TEMP.

RANGE (

PACKAGE

PKG.

NO.

HIP6002CB

0 to 70

20 Ld SOIC

M20.3

Data Sheet

March 2000

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

Intersil Corporation 2000

Absolute Maximum Ratings

Thermal Information

Supply Voltage V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15V

Boot Voltage, V

BOOT

- V

PHASE

. . . . . . . . . . . . . . . . . . . . . . . . +15V

Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to V

+ 0.3V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2

Operating Conditions

Supply Voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . +12V to

10%

Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . 0

to 70

Junction Temperature Range . . . . . . . . . . . . . . . . . . . 0

C to 125

Thermal Resistance (Typical, Note 1)

(

C/W)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

115

Maximum Junction Temperature (Plastic Package) . . . . . . . 150

Maximum Storage Temperature Range . . . . . . . . . . -65

C to 150

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief 379 for details.

Electrical Specifications

Recommended Operating Conditions, unless otherwise noted

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

VCC SUPPLY CURRENT

Nominal Supply

EN = V

; UGATE and LGATE Open

Shutdown Supply

EN = 0V

100

POWER-ON RESET

Rising V

Threshold

OCSET

= 4.5V

10.4

Falling V

Threshold

OCSET

= 4.5V

8.2

Enable - Input threshold Voltage

OCSET

= 4.5V

0.8

2.0

Rising V

OCSET

Threshold

1.26

OSCILLATOR

Free Running Frequency

= OPEN

185

200

215

kHz

Programmable Variation

< R

to GND < 200k

-15

+15

Ramp Amplitude

OSC

= OPEN

1.9

P-P

REFERENCE AND DAC

DACOUT Voltage Accuracy

-1.0

+1.0

ERROR AMPLIFIER

DC Gain

Gain-Bandwidth Product

GBW

MHz

Slew Rate

COMP = 10pF

GATE DRIVERS

Upper Gate Source

UGATE

BOOT

- V

PHASE

= 12V, V

UGATE

= 6V

350

500

Upper Gate Sink

UGATE

LGATE

= 0.3A

5.5

Lower Gate Source

LGATE

= 12V, V

LGATE

= 6V

300

450

Lower Gate Sink

LGATE

= 0.3A

3.5

6.5

PROTECTION

Over-Voltage Trip

% Over Nominal DACOUT Voltage

115

120

OCSET Current Source

OCSET

= 4.5V

170

200

230

OVP Sourcing Current

OVP

SEN

= 5.5V, V

OVP

= 0V

Soft Start Current

POWER GOOD

Upper Threshold (V

SEN

/DACOUT)

SEN

Rising

106

111

Lower Threshold (V

SEN

/DACOUT)

SEN

Falling

Hysteresis (V

SEN

/DACOUT)

Upper and Lower Threshold

PGOOD Voltage Low

PGOOD

= -5mA

0.5

HIP6002

Functional Pin Description

VSEN (Pin 1)

This pin is connected to the converters output voltage. The
PGOOD and OVP comparator circuits use this signal to
report output voltage status and for overvoltage protection.

OCSET (Pin 2)

Connect a resistor (R

OCSET

) from this pin to the drain of the

upper MOSFET. R

OCSET

, an internal 200

A current source

OCS

), and the upper MOSFET on-resistance (r

DS(ON)

) set

the converter over-current (OC) trip point according to the
following equation:

An over-current trip cycles the soft-start function.

SS (Pin 3)

Connect a capacitor from this pin to ground. This capacitor,
along with an internal 10

A current source, sets the soft-

start interval of the converter.

VID0-3 (Pins 4-7)

VID0-3 are the input pins to the 4-bit DAC. The states of
these four pins program the internal voltage reference
(DACOUT). The level of DACOUT sets the converter output
voltage. It also sets the PGOOD and OVP thresholds. Table
1 specifies DACOUT for the 16 combinations of DAC inputs.

EN (Pin 8)

This pin is the open-collector enable pin. Pull this pin below
1V to disable the converter. In shutdown, the soft start pin is
discharged and the UGATE pin is held low.

COMP (Pin 9) and FB (Pin 10)

COMP and FB are the available external pins of the error
amplifier. The FB pin is the inverting input of the error
amplifier and the COMP pin is the error amplifier output.
These pins are used to compensate the voltage-control
feedback loop of the converter.

GND (Pin 11)

Signal ground for the IC. All voltage levels are measured with
respect to this pin.

PGOOD (Pin 12)

PGOOD is an open collector output used to indicate the
status of the converter output voltage. This pin is pulled low
when the converter output is not within

of the

DACOUT reference voltage.

PHASE (Pin 13)

Connect the PHASE pin to the upper MOSFET source. This
input pin is used to monitor the voltage drop across the
MOSFET for over-current protection. This pin also provide
the return path for the upper gate drive.

UGATE (Pin 14)

Connect UGATE to the upper MOSFET gate. This pin
provides the gate drive for the upper MOSFET.

Typical Performance Curves

FIGURE 1. R

RESISTANCE vs FREQUENCY

FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY

100

1000

SWITCHING FREQUENCY (kHz)

RESIST

ANCE (k

)

100

1000

PULLUP

TO +12V

PULLDOWN

TO V

100

200

300

400

500

600

700

800

900

1000

(mA)

SWITCHING FREQUENCY (kHz)

GATE

= 3300pF

GATE

= 1000pF

GATE

= 10pF

UPPER

= C

LOWER

= C

GATE

VSEN

OCSET

VID0

VID1

VID2

VID3

COMP

VCC

LGATE

PGND

OVP

BOOT

UGATE

PHASE

PGOOD

GND

PEAK

OCS

OCSET

DS ON

(

)

--------------------------------------------

HIP6002

BOOT (Pin 15)

This pin provides bias voltage to the upper MOSFET driver.
A bootstrap circuit may be used to create a BOOT voltage
suitable to drive a standard N-Channel MOSFET.

PGND (Pin 16)

This is the power ground connection. Tie the lower MOSFET
source to this pin.

LGATE (Pin 17)

Connect LGATE to the lower MOSFET gate. This pin
provides the gate drive for the lower MOSFET.

VCC (Pin 18)

Provide a 12V bias supply for the chip to this pin.

OVP (Pin 19)

The OVP pin can be used to drive an external SCR in the
event of an overvoltage condition.

RT (Pin 20)

This pin provides oscillator switching frequency adjustment.
By placing a resistor (R

) from this pin to GND, the nominal

200kHz switching frequency is increased according to the
following equation:

Conversely, connecting a pull-up resistor (R

) from this pin

to V

reduces the switching frequency according to the

following equation:

Functional Description

Initialization

The HIP6002 automatically initializes upon receipt of power.
Special sequencing of the input supplies is not necessary.
The Power-On Reset (POR) function continually monitors
the input supply voltages and the enable (EN) pin. The POR
monitors the bias voltage at the VCC pin and the input
voltage (V

) on the OCSET pin. The level on OCSET is

equal to V

less a fixed voltage drop (see over-current

protection). With the EN pin held to V

, the POR function

initiates soft start operation after both input supply voltages
exceed their POR thresholds. For operation with a single
+12V power source, V

and V

are equivalent and the

+12V power source must exceed the rising V

threshold

before POR initiates operation.

The Power-On Reset (POR) function inhibits operation with
the chip disabled (EN pin low). With both input supplies
above their POR thresholds, transitioning the EN pin high
initiates a soft start interval.

Soft Start

The POR function initiates the soft start sequence. An
internal 10

A current source charges an external capacitor

) on the SS pin to 4V. Soft start clamps the error

amplifier output (COMP pin) and reference input (+
terminal of error amp) to the SS pin voltage. Figure 3
shows the soft start interval with C

= 0.1

F. Initially the

clamp on the error amplifier (COMP pin) controls the
converter's output voltage. At t1 in Figure 3, the SS voltage
reaches the valley of the oscillator's triangle wave. The
oscillator's triangular waveform is compared to the ramping
error amplifier voltage. This generates PHASE pulses of
increasing width that charge the output capacitor(s). This
interval of increasing pulse width continues to t2 . With
sufficient output voltage, the clamp on the reference input
controls the output voltage. This is the interval between t2
and t3 in Figure 3. At t3 the SS voltage exceeds the
DACOUT voltage and the output voltage is in regulation.
This method provides a rapid and controlled output voltage
rise. The PGOOD signal toggles `high' when the output
voltage (VSEN pin) is with in

5% of DACOUT. The 2%

hysteresis built into the power good comparators prevents
PGOOD oscillation due to nominal output voltage ripple.

Over-Current Protection

The over-current function protects the converter from a
shorted output by using the upper MOSFET's on-resistance,
r

DS(ON)

to monitor the current. This method enhances the

converter's efficiency and reduces cost by eliminating a
current sensing resistor.

The over-current function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor (R

OCSET

)

programs the over-current trip level. An internal 200

A current

sink develops a voltage across R

OCSET

that is referenced to

. When the voltage across the upper MOSFET (also

referenced to V

) exceeds the voltage across R

OCSET

, the

over-current function initiates a soft-start sequence. The soft-
start function discharges C

with a 10

A current sink and

200kHz

(

)

---------------------

to GND)

200kHz

(

)

---------------------

to 12V)

TIME (5ms/DIV)

SOFT-START
(1V/DIV)

OUTPUT

(1V/DIV)

VOLTAGE

PGOOD
(2V/DIV)

FIGURE 3. SOFT START INTERVAL

HIP6002

inhibits PWM operation. The soft-start function recharges
C

, and PWM operation resumes with the error amplifier

clamped to the SS voltage. Should an overload occur while
recharging C

, the soft start function inhibits PWM operation

while fully charging C

to 4V to complete its cycle. Figure 4

shows this operation with an overload condition. Note that the
inductor current increases to over 15A during the C

charging interval and causes an over-current trip. The
converter dissipates very little power with this method. The
measured input power for the conditions of Figure 4 is 2.5W.

The over-current function will trip at a peak inductor current
(I

PEAK)

determined by:

where I

OCSET

is the internal OCSET current source (200

A -

typical). The OC trip point varies mainly due to the MOSFET's
r

DS(ON)

variations. To avoid over-current tripping in the normal

operating load range, find the R

OCSET

resistor from the

equation above with:

1. The maximum r

DS(ON)

at the highest junction

temperature.

2. The minimum I

OCSET

from the Specification Table.

3. Determine I

PEAK

for I

PEAK

> I

OUT(MAX)

+ (

I)/2, where

is the output inductor ripple current.

For an equation for the ripple current see the section under
component guidelines titled `Output Inductor Selection'.

A small ceramic capacitor should be placed in parallel with
R

OCSET

to smooth the voltage across R

OCSET

in the

presence of switching noise on the input voltage.

Output Voltage Program

The output voltage of a HIP6002 converter is digitally
programmed to levels between 2VDC and 3.5VDC. The
voltage identification (VID) pins program an internal voltage
reference (DACOUT) with a 4-bit digital-to-analog converter

(DAC). The level of DACOUT also sets the PGOOD and
OVP thresholds. Table 1 specifies the DACOUT voltage for
the 16 combinations of open or short connections on the VID
pins. The output voltage should not be adjusted while the
converter is delivering power. Remove input power or inhibit the
converter (EN pin to GND) before changing the output voltage.
Adjusting the output voltage during operation could toggle the
PGOOD signal and exercise the overvoltage protection.

The DAC function is a precision non-inverting summation
amplifier shown in Figure 5. The resistor values shown are
only approximations of the actual precision values used.
Grounding any combination of the VID pins increases the
DACOUT voltage. The `open' circuit voltage on the VID pins
is the band gap reference voltage, 1.26V.

OUTPUT INDUCT

SOFT

-ST

TIME (20ms/DIV)

10A

15A

FIGURE 4. OVER-CURRENT OPERATION

PEAK

OCSET

DS(ON)

---------------------------------------------------

TABLE 1. OUTPUT VOLTAGE PROGRAM

PIN NAME

NOMINAL

DACOUT

VOLTAGE

VID3

VID2

VID1

VID0

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

NOTE: 0 = connected to GND or V

, 1 = OPEN.

HIP6002

Application Guidelines

Layout Considerations

As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible, using ground
plane construction or single point grounding.

Figure 6 shows the critical power components of the converter.
To minimize the voltage overshoot, the interconnecting wires
indicated by heavy lines should be part of ground or power
plane in a printed circuit board. The components shown in
Figure 6 should be located as close together as possible.
Please note that the capacitors C

and C

each represent

numerous physical capacitors. Locate the HIP6002 within 3
inches of the MOSFETs, Q1 and Q2. The circuit traces for the
MOSFETs' gate and source connections from the HIP6002
must be sized to handle up to 1A peak current.

Figure 7 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, C

close to the SS pin because the internal current source is
only 10

A. Provide local V

decoupling between VCC and

GND pins. Locate the capacitor, C

BOOT

as close as practical

to the BOOT and PHASE pins.

Feedback Compensation

Figure 8 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V

OUT

) is regulated to the Reference voltage level. The error

amplifier (Error Amp) output (V

E/A

) is compared with the

oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of V

at the

PHASE node. The PWM wave is smoothed by the output
filter (L

and C

The modulator transfer function is the small-signal transfer
function of V

OUT

E/A

. This function is dominated by a DC

Gain and the output filter (L

and C

), with a double pole

break frequency at F

and a zero at F

ESR

. The DC Gain of

the modulator is simply the input voltage (V

) divided by the

peak-to-peak oscillator voltage

OSC

Modulator Break Frequency Equations

The compensation network consists of the error amplifier
(internal to the HIP6002) and the impedance networks Z

and Z

. The goal of the compensation network is to

provide a closed loop transfer function with the highest 0dB
crossing frequency (f

0dB

) and adequate phase margin.

Phase margin is the difference between the closed loop
phase at f

0dB

and 180 degrees

The equations below relate

the compensation network's poles, zeros and gain to the
components (R1, R2, R3, C1, C2, and C3) in Figure 9. Use
these guidelines for locating the poles and zeros of the
compensation network:

BAND GAP

REFERENCE

1.26V

VID0

VID1

VID2

VID3

COMP

DACOUT

ERROR
AMPLIFIER

21.5k

1.7k

10.7k

5.4k

2.7k

2.9k

DAC

FIGURE 5. DAC FUNCTION SCHEMATIC

PGND

LGATE

UGATE

PHASE

OUT

RETURN

HIP6002

FIGURE 6. PRINTED CIRCUIT BOARD POWER AND

GROUND PLANES OR ISLANDS

FIGURE 7. PRINTED CIRCUIT BOARD SMALL SIGNAL

LAYOUT GUIDELINES

+12V

HIP6002

GND

VCC

BOOT

OUT

PHASE

BOOT

VCC

---------------------------------------

ESR

(

)

---------------------------------------------

HIP6002

Compensation Break Frequency Equations

1. Pick Gain (R2/R1) for desired converter bandwidth

2. Place 1

Zero Below Filter's Double Pole (~75% F

)

3. Place 2

Zero at Filter's Double Pole

4. Place 1

Pole at the ESR Zero

5. Place 2

Pole at Half the Switching Frequency

6. Check Gain against Error Amplifier's Open-Loop Gain

7. Estimate Phase Margin - Repeat if Necessary

Figure 9 shows an asymptotic plot of the DC-DC converter's
gain vs frequency. The actual Modulator Gain has a high
gain peak due to the high Q factor of the output filter and is
not shown in Figure 9. Using the above guidelines should
give a Compensation Gain similar to the curve plotted. The
open loop error amplifier gain bounds the compensation gain.
Check the compensation gain at F

with the capabilities of

the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 9 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to

multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.

The compensation gain uses external impedance networks
Z

and Z

to provide a stable, high bandwidth (BW) overall

loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.

Component Selection Guidelines

Output Capacitor Selection

An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.

Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the
transient and slow the current load rate seen by the bulk
capacitors. The bulk filter capacitor values are generally
determined by the ESR (effective series resistance) and
voltage rating requirements rather than actual capacitance
requirements.

High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible.
Be careful not to add inductance in the circuit board wiring
that could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements. For example, Intel
recommends that the high frequency decoupling for the
Pentium Pro be composed of at least forty (40) 1

ceramic capacitors in the 1206 surface-mount package.

Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The

OUT

OSC

REFERENCE

ESR

OSC

ERROR
AMP

PWM

DRIVER

(PARASITIC)

DACOUT

COMP

OUT

HIP6002

COMPARATOR

DRIVER

DETAILED COMPENSATION COMPONENTS

PHASE

E/A

FIGURE 8. VOLTAGE - MODE BUCK CONVERTER

COMPENSATION DESIGN

----------------------------------

(

)

------------------------------------------------------

----------------------

-------------------------------------------------------

----------------------------------

100

-20

-40

-60

10M

100K

10K

100

OPEN LOOP
ERROR AMP GAIN

20LOG

ESR

COMPENSATION

GAIN (dB)

FREQUENCY (Hz)

GAIN

20LOG

OSC

)

MODULATOR

GAIN

(R2/R1)

FIGURE 9. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

CLOSED LOOP

GAIN

HIP6002

bulk capacitor's ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor's ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the Equivalent Series Inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with your
capacitor supplier and measure the capacitor's impedance with
frequency to select a suitable component. In most cases,
multiple electrolytic capacitors of small case size perform better
than a single large case capacitor.

Output Inductor Selection

The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter's response
time to the load transient. The inductor value determines the
converter's ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the following equations:

Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter's response time to a load transient.

One of the parameters limiting the converter's response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
HIP6002 will provide either 0% or 100% duty cycle in response
to a load transient. The response time is the time required to
slew the inductor current from an initial current value to the
transient current level. During this interval the difference
between the inductor current and the transient current level
must be supplied by the output capacitor. Minimizing the
response time can minimize the output capacitance required.

The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:

where: I

TRAN

is the transient load current step, t

RISE

is the

response time to the application of load, and t

FALL

is the

response time to the removal of load. With a +5V input
source, the worst case response time can be either at the
application or removal of load and dependent upon the
DACOUT setting. Be sure to check both of these equations
at the minimum and maximum output levels for the worst
case response time. With a +12V input, and output voltage
level equal to DACOUT, t

FALL

is the longest response time.

Input Capacitor Selection

Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time Q1 turns on. Place the
small ceramic capacitors physically close to the MOSFETs
and between the drain of Q1 and the source of Q2.

The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 the DC load current.

For a through hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX
or equivalent) may be needed. For surface mount designs, solid
tantalum capacitors can be used, but caution must be
exercised with regard to the capacitor surge current rating.
These capacitors must be capable of handling the surge-
current at power-up. The TPS series available from AVX, and
the 593D series from Sprague are both surge current tested.

MOSFET Selection/Considerations

The HIP6002 requires 2 N-channel power MOSFETs. These
should be selected based upon r

DS(ON)

, gate supply

requirements, and thermal management requirements.

In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss
components; conduction loss and switching loss. The
conduction losses are the largest component of power
dissipation for both the upper and the lower MOSFETs.
These losses are distributed between the two MOSFETs
according to duty factor (see the equations below). Only the
upper MOSFET has switching losses, since the Schottky
rectifier clamps the switching node before the synchronous
rectifier turns on. These equations assume linear

voltage-current transitions and do not adequately model
power loss due the reverse-recovery of the lower MOSFET's
body diode. The gate-charge losses are dissipated by the
HIP6002 and don't heat the MOSFETs. However, large gate-
charge increases the switching interval, t

which increases

OUT

I x ESR

I =

- V

OUT

Fs x L

--------------------------------

OUT

----------------

RISE

TRAN

OUT

--------------------------------

FALL

TRAN

OUT

-------------------------------

UPPER

= I

x r

DS(ON)

x D + 1

Io x V

x t

x Fs

LOWER

= I

x r

DS(ON)

x (1 - D)

Where: D is the duty cycle = V

OUT

is the switching interval, and

Fs is the switching frequency.

HIP6002

the upper MOSFET switching losses. Ensure that both
MOSFETs are within their maximum junction temperature at
high ambient temperature by calculating the temperature rise
according to package thermal-resistance specifications. A
separate heatsink may be necessary depending upon
MOSFET power, package type, ambient temperature and air
flow.

Standard-gate MOSFETs are normally recommended for
use with the HIP6002. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFET's absolute
gate-to-source voltage rating determine whether logic-level
MOSFETs are appropriate.

Figure 10 shows the upper gate drive (BOOT pin) supplied
by a bootstrap circuit from V

. The boot capacitor, C

BOOT

develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of V

less the boot diode drop (V

) when the lower MOSFET, Q2

turns on. Logic-level MOSFETs can only be used if the
MOSFET's absolute gate-to-source voltage rating exceeds
the maximum voltage applied to V

Figure 11 shows the upper gate drive supplied by a direct
connection to V

. This option should only be used in

converter systems where the main input voltage is +5 VDC or
less. The peak upper gate-to-source voltage is approximately
V

less the input supply. For + 5V main power and + 12

VDC for the bias, the gate-to-source voltage of Q1 is 7V. A
logic-level MOSFET is a good choice for Q1 and a logic-level
MOSFET can be used for Q2 if its absolute gate-to-source
voltage rating exceeds the maximum voltage applied to V

Schottky Selection

Rectifier D2 is a clamp that catches the negative inductor
swing during the dead time between turning off the lower
MOSFET and turning on the upper MOSFET. The diode
must be a Schottky type to prevent the lossy parasitic
MOSFET body diode from conducting. It is acceptable to
omit the diode and let the body diode of the lower MOSFET
clamp the negative inductor swing, but efficiency will drop
one or two percent as a result. The diode's rated reverse
breakdown voltage must be greater than the maximum input
voltage.

HIP6002 DC-DC Converter Application
Circuit

Figure 12 shows an application circuit of a DC-DC Converter
for an Intel Pentium Pro microprocessor. Detailed
information on the circuit, including a complete
Bill-of-Materials and circuit board description, can be found
in Application Note AN9668. See Intersil's home page on the
web: www.intersil.com or Intersil AnswerFAX
(321-724-7800) document # 99668.

+12V

PGND

HIP6002

GND

LGATE

UGATE

PHASE

BOOT

VCC

+5V OR +12V

NOTE:

NOTE:
V

G-S

BOOT

FIGURE 10. UPPER GATE DRIVE - BOOTSTRAP OPTION

G-S

-V

+12V

PGND

HIP6002

GND

LGATE

UGATE

PHASE

BOOT

VCC

+5V OR LESS

NOTE:

NOTE:
V

G-S

FIGURE 11. UPPER GATE DRIVE - DIRECT V

DRIVE OPTION

G-S

-5V

HIP6002

+12V

PGND

HIP6002

VSEN

COMP

VID0

VID1

VID2

VID3

OVP

PGOOD

D/A

GND

MONITOR

OSC

VCC

L1 - 1

C1 - C4

C15 - C21

0.1

2x 1

0.1

2.2nF

8.2nF

20K

1.33K

10K

4x 330

7x 1000

0.1

LGATE

UGATE

OCSET

PHASE

BOOT

2N6394

1.1K

100pF

+5V

+12V

AND

PROTECTION

Component Selection Notes:
C15 - C21 each 1000

F 6.3W VDC, Sanyo MV-GX or Equivalent.

C1 - C4 each 330

F 25W VDC, Sanyo MV-GX or Equivalent.

L0 - Core: Micrometals T50-52B; Each Winding: 10 Turns of 16AWG.
L1 - Core: Micrometals T50-52; Winding: 5 Turns of 18AWG.
D1 - 1N4148 or Equivalent.
D2 - 3A, 40V Schottky, Motorola MBR340 or Equivalent.
Q1 - Q2 - Intersil MOSFET; RFP70N03.

FIGURE 12. PENTIUM PRO DC-DC CONVERTER

HIP6002

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

Sales Office Headquarters

NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240

EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05

ASIA
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029

HIP6002

Small Outline Plastic Packages (SOIC)

NOTES:

1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of

Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension "D" does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.

4. Dimension "E" does not include interlead flash or protrusions. Interlead

flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. "L" is the length of terminal for soldering to a substrate.

7. "N" is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width "B", as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

INDEX
AREA

-B-

0.25(0.010)

C A

B S

-A-

-C-

SEATING PLANE

0.10(0.004)

h x 45

0.25(0.010)

M20.3

(JEDEC MS-013-AC ISSUE C)

20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

SYMBOL

INCHES

MILLIMETERS

NOTES

MIN

MAX

MIN

MAX

0.0926

0.1043

2.35

2.65

0.0040

0.0118

0.10

0.30

0.013

0.0200

0.33

0.51

0.0091

0.0125

0.23

0.32

0.4961

0.5118

12.60

13.00

0.2914

0.2992

7.40

7.60

0.050 BSC

1.27 BSC

0.394

0.419

10.00

10.65

0.010

0.029

0.25

0.75

0.016

0.050

0.40

1.27

Rev. 0 12/93

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