2-131

HIP6007

Buck Pulse-Width Modulator (PWM)
Controller

The HIP6007 provides complete control and protection for
a DC-DC converter optimized for high-performance
microprocessor applications. It is designed to drive an
N-Channel MOSFET in a standard buck topology. The
HIP6007 integrates all of the control, output adjustment,
monitoring and protection functions into a single package.

The output voltage of the converter can be precisely
regulated to as low as 1.27V, with a maximum tolerance of

1% over temperature and line voltage variations.

The HIP6007 provides simple, single feedback loop, voltage-
mode control with fast transient response. It includes a
200kHz free-running triangle-wave oscillator that is
adjustable from below 50kHz to over 1MHz. The error
amplifier features a 15MHz gain-bandwidth product and
6V/

s slew rate which enables high converter bandwidth for

fast transient performance. The resulting PWM duty ratio
ranges from 0% to 100%.

The HIP6007 protects against over-current conditions by
inhibiting PWM operation. The HIP6007 monitors the current
by using the r

DS(ON)

of the upper MOSFET which eliminates

the need for a current sensing resistor.

Pinout

HIP6007

(SOIC)

TOP VIEW

Features

· Drives N-Channel MOSFET

· Operates From +5V or +12V Input

· Simple Single-Loop Control Design

- Voltage-Mode PWM Control

· Fast Transient Response

- High-Bandwidth Error Amplifier

- Full 0% to 100% Duty Ratio

· Excellent Output Voltage Regulation

- 1.27V Internal Reference

1% Over Line Voltage and Temperature

· Over-Current Fault Monitor

- Does Not Require Extra Current Sensing Element

- Uses MOSFET's r

DS(on)

· Small Converter Size

- Constant Frequency Operation

- 200kHz Free-Running Oscillator Programmable from

50kHz to Over 1MHz

· 14 Pin, SOIC Package

Applications

· Power Supply for Pentium®, Pentium Pro, PowerPCTM and

AlphaTM Microprocessors

· High-Power 5V to 3.xV DC-DC Regulators

· Low-Voltage Distributed Power Supplies

PowerPCTM is a trademark of IBM.

AlphaTM is a trademark of Digital Equipment Corporation.

Pentium® is a registered trademark of Intel Corporation.

OCSET

COMP

VCC

BOOT

UGATE

PHASE

GND

Ordering Information

PART NUMBER

TEMP. RANGE

(

PACKAGE

PKG.

NO.

HIP6007CB

0 to 70

14 Ld SOIC

M14.15

Data Sheet

September 1997

File Number

4307.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207

Intersil Corporation 1999

2-133

Absolute Maximum Ratings

Thermal Information

Supply Voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15.0V

Boot Voltage, V

BOOT

- V

PHASE

. . . . . . . . . . . . . . . . . . . . . . . +15.0V

Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2

Operating Conditions

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V

10%

Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0

C to 70

Junction Temperature Range . . . . . . . . . . . . . . . . . . . . 0

C to 125

Thermal Resistance (Typical, Note 1)

(

C/W)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

150

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150

Maximum Storage Temperature Range . . . . . . . . . . -65

C to 150

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300

(Lead Tips Only)

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

Recommended Operating Conditions, Unless Otherwise Noted

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

VCC SUPPLY CURRENT

Nominal Supply

EN = VCC; UGATE and LGATE Open

Shutdown Supply

EN = 0V

100

POWER-ON RESET

Rising VCC Threshold

OCSET

= 4.5VDC

10.4

Falling VCC Threshold

OCSET

= 4.5VDC

8.2

Enable - Input threshold Voltage

OCSET

= 4.5VDC

0.8

2.0

Rising V

OCSET

Threshold

1.27

OSCILLATOR

Free Running Frequency

RT = OPEN, V

= 12

185

200

215

kHz

Total Variation

< RT to GND < 200k

-15

+15

Ramp Amplitude

OSC

RT = OPEN

1.9

P-P

REFERENCE

Reference Voltage

1.258

1.270

1.282

ERROR AMPLIFIER

DC Gain

Gain-Bandwidth Product

GBW

MHz

Slew Rate

COMP = 10pF

GATE DRIVERS

Upper Gate Source

UGATE

BOOT

- V

PHASE

= 12V, V

UGATE

= 6V

350

500

Upper Gate Sink

UGATE

LGATE

= 0.3A

5.5

PROTECTION

OCSET Current Source

OCSET

= 4.5VDC

170

200

230

Soft Start Current

HIP6007

2-134

Functional Pin Description

RT (Pin 1)

This pin provides oscillator switching frequency adjustment.
By placing a resistor (R

) from this pin to GND, the nominal

200kHz switching frequency is increased according to the
following equation:

Conversely, connecting a pull-up resistor (R

) from this pin

to VCC reduces the switching frequency according to the
following equation.:

OCSET (Pin 2)

Connect a resistor (R

OCSET

) from this pin to the drain of the

upper MOSFET. R

OCSET

, an internal 200

A current source

OCS

), and the upper MOSFET on-resistance (r

DS(ON)

) set

the converter over-current (OC) trip point according to the
following equation:

An over-current trip cycles the soft-start function.

SS (Pin 3)

Connect a capacitor from this pin to ground. This capacitor,
along with an internal 10

A current source, sets the soft-

start interval of the converter.

COMP (Pin 4) and FB (Pin 5)

COMP and FB are the available external pins of the error
amplifier. The FB pin is the inverting input of the error
amplifier and the COMP pin is the error amplifier output.
These pins are used to compensate the voltage-control
feedback loop of the converter.

EN (Pin 6)

This pin is the open-collector enable pin. Pull this pin below
1V to disable the converter. In shutdown, the soft start pin is
discharged and the UGATE and LGATE pins are held low.

GND (Pin 7)

Signal ground for the IC. All voltage levels are measured with
respect to this pin.

PHASE (Pin 8)

Connect the PHASE pin to the upper MOSFET source. This
pin is used to monitor the voltage drop across the MOSFET
for over-current protection. This pin also provides the return
path for the upper gate drive.

UGATE (Pin 9)

Connect UGATE to the upper MOSFET gate. This pin
provides the gate drive for the upper MOSFET.

BOOT (Pin 10)

This pin provides bias voltage to the upper MOSFET driver.
A bootstrap circuit may be used to create a BOOT voltage
suitable to drive a standard N-Channel MOSFET.

VCC (Pin 14)

Provide a 12V bias supply for the chip to this pin.

Typical Performance Curves

FIGURE 1. R

RESISTANCE vs FREQUENCY

FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY

100

1000

SWITCHING FREQUENCY (kHz)

RESIST

ANCE (k

)

100

1000

PULLUP

TO +12V

PULLDOWN

TO V

100

200

300

400

500

600

700

800

900

1000

(mA)

SWITCHING FREQUENCY (kHz)

GATE

= 3300pF

GATE

= 1000pF

GATE

= 10pF

OCSET

COMP

VCC

BOOT

UGATE

PHASE

GND

200kHz

(

)

---------------------

to GND)

200kHz

(

)

---------------------

to 12V)

PEAK

OCS

OCSET

DS ON

(

)

--------------------------------------------

HIP6007

2-135

Functional Description

Initialization

The HIP6007 automatically initializes upon receipt of power.
Special sequencing of the input supplies is not necessary.
The Power-On Reset (POR) function continually monitors
the input supply voltages and the enable (EN) pin. The POR
monitors the bias voltage at the VCC pin and the input
voltage (V

) on the OCSET pin. The level on OCSET is

equal to V

less a fixed voltage drop (see over-current

protection). With the EN pin held to VCC, the POR function
initiates soft start operation after both input supply voltages
exceed their POR thresholds. For operation with a single
+12V power source, V

and V

are equivalent and the

+12V power source must exceed the rising V

threshold

before POR initiates operation.

The Power-On Reset (POR) function inhibits operation with
the chip disabled (EN pin low). With both input supplies
above their POR thresholds, transitioning the EN pin high
initiates a soft start interval.

Soft Start

The POR function initiates the soft start sequence. An internal
10

A current source charges an external capacitor (C

) on

the SS pin to 4V. Soft start clamps the error amplifier output
(COMP pin) and reference input (+ terminal of error amp) to
the SS pin voltage. Figure 3 shows the soft start interval with
C

= 0.1

F. Initially the clamp on the error amplifier (COMP

pin) controls the converter's output voltage. At t1 in Figure 3,
the SS voltage reaches the valley of the oscillator's triangle
wave. The oscillator's triangular waveform is compared to the
ramping error amplifier voltage. This generates PHASE
pulses of increasing width that charge the output capacitor(s).
This interval of increasing pulse width continues to t2. With
sufficient output voltage, the clamp on the reference input
controls the output voltage. This is the interval between t2 and
t3 in Figure 3. At t3 the SS voltage exceeds the reference
voltage and the output voltage is in regulation. This method
provides a rapid and controlled output voltage rise.

Over-Current Protection

The over-current function protects the converter from a
shorted output by using the upper MOSFET's on-resistance,
r

DS(ON)

to monitor the current. This method enhances the

converter's efficiency and reduces cost by eliminating a
current sensing resistor.

The over-current function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor (R

OCSET

)

programs the over-current trip level. An internal 200

(typical) current sink develops a voltage across R

OCSET

that

is reference to V

. When the voltage across the upper

MOSFET (also referenced to V

) exceeds the voltage

across R

OCSET

, the over-current function initiates a soft-

start sequence. The soft-start function discharges C

with

a 10

A current sink and inhibits PWM operation. The soft-

start function recharges C

, and PWM operation resumes

with the error amplifier clamped to the SS voltage. Should an
overload occur while recharging C

, the soft start function

inhibits PWM operation while fully charging C

to 4V to

complete its cycle. Figure 4 shows this operation with an
overload condition. Note that the inductor current increases
to over 15A during the C

charging interval and causes an

over-current trip. The converter dissipates very little power
with this method. The measured input power for the
conditions of Figure 4 is 2.5W.

FIGURE 3. SOFT-START INTERVAL

TIME (5ms/DIV)

SOFT-START
(1V/DIV)

OUTPUT

(1V/DIV)

VOLTAGE

HIP6007

2-136

The over-current function will trip at a peak inductor current
(I

PEAK

) determined by:

where I

OCSET

is the internal OCSET current source (200

- typical). The OC trip point varies mainly due to the
MOSFET's r

DS(ON)

variations. To avoid over-current tripping

in the normal operating load range, find the R

OCSET

resistor

from the equation above with:

1. The maximum r

DS(ON)

at the highest junction tempera-

ture.

2. The minimum I

OCSET

from the specification table.

3. Determine

where

I is the output inductor ripple current.

For an equation for the ripple current see the section under
component guidelines titled `Output Inductor Selection'.

A small ceramic capacitor should be placed in parallel with
R

OCSET

to smooth the voltage across R

OCSET

in the

presence of switching noise on the input voltage.

Application Guidelines

Layout Considerations

As in any high frequency switching converter, layout is very
important. Switching current from one power device to
another can generate voltage transients across the
impedances of the interconnecting bond wires and circuit
traces. These interconnecting impedances should be
minimized by using wide, short printed circuit traces. The
critical components should be located as close together as
possible using ground plane construction or single point
grounding.

Figure 5 shows the critical power components of the
converter. To minimize the voltage overshoot the
interconnecting wires indicated by heavy lines should be

part of ground or power plane in a printed circuit board. The
components shown in Figure 6 should be located as close
together as possible. Please note that the capacitors C

and C

each represent numerous physical capacitors.

Locate the HIP6007 within 3 inches of the MOSFETs, Q1.
The circuit traces for the MOSFETs' gate and source
connections from the HIP6007 must be sized to handle up to
1A peak current.

Figure 6 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, C

close to the SS pin because the internal current source is
only 10

A. Provide local V

decoupling between VCC and

GND pins. Locate the capacitor, C

BOOT

as close as practical

to the BOOT and PHASE pins.

FIGURE 4. OVER-CURRENT OPERATION

OUTPUT INDUCT

SOFT

-ST

TIME (20ms/DIV)

10A

15A

PEAK

OCSET

DS ON

(

)

---------------------------------------------------

PEAK

for I

PEAK

OUT MAX

(

)

( )

FIGURE 5. PRINTED CIRCUIT BOARD

POWER AND GROUND PLANES OR ISLANDS

UGATE

PHASE

OUT

RETURN

HIP6007

+12V

HIP6007

GND

BOOT

OUT

PHASE

FIGURE 6. PRINTED CIRCUIT BOARD

SMALL SIGNAL LAYOUT GUIDELINES

BOOT

VCC

HIP6007

2-137

Feedback Compensation

Figure 7 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(Vout) is regulated to the Reference voltage level. The error
amplifier (Error Amp) output (V

E/A

) is compared with the

oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of Vin at the
PHASE node. The PWM wave is smoothed by the output
filter (Lo and Co).

The modulator transfer function is the small-signal transfer
function of Vout/V

E/A

. This function is dominated by a DC

Gain and the output filter (Lo and Co), with a double pole
break frequency at F

and a zero at F

ESR

. The DC Gain of

the modulator is simply the input voltage (Vin) divided by the
peak-to-peak oscillator voltage

OSC

Modulator Break Frequency Equations

The compensation network consists of the error amplifier
(internal to the HIP6007) and the impedance networks Z

and Z

. The goal of the compensation network is to provide

a closed loop transfer function with the highest 0dB crossing
frequency (f

0dB

) and adequate phase margin. Phase margin

is the difference between the closed loop phase at f

0dB

and

180

The equations below relate the compensation

network's poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 8. Use these guidelines for
locating the poles and zeros of the compensation network:

Compensation Break Frequency Equations

1. Pick Gain (R2/R1) for desired converter bandwidth

2. Place 1

Zero Below Filter's Double Pole

(~75% F

)

3. Place 2

Zero at Filter's Double Pole

4. Place 1

Pole at the ESR Zero

5. Place 2

Pole at Half the Switching Frequency

6. Check Gain against Error Amplifier's Open-Loop Gain

7. Estimate Phase Margin - Repeat if Necessary

Figure 8 shows an asymptotic plot of the DC-DC converter's
gain vs frequency. The actual Modulator Gain has a high gain
peak do to the high Q factor of the output filter and is not
shown in Figure 8. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at F

with the capabilities of

the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 8 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.

The compensation gain uses external impedance networks
Z

and Z

to provide a stable, high bandwidth (BW) overall

loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45

Include worst case component variations when determining
phase margin.

FIGURE 7. VOLTAGE - MODE BUCK CONVERTER

COMPENSATION DESIGN

OUT

OSC

REFERENCE

ESR

OSC

ERROR
AMP

PWM

DRIVER

(PARASITIC)

REF

COMP

OUT

HIP6007

COMPARATOR

DRIVER

DETAILED COMPENSATION COMPONENTS

PHASE

E/A

LC =

---------------------------------------

ESR

(

)

--------------------------------------------

---------------------------------

C1 + C2

----------------------

------------------------------------------------------

R1 + R3

(

)

-----------------------------------------------------

---------------------------------

100

-20

-40

-60

10M

100K

10K

100

OPEN LOOP
ERROR AMP GAIN

ESR

COMPENSATION

GAIN (dB)

FREQUENCY (Hz)

GAIN

20LOG

OSC

)

MODULATOR

GAIN

20LOG

(R2/R1)

CLOSED LOOP
GAIN

FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

HIP6007

2-138

Component Selection Guidelines

Output Capacitor Selection

An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.

Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the
transient and slow the current load rate seen by the bulk
capacitors. The bulk filter capacitor values are generally
determined by the ESR (effective series resistance) and
voltage rating requirements rather than actual capacitance
requirements.

High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements. For example, Intel
recommends that the high frequency decoupling for the
Pentium-Pro be composed of at least forty (40) 1.0

ceramic capacitors in the 1206 surface-mount package.

Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor's ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient.
An aluminum electrolytic capacitor's ESR value is related to
the case size with lower ESR available in larger case sizes.
However, the equivalent series inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient
loading. Unfortunately, ESL is not a specified parameter.
Work with your capacitor supplier and measure the
capacitor's impedance with frequency to select a suitable
component. In most cases, multiple electrolytic capacitors of
small case size perform better than a single large case
capacitor.

Output Inductor Selection

The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter's response
time to the load transient. The inductor value determines the
converter's ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the following equations:

Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter's response time to a load transient.

One of the parameters limiting the converter's response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
HIP6007 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.

The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:

where: I

TRAN

is the transient load current step, t

RISE

is the

response time to the application of load, and t

FALL

is the

response time to the removal of load. With a +5V input
source, the worst case response time can be either at the
application or removal of load and dependent upon the
output voltage setting. Be sure to check both of these
equations at the minimum and maximum output levels for the
worst case response time.

Input Capacitor Selection

Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time Q1 turns on. Place
the small ceramic capacitors physically close to the
MOSFETs and between the drain of Q1 and the anode of
Schottky diode D2.

The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 the DC load current.

For a through hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-
GX or equivalent) may be needed. For surface mount
designs, solid tantalum capacitors can be used, but caution
must be exercised with regard to the capacitor surge current
rating. These capacitors must be capable of handling the
surge-current at power-up. The TPS series available from
AVX, and the 593D series from Sprague are both surge
current tested.

I =

- V

OUT

--------------------------------

OUT

----------------

OUT

I x ESR

RISE

x I

TRAN

- V

FALL

x I

TRAN

HIP6007

2-139

MOSFET Selection/Considerations

The HIP6007 requires an N-Channel power MOSFET. It
should be selected based upon r

DS(ON)

, gate supply

requirements, and thermal management requirements.

In high-current applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The power dissipation includes
two loss components; conduction loss and switching loss.
The conduction losses are the largest component of power
dissipation for the MOSFET. Switching losses also
contribute to the overall MOSFET power loss (see the
equations below). These equations assume linear voltage-
current transitions and are approximations. The gate-
charge losses are dissipated by the HIP6007 and don't
heat the MOSFET. However, large gate-charge increases
the switching interval, t

, which increases the upper

MOSFET switching losses. Ensure that the MOSFET is
within its maximum junction temperature at high ambient
temperature by calculating the temperature rise according
to package thermal-resistance specifications. A separate
heatsink may be necessary depending upon MOSFET
power, package type, ambient temperature and air flow.

Standard-gate MOSFETs are normally recommended for
use with the HIP6007. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFET's absolute gate-to-
source voltage rating determine whether logic-level
MOSFETs are appropriate.

Figure 9 shows the upper gate drive (BOOT pin) supplied by
a bootstrap circuit from V

. The boot capacitor, C

BOOT

develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of V

less the boot diode drop (V

) when the lower MOSFET, Q2

turns on. A logic-level MOSFET can only be used for Q1 if
the MOSFET's absolute gate-to-source voltage rating
exceeds the maximum voltage applied to V

Figure 10 shows the upper gate drive supplied by a direct
connection to VCC. This option should only be used in
converter systems where the main input voltage is +5VDC
or less. The peak upper gate-to-source voltage is
approximately V

less the input supply. For +5V main

power and +12VDC for the bias, the gate-to-source voltage
of Q1 is 7V. A logic-level MOSFET is a good choice for Q1
and a logic-level MOSFET is a good choice for Q1 under
these conditions.

Schottky Selection

Rectifier D2 conducts when the upper MOSFET Q1 is off.
The diode should be a Schottky type for low power losses.
The power dissipation in the schottky rectifier is
approximated by:

In addition to power dissipation, package selection and
heatsink requirements are the main design tradeoffs in
choosing the schottky rectifier. Since the three factors are
interrelated, the selection process is an iterative procedure.
The maximum junction temperature of the rectifier must
remain below the manufacturer's specified value, typically
125

C. By using the package thermal resistance specification

and the schottky power dissipation equation (shown above),
the junction temperature of the rectifier can be estimated. Be
sure to use the available airflow and ambient temperature to
determine the junction temperature rise.

COND

= I

x r

DS(ON)

x D

x V

x t

x Fs

Where: D is the duty cycle = V

/ V

is the switching interval, and

Fs is the switching frequency.

FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION

+12V

HIP6007

GND

UGATE

PHASE

BOOT

VCC

+5V OR +12V

BOOT

NOTE:
V

G-S

- V

FIGURE 10. UPPER GATE DRIVE - DIRECT V

DRIVE OPTION

+12V

HIP6007

GND

UGATE

PHASE

BOOT

VCC

+5V OR LESS

NOTE:

G-S

- 5V

COND

= I

x V

x (1 - D)

Where: D is the duty cycle = V

, and

is the schottky forward voltage drop

HIP6007

2-140

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out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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HIP6007 DC-DC Converter Application Circuit

The figure below shows an application circuit of a DC-DC
Converter for a microprocessor application. Detailed
information on the circuit, including a complete Bill-of-
Materials and circuit board description, can be found in

Application Note AN9722. See Intersil's home page on the
web: http://www.intersil.com or Intersil AnswerFAX (407-724-
7800) document # 99722.

HIP6007

COMP

REF

GND

OSC

VCC

VIN

C1-5

C6-11

0.1

2x 1

0.1

33pF

0.01

15k

3x 680

4x 1000

UGATE

OCSET

PHASE

BOOT

SPARE

CR1

3.01k

1000pF

C13

C16

C15

C14

C12

C17-18

C19

C20

4148

RTN

12VCC

SPARE

JP1

CR3

1206

OUT

RTN

ENABLE

R2
1k

COMP
TP1

PHASE

TP2

R7
10k

13 NC

SPARE

MONITOR AND

PROTECTION

Component Selection Notes

C1-C3 -3 each 680

F 25W VDC, Sanyo MV-GX or equivalent

C6-C9 -4 each 1000

F 6.3W VDC, Sanyo MV-GX or equivalent

L1 -Core: Micrometals T60-52; Winding: 14 Turns of 17AWG

CR1 -1N4148 or equivalent

CR3 -15A, 35V Schottky, Motorola MBR1535CT or equivalent

Q1 -Intersil MOSFET; RFP25N05

FIGURE 11. DC-DC CONVERTER APPLICATION CIRCUIT

HIP6007

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HIP6007CB