FN4793.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

Intersil (and design) is a trademark of Intersil Americas Inc.

HIP6021A

Advanced PWM and Triple Linear Power
Controller

The HIP6021A provides the power control and protection for
four output voltages in high-performance, graphics intensive
microprocessor and computer applications. The IC
integrates a voltage-mode PWM controller and three linear
controllers, as well as the monitoring and protection
functions into a 28 lead SOIC package.

The synchronous-rectified buck converter includes an Intel-
compatible, TTL 5-input digital-to-analog converter (DAC)
that adjusts the core PWM output voltage from 1.3V

2.05V

in 0.05V steps and from 2.1V

to 3.5V

in 0.1V

increments. The precision reference and voltage-mode
control provide

1% static regulation. A TTL-compatible

signal applied to the SELECT pin dictates which method of
control is used for the AGP bus power: a low state results in
linear control of the AGP bus to 1.5V, while a high state
transitions the output through a linearly controlled softstart to
3.3V, followed by full enhancement of the external MOSFET
to pass the input voltage. The other two linear regulators
provide fixed output voltages of 1.5V GTL bus power and
1.8V power for the North/South Bridge core and/or cache
memory. These levels are user-adjustable by means of an
external resistor divider and pulling the FIX pin low. All linear
controllers can employ either N-Channel MOSFETs or
bipolar NPNs for the pass transistor.

The HIP6021A monitors all the output voltages. A single
Power Good signal is issued when the core is within

10% of

the DAC setting and all other outputs are above their under-
voltage levels. Additional built-in over-voltage protection for
the core output uses the lower MOSFET to prevent output
voltages above 115% of the DAC setting. The PWM
controller's over-current function monitors the output current
by using the voltage drop across the upper MOSFET's
r

DS(ON)

Features

· Provides 4 Regulated Voltages

- Microprocessor Core, AGP Bus, Memory, and GTL Bus

Power

· Drives N-Channel MOSFETs

· Linear Regulator Drives Compatible with both MOSFET

and Bipolar Series Pass Transistors

· Fixed or Externally Resistor-Adjustable Linear Outputs

· Simple Single-Loop Control Design

- Voltage-Mode PWM Control

· Fast PWM Converter Transient Response

- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Ratio

· Excellent Output Voltage Regulation

- Core PWM Output:

1% Over Temperature

- Other Outputs:

3% Over Temperature

· TTL-Compatible 5-Bit DAC Core Output Voltage Selection

- Shutdown Feature Removed When All Inputs High
- Wide Range 1.3V

to 3.5V

· Power-Good Output Voltage Monitor

· Over-Voltage and Over-Current Fault Monitors

- Switching Regulator Does Not Require Extra Current

Sensing Element, Uses Upper MOSFET's r

DS(ON)

· Small Converter Size

- Constant Frequency Operation
- 200kHz Free-Running Oscillator; Programmable From

50kHz to Over 1MHz

- Small External Component Count

Applications

· Motherboard Power Regulation for Computers

Pinout

HIP6021A (SOIC)

TOP VIEW

Ordering Information

PART NUMBER

TEMP.

RANGE (

PACKAGE

PKG.

NO.

HIP6021ACB

0 to 70

28 Ld SOIC

M28.3

HIP6021EVAL1

Evaluation Board

DRIVE2

FIX

VID4

VID3

VSEN2

SELECT

FAULT/RT

VSEN4

VCC

PGND

LGATE

PHASE

DRIVE3

COMP

GND

VAUX

DRIVE4

UGATE

PGOOD

VID2

VSEN1

VSEN3

VID1

VID0

OCSET

Data Sheet

December 2001

Absolute Maximum Ratings

Thermal Information

Supply Voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15V

PGOOD, RT/FAULT, DRIVE, PHASE,

and GATE Voltage . . . . . . . . . . . . . . . GND - 0.3V to V

+ 0.3V

Input, Output or I/O Voltage . . . . . . . . . . . . . . . . . . GND -0.3V to 7V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Operating Conditions

Supply Voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . +12V

10%

Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . 0

C to 70

Junction Temperature Range. . . . . . . . . . . . . . . . . . . 0

C to 125

Thermal Resistance (Typical, Note 1)

(

C/W)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum Junction Temperature (Plastic Package) . . . . . . . 150

Maximum Storage Temperature Range . . . . . . . . . . -65

C to 150

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams, and Typical Application Schematic

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

VCC SUPPLY CURRENT

Nominal Supply Current

UGATE, LGATE, DRIVE2, DRIVE3, and
DRIVE4 Open

POWER-ON RESET

Rising VCC Threshold

OCSET

= 4.5V

10.4

Falling VCC Threshold

OCSET

= 4.5V

8.2

Rising VAUX Threshold

OCSET

= 4.5V

2.5

VAUX Threshold Hysteresis

OCSET

= 4.5V

0.5

Rising V

OCSET

Threshold

1.26

OSCILLATOR

Free Running Frequency

OSC

RT = OPEN

185

200

215

kHz

Total Variation

< RT to GND < 200k

-15

+15

Ramp Amplitude

OSC

RT = Open

1.9

P-P

DAC AND BANDGAP REFERENCE

DAC(VID0-VID4) Input Low Voltage

0.8

DAC(VID0-VID4) Input High Voltage

2.0

DACOUT Voltage Accuracy

-1.0

+1.0

Bandgap Reference Voltage

1.265

Bandgap Reference Tolerance

-2.5

+2.5

LINEAR REGULATORS (OUT2, OUT3, AND OUT4)

Regulation (All Linears)

Except OUT2 when SELECT > 2.0V

VSEN2 Regulation Voltage

VREG

SELECT < 0.8V

1.5

VSEN3 Regulation Voltage

VREG

1.5

VSEN4 Regulation Voltage

VREG

1.8

Under-Voltage Level (VSEN/VREG)

VSEN

VSEN Rising

Under-Voltage Hysteresis (VSEN/VREG)

VSEN Falling

Output Drive Current (All Linears)

VAUX-V

DRIVE

> 0.6V

HIP6021A

SYNCHRONOUS PWM CONTROLLER ERROR AMPLIFIER

DC Gain

Gain-Bandwidth Product

GBWP

MHz

Slew Rate

COMP = 10pF

PWM CONTROLLER GATE DRIVER

UGATE Source

UGATE

VCC = 12V, V

UGATE

= 6V

UGATE Sink

UGATE

GATE-PHASE

= 1V

1.7

3.5

LGATE Source

LGATE

VCC = 12V, V

LGATE

= 1V

LGATE Sink

LGATE

= 1V

1.4

3.0

PROTECTION

VSEN1 Over-Voltage (VSEN1/DACOUT)

VSEN1 Rising

115

120

FAULT Sourcing Current

OVP

FAULT/RT

= 2.0V

8.5

OCSET1 Current Source

OCSET

= 4.5V

170

200

230

Soft-Start Current

POWER GOOD

VSEN1 Upper Threshold
(VSEN1/DACOUT)

VSEN1 Rising

108

110

VSEN1 Under-Voltage
(VSEN1/DACOUT)

VSEN1 Rising

VSEN1 Hysteresis (VSEN1/DACOUT)

Upper/Lower Threshold

PGOOD Voltage Low

PGOOD

= -4mA

0.8

Electrical Specifications

Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams, and Typical Application Schematic (Continued)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Typical Performance Curve

FIGURE 1. R

RESISTANCE vs FREQUENCY

100

1000

SWITCHING FREQUENCY (kHz)

RESIST

ANCE (

)

100

1000

PULLUP

TO +12V

PULLDOWN TO V

HIP6021A

Functional Pin Descriptions

VCC (Pin 28)

Provide a 12V bias supply for the IC to this pin. This pin also
provides the gate bias charge for all the MOSFETs
controlled by the IC. The voltage at this pin is monitored for
Power-On Reset (POR) purposes.

GND (Pin 17)

Signal ground for the IC. All voltage levels are measured
with respect to this pin.

PGND (Pin 24)

This is the power ground connection. Tie the synchronous
PWM converter's lower MOSFET source to this pin.

VAUX (Pin 16)

This pin provides boost current for the linear regulators'
output drives in the event bipolar NPN transistors (instead
of N-Channel MOSFETs) are employed as pass elements.
The voltage at this pin is monitored for power-on reset
(POR) purposes.

SS (Pin 12)

Connect a capacitor from this pin to ground. This capacitor,
along with an internal 28

A current source, sets the softstart

interval of the converter.

FAULT / RT (Pin 13)

This pin provides oscillator switching frequency adjustment.
By placing a resistor (R

) from this pin to GND, the nominal

200kHz switching frequency is increased according to the
following equation:

Conversely, connecting a resistor from this pin to VCC
reduces the switching frequency according to the following
equation:

Nominally, the voltage at this pin is 1.26V. In the event of an
over-voltage or over-current condition, this pin is internally
pulled to VCC.

PGOOD (Pin 8)

PGOOD is an open collector output used to indicate the
status of the output voltages. This pin is pulled low when the
synchronous regulator output is not within

10%

of the

DACOUT reference voltage or when any of the other outputs
are below their under-voltage thresholds.

The PGOOD output is open for `11111' VID code.

SD (Pin 9)

This pin shuts down all the outputs. A TTL-compatible, logic
level high signal applied at this pin immediately discharges

the soft-start capacitor, disabling all the outputs. Dedicated
internal circuitry insures the core output voltage does not go
negative during this process. When re-enabled, the IC
undergoes a new soft-start cycle. Left open, this pin is pulled
low by an internal pull-down resistor, enabling operation.

FIX (Pin 2)

Grounding this pin bypasses the internal resistor dividers
that set the output voltage of the 1.5V and 1.8V linear
regulators. This way, the output voltage of the two regulators
can be adjusted from 1.26V up to the input voltage (+3.3V or
+5V) by way of an external resistor divider connected at the
corresponding VSEN pin. The new output voltage set by the
external resistor divider can be determined using the
following formula:

where R

OUT

is the resistor connected from VSEN to the

output of the regulator, and R

GND

is the resistor connected

from VSEN to ground. Left open, the FIX pin is pulled high,
enabling fixed output voltage operation.

VID0, VID1, VID2, VID3, VID4 (Pins 7, 6, 5, 4 and 3)

VID0-4 are the TTL-compatible input pins to the 5-bit DAC.
The logic states of these five pins program the internal
voltage reference (DACOUT). The level of DACOUT sets the
microprocessor core converter output voltage, as well as the
corresponding PGOOD and OVP thresholds.

OCSET (Pin 23)

Connect a resistor from this pin to the drain of the respective
upper MOSFET. This resistor, an internal 200

A current

source, and the upper MOSFET's on-resistance set the
converter over-current trip point. An over-current trip cycles
the soft-start function.

The voltage at this pin is monitored for power-on reset
(POR) purposes and pulling this pin low with an open drain
device will shutdown the IC.

PHASE (Pin 26)

Connect the PHASE pin to the PWM converter's upper
MOSFET source. This pin represents the gate drive return
current path and is used to monitor the voltage drop across
the upper MOSFET for over-current protection.

UGATE (Pin 27)

Connect UGATE pin to the PWM converter's upper
MOSFET gate. This pin provides the gate drive for the upper
MOSFET.

LGATE (Pin 25)

Connect LGATE to the PWM converter's lower MOSFET
gate. This pin provides the gate drive for the lower MOSFET.

200kH z

(

)

---------------------

to GND)

200kH z

(

)

---------------------

to 12V)

OUT

1.265V

OUT

GND

-----------------

HIP6021A

COMP and FB (Pin 20 and 21)

COMP and FB are the available external pins of the PWM
converter error amplifier. The FB pin is the inverting input of the
error amplifier. Similarly, the COMP pin is the error amplifier
output. These pins are used to compensate the voltage-mode
control feedback loop of the synchronous PWM converter.

VSEN1 (Pin 22)

This pin is connected to the PWM converter's output voltage.
The PGOOD and OVP comparator circuits use this signal to
report output voltage status and for over-voltage protection.

DRIVE2 (Pin 1)

Connect this pin to the gate of an external MOSFET. This pin
provides the drive for the AGP regulator's pass transistor.

VSEN2 (Pin 10)

Connect this pin to the output of the AGP linear regulator.
The voltage at this pin is regulated to the level
predetermined by the logic-level status of the SELECT pin.
This pin is also monitored for under-voltage events.

SELECT (Pin 11)

This pin determines the output voltage of the AGP bus linear
regulator. A low TTL input sets the output voltage to 1.5V
and the linear controller regulates this voltage to within

3%.

A TTL high input turns Q3 on continuously, providing a DC
current path from the input (+3.3V

) to the output (V

OUT2

)

of the AGP controller.

DRIVE3 (Pin 18)

Connect this pin to the gate of an external MOSFET. This pin
provides the drive for the 1.5V regulator's pass transistor.

VSEN3 (Pin 19)

Connect this pin to the output of the 1.5V linear regulator.
This pin is monitored for under-voltage events.

DRIVE4 (Pin 15)

Connect this pin to the gate of an external MOSFET. This pin
provides the drive for the 1.8V regulator's pass transistor.

VSEN4 (Pin 14)

Connect this pin to the output of the linear 1.8V regulator.
This pin is monitored for under voltage events.

Description

Operation

The HIP6021A monitors and precisely controls 4 output
voltage levels (Refer to Block and Simplified Power System
Diagrams, and Typical Application Schematic). It is
designed for microprocessor computer applications with
3.3V, 5V, and 12V bias input from an ATX power supply.
The microprocessor core voltage (V

OUT1

) is controlled in a

synchronous-rectified buck converter configuration. The
PWM controller regulates the microprocessor core voltage

to a level programmed by the 5-bit digital-to-analog
converter (DAC).

The AGP bus voltage (VOUT2) is set using the SELECT
pin to either a 1.5V linear regulated output or to the 3.3V

through a pass device. Selection of either output voltage is
set depending on the logic level of the SELECT pin.

The two remaining linear controllers supply the 1.5V GTL
bus power (V

OUT3

) and the 1.8V memory power (V

OUT4

These output voltages are user adjustable. All linear
controllers are designed to employ an external pass
transistor.

Initialization

The HIP6021A automatically initializes upon receipt of input
power. Special sequencing of the input supplies is not
necessary. The Power-On Reset (POR) function continually
monitors the input supply voltages. The POR monitors the
bias voltage (+12V

) at the VCC pin, the 5V input voltage

(+5V

) on the OCSET pin, and the 3.3V input voltage

(+3.3V

) at the VAUX pin. The normal level on OCSET is

equal to +5V

less a fixed voltage drop (see over-current

protection). The POR function initiates soft-start operation
after all supply voltages exceed their POR thresholds.

Soft-Start

The POR function initiates the soft-start sequence. Initially,
the voltage on the SS pin rapidly increases to approximately
1V (this minimizes the softstart interval). Then an internal
28

A current source charges an external capacitor (C

) on

the SS pin to 4.5V. The PWM error amplifier reference input
(+ terminal) and output (COMP pin) are clamped to a level
proportional to the SS pin voltage. As the SS pin voltage
slews from 1V to 4V, the output clamp allows generation of
PHASE pulses of increasing width that charge the output
capacitor(s). After the output voltage increases to
approximately 70% of the set value, the reference input
clamp slows the output voltage rate-of-rise and provides a
smooth transition to the final set voltage. Additionally, all
linear regulators' reference inputs are clamped to a voltage
proportional to the SS pin voltage. This method provides a
rapid and controlled output voltage rise.

Figure 2 shows the soft-start sequence for the typical
application. At T0 the SS voltage rapidly increases to
approximately 1V. At T1, the SS pin and error amplifier
output voltage reach the valley of the oscillator's triangle
wave. The oscillator's triangular waveform is compared to
the clamped error amplifier output voltage. As the SS pin
voltage increases, the pulse width on the PHASE pin
increases. The interval of increasing pulse width continues
until each output reaches sufficient voltage to transfer
control to the input reference clamp. If we consider the
2.5V core output (V

OUT1

) in Figure 2, this time occurs at

T2. During the interval between T2 and T3, the error
amplifier reference ramps to the final value and the
converter regulates the output a voltage proportional to the

HIP6021A

SS pin voltage. At T3 the input clamp voltage exceeds the
reference voltage and the output voltage is in regulation.

The remaining outputs are also programmed to follow the
SS pin voltage. The PGOOD signal toggles `high' when all
output voltage levels have exceeded their under-voltage
levels. The waveform for V

OUT2

represents the case where

SELECT is held `high'. The AGP bus voltage is controlled in
the same manner as the other linear regulators during the
softstart sequence. Once the softstart sequence is
complete (T4), the gate of the external pass device is fully
enhanced and V

OUT2

tracks the 3.3V

voltage. See the

Soft-Start Interval section under Applications Guidelines for
a procedure to determine the soft-start interval.

Fault Protection

All four outputs are monitored and protected against extreme
overload. A sustained overload on any output or an over-
voltage on V

OUT1

output (VSEN1) disables all outputs and

drives the FAULT/RT pin to VCC.

Figure 3 shows a simplified schematic of the fault logic. An
over-voltage detected on VSEN1 immediately sets the fault
latch. A sequence of three over-current fault signals also
sets the fault latch. The over-current latch is set dependent
upon the states of the over-current (OC), linear under-
voltage (LUV) and the soft-start signals. A window
comparator monitors the SS pin and indicates when C

fully charged to 4V (UP signal). An under-voltage on either
linear output (VSEN2, VSEN3, or VSEN4) is ignored until
after the soft-start interval (T4 in Figure 2). This allows
V

OUT2

, V

OUT3

, and V

OUT4

to increase without fault at start-

up. Cycling the bias input voltage (+12V

on the VCC pin off

then on) resets the counter and the fault latch.

Over-Voltage Protection

During operation, a short on the upper MOSFET of the PWM
regulator (Q1) causes V

OUT1

to increase. When the output

exceeds the over-voltage threshold of 115% of DACOUT, the
over-voltage comparator trips to set the fault latch and turns
Q2 on. This blows the input fuse and reduces V

OUT1

. The

fault latch raises the FAULT/RT pin to VCC.

A separate over-voltage circuit provides protection during
the initial application of power. For voltages on the VCC pin
below the power-on reset (and above ~4V), the output level
is monitored for voltages above 1.3V. Should VSEN1 exceed
this level, the lower MOSFET, Q2 is driven on.

Over-Current Protection

All outputs are protected against excessive over-currents.
The PWM controller uses the upper MOSFET's
on-resistance, r

DS(ON)

to monitor the current for protection

against shorted output. All linear controllers monitor their
respective VSEN pins for under-voltage events to protect
against excessive currents.

Figure 4 illustrates the over-current protection with an
overload on OUT1. The overload is applied at T0 and the
current increases through the inductor (L

OUT1

). At time T1,

the OVER-CURRENT comparator trips when the voltage
across Q1 (i

· r

DS(ON)

) exceeds the level programmed by

ROCSET. This inhibits all outputs, discharges the soft-start
capacitor (C

) with a 10mA current sink, and increments

the counter. C

recharges at T2 and initiates a soft-start

cycle with the error amplifiers clamped by soft-start. With
OUT1 still overloaded, the inductor current increases to trip
the over-current comparator. Again, this inhibits all outputs,
but the soft-start voltage continues increasing to 4V before
discharging. The counter increments to 2. The soft-start
cycle repeats at T3 and trips the over-current comparator.
The SS pin voltage increases to 4V at T4 and the counter
increments to 3. This sets the fault latch to disable the
converter. The fault is reported on the FAULT/RT pin.

FIGURE 2. SOFT-START INTERVAL

TIME

PGOOD

SOFT-START

(1V/DIV)

OUTPUT

(0.5V/DIV)

VOLTAGES

OUT1

(DAC = 2.5V)

OUT2

(= 3.3V

)

OUT4

(= 1.8V)

OUT3

(= 1.5V)

FAULT

LATCH

POR

COUNTER

OC1

LUV

0.15V

VCC

FAULT

FIGURE 3. FAULT LOGIC - SIMPLIFIED SCHEMATIC

OVER-

CURRENT

LATCH

INHIBIT

HIP6021A

The linear controllers operate in the same way as the PWM
in response to over-current faults. The differentiating factor
for the linear controllers is that they monitor the VSEN pins
for under-voltage events. Should excessive currents cause
the voltage at the VSEN pins to fall below the linear under-
voltage threshold, the LUV signal sets the over-current
latch if C

fully charged. Blanking the LUV signal during

the C

charge interval allows the linear outputs to build

above the under-voltage threshold during normal operation.
Cycling the bias input power off then on resets the counter
and the fault latch.

A resistor (R

OCSET

) programs the over-current trip level for

the PWM converter. As shown in Figure 5, the internal
200

A current sink, I

OCSET

develops a voltage across

OCSET

SET

) that is referenced to V

. The DRIVE

signal enables the over-current comparator (OVER-
CURRENT). When the voltage across the upper MOSFET
(V

) exceeds V

SET

, the over-current comparator trips to

set the over-current latch. Both V

SET

and V

are

referenced to V

and a small capacitor across R

OCSET

helps V

OCSET

track the variations of V

due to MOSFET

switching. The over-current function will trip at a peak
inductor current (I

PEAK)

determined by:

The OC trip point varies with MOSFET's r

DS(ON)

temperature variations. To avoid over-current tripping in the
normal operating load range, determine the R

OCSET

resistor from the equation above with:

1. The maximum r

DS(ON)

at the highest junction temperature.

2. The minimum I

OCSET

from the specification table.

3. Determine I

PEAK

for I

PEAK

> I

OUT(MAX)

+ (

I)/2, where

I is the output inductor ripple current.

For an equation for the ripple current see the section under
component guidelines titled `PWM Output Inductor
Selection'.

OUT1 Voltage Program

The output voltage of the PWM converter is programmed to
discrete levels between 1.3V

and 3.5V

. This output

(OUT1) is designed to supply the core voltage of Intel's
advanced microprocessors. The voltage identification (VID)
pins program an internal voltage reference (DACOUT) with a
TTL-compatible 5-bit digital-to-analog converter. The level of
DACOUT also sets the PGOOD and OVP thresholds.
Table 1 specifies the DACOUT voltage for the different
combinations of connections on the VID pins. The VID pins
can be left open for a logic 1 input, because they are
internally pulled up to an internal voltage of about 5V by a
10

A current source. Changing the VID inputs during

operation is not recommended, as it could toggle the
PGOOD signal and exercise the over-voltage protection.

INDUCT

CURRENT

SOF

-
S

ART

FIGURE 4. OVER-CURRENT OPERATION

TIME

AUL

/
R

10V

OVERLOAD

APPLIED

FAULT

REPORTED

COUNT

= 1

COUNT

= 2

COUNT

= 3

PEAK

OCSET

DS ON

(

)

----------------------------------------------------

UGATE

OCSET

PHASE

OVER-

CURRENT

GATE

CONTROL

VCC

200

SET

OCSET

= +5V

OVER-CURRENT TRIP:

OCSET

FIGURE 5. OVER-CURRENT DETECTION

PWM

DRIVE

DS ON

(

)

OCSET

SET

PHASE

OCSET

SET

HIP6021A

OUT2 Voltage Selection

The AGP output voltage is internally set to one of two levels,
based on the status of the SELECT pin. Grounding the
SELECT pin enables the internal 1.5V regulator control

circuitry. Left open, the SELECT pin is internally pulled `high'
and the AGP voltage is regulated to 3.3V during the softstart
sequence. Once complete, the gate drive is increased and
the regulator becomes a simple pass circuit for the 3.3V
input voltage.

OUT3 and OUT4 Voltage Adjustability

The GTL bus voltage (1.5V, OUT3) and the chip set and/or
cache memory voltage (1.8V, OUT4) are internally set for
simple, low-cost implementation in typical Intel motherboard
architectures. However, if different voltage settings are
desired for these two outputs, the FIX pin provides the
necessary adaptability. Left open (NC), this pin sets the fixed
output voltages described above. Grounding this pin allows
both output voltages to be set by means of external resistor
dividers as shown in Figure 6.

Application Guidelines

Soft-Start Interval

Initially, the soft-start function clamps the error amplifier's
output of the PWM converter. This generates PHASE pulses
of increasing width that charge the output capacitor(s). After
the output voltage increases to approximately 70% of the set
value, the reference input of the error amplifier is clamped to
a voltage proportional to the SS pin voltage. The resulting
output voltages start-up as shown in Figure 2.

The soft-start function controls the output voltage rate of rise
to limit the current surge at start-up. The soft-start interval and
the surge current are programmed by the soft-start capacitor,
C

. Programming a faster soft-start interval increases the

peak surge current. The peak surge current occurs during the
initial output voltage rise to 70% of the set value.

TABLE 1. OUT1 VOLTAGE PROGRAM

PIN NAME

NOMINAL

DACOUT

VOLTAGE

VID4

VID3

VID2

VID1

VID0

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

1.80

1.85

1.90

1.95

2.00

2.05

2.00

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

NOTE: 0 = connected to GND, 1 = open or connected to 5V through
pull-up resistors.

DRIVE3

VSEN3

VSEN4

OUT4

OUT3

HIP6021A

OUT3

OUT4

+3.3V

DRIVE4

VAUX

FIX

OUT

--------

FIGURE 6. ADJUSTING THE OUTPUT VOLTAGE OF

OUTPUTS 3 AND 4

HIP6021A

Shutdown

The HIP6021A features a dedicated shutdown pin (SD). A
TTL-compatible, logic high signal applied to this pin shuts
down (disables) all four outputs and discharges the soft-start
capacitor. Following a shutdown, a logic low signal
re-enables the outputs through initiation of a new soft-start
cycle. Left open this pin will asses a logic low state, due to its
internal pull-down resistor, thus enabling normal operation of
all outputs.

The PWM output does not switch until the soft-start voltage
(V

) exceeds the oscillator's valley voltage. The references

on each linear's error amplifier are clamped to the soft-start
voltage. Holding the SS pin low (with an open drain or
collector signal) turns off all four regulators.

Layout Considerations

MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. The voltage
spikes can degrade efficiency, radiate noise into the circuit,
and lead to device over-voltage stress. Careful component
layout and printed circuit design minimizes the voltage
spikes in the converter. Consider, as an example, the turn-
off transition of the upper PWM MOSFET. Prior to turn-off,
the upper MOSFET was carrying the full load current.
During the turn-off, current stops flowing in the upper
MOSFET and is picked up by the lower MOSFET or
Schottky diode. Any inductance in the switched current
path generates a large voltage spike during the switching
interval. Careful component selection, tight layout of the
critical components, and short, wide circuit traces minimize
the magnitude of voltage spikes. See Application Note
AN9836 for evaluation board drawings of the component
placement and the printed circuit board layout of a typical
application.

There are two sets of critical components in a DC-DC
converter using a HIP6021A controller. The switching power
components are the most critical because they switch large
amounts of energy, and as such, they tend to generate
equally large amounts of noise. The critical small signal
components are those connected to sensitive nodes or
those supplying critical bypass current.

The power components and the controller IC should be
placed first. Locate the input capacitors, especially the high-
frequency ceramic decoupling capacitors, close to the power
switches. Locate the output inductor and output capacitors
between the MOSFETs and the load. Locate the PWM
controller close to the MOSFETs.

The critical small signal components include the bypass
capacitor for VCC and the soft-start capacitor, C

. Locate

these components close to their connecting pins on the
control IC. Minimize any leakage current paths from SS
node, since the internal current source is only 28

A multi-layer printed circuit board is recommended.
Figure 7 shows the connections of the critical components
in the converter. Note that the capacitors C

and C

OUT

each represent numerous physical capacitors. Dedicate
one solid layer for a ground plane and make all critical
component ground connections with vias to this layer.
Dedicate another solid layer as a power plane and break
this plane into smaller islands of common voltage levels.
The power plane should support the input power and
output power nodes. Use copper filled polygons on the top
and bottom circuit layers for the PHASE nodes, but do not
unnecessarily oversize these particular islands. Since the
PHASE nodes are subjected to very high dV/dt voltages,
the stray capacitor formed between these islands and the
surrounding circuitry will tend to couple switching noise.
Use the remaining printed circuit layers for small signal
wiring. The wiring traces from the control IC to the
MOSFET gate and source should be sized to carry 2A peak
currents.

PWM Controller Feedback Compensation

The PWM controller uses voltage-mode control for output
regulation. This section highlights the design consideration
for a PWM voltage-mode controller. Apply the methods and
considerations only to the PWM controller.

Figure 8 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V

OUT

) is regulated to the Reference voltage level. The

reference voltage level is the DAC output voltage
(DACOUT). The error amplifier (Error Amp) output (V

E/A

) is

compared with the oscillator (OSC) triangular wave to
provide a pulse-width modulated (PWM) wave with an
amplitude of V

at the PHASE node. The PWM wave is

smoothed by the output filter (L

and C

The modulator transfer function is the small-signal transfer
function of V

OUT

E/A

. This function is dominated by a DC

Gain, given by V

OSC

, and shaped by the output filter,

with a double pole break frequency at F

and a zero

at F

ESR

Modulator Break Frequency Equations

The compensation network consists of the error amplifier
(internal to the HIP6021A) and the impedance networks Z

and Z

. The goal of the compensation network is to provide

a closed loop transfer function with high 0dB crossing
frequency (f

0dB

) and adequate phase margin. Phase margin

is the difference between the closed loop phase at f

0dB

and

180 degrees. The equations below relate the compensation
network's poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 7. Use these guidelines for
locating the poles and zeros of the compensation network:

----------------------------------------

ESR

-----------------------------------------

HIP6021A

1. Pick Gain (R2/R1) for desired converter bandwidth

2. Place 1

Zero Below Filter's Double Pole (~75% F

)

3. Place 2

Zero at Filter's Double Pole

4. Place 1

Pole at the ESR Zero

5. Place 2

Pole at Half the Switching Frequency

6. Check Gain against Error Amplifier's Open-Loop Gain

7. Estimate Phase Margin - Repeat if Necessary

Figure 9 shows an asymptotic plot of the DC-DC converter's
gain vs frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown in Figure 8. Using the above guidelines
should yield a Compensation Gain similar to the curve plotted.
The gain. Check the compensation gain at F

with the

capabilities of the error amplifier. The Closed Loop Gain is
constructed on the log-log graph of Figure 9 by adding the
Modulator Gain (in dB) to the Compensation Gain (in dB). This
is equivalent to multiplying the modulator transfer function to
the compensation transfer function and plotting the gain.

The compensation gain uses external impedance networks
Z

and Z

to provide a stable, high bandwidth (BW) overall

loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45

degrees. Include worst case component variations when
determining phase margin.

Compensation Break Frequency Equations

FIGURE 7. PRINTED CIRCUIT BOARD POWER PLANES AND

ISLANDS

OUT1

+12V

VCC

VIA CONNECTION TO GROUND PLANE

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT PLANE LAYER

OUT1

CR1

HIP6021A

OUT2

OUT3

+5V

PGND

LGATE1

UGATE1

PHASE1

DRIVE3

KEY

GND

VCC

DRIVE2

OCSET1

OUT4

DRIVE4

+3.3V

OUT3

OUT4

+3.3V

FIGURE 8. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

OUT

OSC

REFERENCE

ESR

OSC

ERROR
AMP

PWM

DRIVER

(PARASITIC)

DACOUT

COMP

OUT

HIP6021A

COMP

DRIVER

DETAILED COMPENSATION COMPONENTS

PHASE

E/A

-----------------------------------

(

)

-------------------------------------------------------

C 1

----------------------

-------------------------------------------------------

C 3

-----------------------------------

FIGURE 9. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

100

-20

-40

-60

10M

100K

10K

100

OPEN LOOP

ERROR AMP GAIN

ESR

COMPENSATION

GAIN (

FREQUENCY (Hz)

GAIN

MODULATOR

GAIN

CLOSED LOOP
GAIN

------------

log

R2
R1

--------

log

HIP6021A

Component Selection Guidelines

Output Capacitors

The output capacitors for each output have unique
requirements. In general, the output capacitors should be
selected to meet the dynamic regulation requirements.
Additionally, the PWM converters require an output capacitor
to filter the current ripple. The load transient for the
microprocessor core requires high quality capacitors to
supply the high slew rate (di/dt) current demands.

PWM Output

Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
current and slow the load rate-of-change seen by the bulk
capacitors. The bulk filter capacitor values are generally
determined by the ESR (effective series resistance) and
voltage rating requirements rather than actual capacitance
requirements.

High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.

Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor's ESR determines the output ripple voltage and
the initial voltage drop following a high slew-rate transient's
edge. An aluminum electrolytic capacitor's ESR value is
related to the case size with lower ESR available in larger
case sizes. However, the equivalent series inductance (ESL)
of these capacitors increases with case size and can reduce
the usefulness of the capacitor to high slew-rate transient
loading. Unfortunately, ESL is not a specified parameter. Work
with your capacitor supplier and measure the capacitor's
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.

Linear Output Capacitors

The output capacitors for the linear regulators provide
dynamic load current. The linear controllers use dominant
pole compensation integrated into the error amplifier and are
insensitive to output capacitor selection. Output capacitors
should be selected for transient load regulation.

PWM Output Inductor

The PWM converter requires an output inductor. The output
inductor is selected to meet the output voltage ripple
requirements and sets the converter's response time to a
load transient. The inductor value determines the converter's
ripple current and the ripple voltage is a function of the ripple
current. The ripple voltage and current are approximated by
the following equations:

Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values increase
the converter's response time to a load transient.

One of the parameters limiting the converter's response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
HIP6021A will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
interval required to slew the inductor current from an initial
current value to the post-transient current level. During this
interval the difference between the inductor current and the
transient current level must be supplied by the output
capacitor(s). Minimizing the response time can minimize the
output capacitance required.

The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:

where: I

TRAN

is the transient load current step, t

RISE

is the

response time to the application of load, and t

FALL

is the

response time to the removal of load. Be sure to check both
of these equations at the minimum and maximum output
levels for the worst case response time.

Input Capacitors

The important parameters for the bulk input capacitors are
the voltage rating and the RMS current rating. For reliable
operation, select bulk input capacitors with voltage and
current ratings above the maximum input voltage and largest
RMS current required by the circuit. The capacitor voltage
rating should be at least 1.25 times greater than the
maximum input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 of the summation of the DC load current.

Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use ceramic capacitance
for the high frequency decoupling and bulk capacitors to
supply the RMS current. Small ceramic capacitors can be
placed very close to the upper MOSFET to suppress the
voltage induced in the parasitic circuit impedances.

For a through-hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX
or equivalent) may be needed. For surface mount designs,
solid tantalum capacitors can be used, but caution must be
exercised with regard to the capacitor surge current rating.
These capacitors must be capable of handling the surge-
current at power-up. The TPS series available from AVX, and
the 593D series from Sprague are both surge current tested.

OUT

--------------------------------

OUT

----------------

OUT

ESR

RISE

TRAN

OUT

--------------------------------

FALL

TRAN

OUT

-------------------------------

HIP6021A

MOSFET Considerations

The HIP6021A requires 5 external transistors. Two N-Channel
MOSFETs are used in the synchronous-rectified buck
topology of PWM1 converter. It is recommended that the
AGP linear regulator pass element be a N-Channel
MOSFET as well. The GTL and memory linear controllers
can also each drive a MOSFET or a NPN bipolar as a pass
transistor. All these transistors should be selected based
upon r

DS(ON)

, current gain, saturation voltages, gate supply

requirements, and thermal management considerations.

PWM MOSFETs

In high-current PWM applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The power dissipation includes two
loss components; conduction loss and switching loss. These
losses are distributed between the upper and lower
MOSFETs according to duty factor (see the equations
below). The conduction losses are the main component of
power dissipation for the lower MOSFETs. Only the upper
MOSFET has significant switching losses, since the lower
device turns on and off into near zero voltage.

The equations below assume linear voltage-current
transitions and do not model power loss due to the reverse-
recovery of the lower MOSFET's body diode. The gate-
charge losses are dissipated by the HIP6021A and don't
heat the MOSFETs. However, large gate-charge increases
the switching time, t

which increases the upper MOSFET

switching losses. Ensure that both MOSFETs are within their
maximum junction temperature at high ambient temperature
by calculating the temperature rise according to package
thermal-resistance specifications. A separate heatsink may
be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.

The r

DS(ON)

is different for the two equations above even if

the same device is used for both. This is because the gate
drive applied to the upper MOSFET is different than the
lower MOSFET. Figure 10 shows the gate drive where the
upper MOSFET's gate-to-source voltage is approximately
VCC less the input supply. For +5V main power and
+12VDC for the bias, the gate-to-source voltage of Q1 is 7V.
The lower gate drive voltage is +12VDC. A logic-level
MOSFET is a good choice for Q1 and a logic-level MOSFET
can be used for Q2 if its absolute gate-to-source voltage
rating exceeds the maximum voltage applied to VCC.

Rectifier CR1 is a clamp that catches the negative inductor
swing during the dead time between the turn off of the lower
MOSFET and the turn on of the upper MOSFET. The diode
must be a Schottky type to prevent the lossy parasitic
MOSFET body diode from conducting. It is acceptable to
omit the diode and let the body diode of the lower MOSFET
clamp the negative inductor swing, but efficiency could drop
one or two percent as a result. The diode's rated reverse
breakdown voltage must be greater than the maximum input
voltage.

Linear Controller Transistors

The main criteria for selection of transistors for the linear
regulators is package selection for efficient removal of heat.
The power dissipated in a linear regulator is:

Select a package and heatsink that maintains the junction
temperature below the rating with a the maximum expected
ambient temperature.

When selecting bipolar NPN transistors for use with the
linear controllers, insure the current gain at the given
operating VCE is sufficiently large to provide the desired
output load current when the base is fed with the minimum
driver output current.

UPPER

DS ON

(

)

OUT

------------------------------------------------------------

----------------------------------------------------

LOWER

DS ON

(

)

OUT

(

)

---------------------------------------------------------------------------------

FIGURE 10. UPPER GATE DRIVE - DIRECT V

DRIVE OPTION

+12V

PGND

HIP6021A

GND

LGATE

UGATE

PHASE

VCC

+5V OR LESS

NOTE:

NOTE:
V

-5V

CR1

LINEAR

OUT

(

)

HIP6021A

HIP6021A DC-DC Converter Application Circuit

Figure 11 shows an application circuit of a power supply for a
microprocessor computer system. The power supply provides
the microprocessor core voltage (VOUT1), the AGP bus
voltage (VOUT2), the GTL bus voltage (VOUT3), and the
memory voltage (VOUT4) from +3.3V, +5VDC, and +12VDC.

For detailed information on the circuit, including a Bill-of-
Materials and circuit board description, see Application Note
AN9836. Also see Intersil's web page (http://www.intersil.com)
or Intersil AnswerFAX (407-724-7800) Document No. 99836 for
the latest information.

VID1

VID2

VID3

VID4

GND

VCC

+5V

VID0

+12V

PGND

VSEN1

PGOOD

LGATE

UGATE

OCSET

PHASE

Q1, 2

POWERGOOD

COMP

OUT2

VSEN2

DRIVE2

DRIVE3

VSEN3

DRIVE4

C25, 26

OUT3

OUT4

C23, 24

C12-19

HIP6021A

C1-6

OUT1

C20

C21

C22

C27

2x 1000

2x1000

C10, 11
2x1000

6 x1000

1000pF

8 x1000

0.1

4.2

0.22

10pF

2.7nF

10.2K

1.62K

GND

(3.3V

OR 1.5V)

(1.5V)

(1.8V)

VSEN4

TYPEDET

SELECT

+3.3V

499K

150K

FIX

1.0K

FAULT/RT

VAUX

HUF76107D3S

HUF76121D3S

2xHUF76143S3S

(1.3V-3.5V)

FIGURE 11. POWER SUPPLY APPLICATION CIRCUIT FOR A MICROPROCESSOR COMPUTER SYSTEM

HIP6021A

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

Sales Office Headquarters

NORTH AMERICA
Intersil Corporation
7585 Irvine Center Drive
Suite 100
Irvine, CA 92618
TEL: (949) 341-7000
FAX: (949) 341-7123

Intersil Corporation
2401 Palm Bay Rd.
Palm Bay, FL 32905
TEL: (321) 724-7000
FAX: (321) 724-7946

EUROPE
Intersil Europe Sarl
Ave. William Graisse, 3
1006 Lausanne
Switzerland
TEL: +41 21 6140560
FAX: +41 21 6140579

ASIA
Intersil Corporation
Unit 1804 18/F Guangdong Water Building
83 Austin Road
TST, Kowloon Hong Kong
TEL: +852 2723 6339
FAX: +852 2730 1433

HIP6021A

Small Outline Plastic Packages (SOIC)

NOTES:

1. Symbols are defined in the "MO Series Symbol List" in Section 2.2

of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension "D" does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.

4. Dimension "E" does not include interlead flash or protrusions. In-

terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

6. "L" is the length of terminal for soldering to a substrate.

7. "N" is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width "B", as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are not necessarily exact.

INDEX
AREA

-B-

0.25(0.010)

C A

B S

-A-

-C-

SEATING PLANE

0.10(0.004)

h x 45

0.25(0.010)

M28.3

(JEDEC MS-013-AE ISSUE C)

28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

SYMBOL

INCHES

MILLIMETERS

NOTES

MIN

MAX

MIN

MAX

0.0926

0.1043

2.35

2.65

0.0040

0.0118

0.10

0.30

0.013

0.0200

0.33

0.51

0.0091

0.0125

0.23

0.32

0.6969

0.7125

17.70

18.10

0.2914

0.2992

7.40

7.60

0.05 BSC

1.27 BSC

0.394

0.419

10.00

10.65

0.01

0.029

0.25

0.75

0.016

0.050

0.40

1.27

Rev. 0 12/93

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HIP6021ACB-T

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HIP6021ACB-T