6-134
March 1997
HM-6504/883
4096 x 1 CMOS RAM
Features
This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
Low Power Standby . . . . . . . . . . . . . . . . . . . 125
W Max
Low Power Operation . . . . . . . . . . . . . 35mW/MHz Max
Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min
TTL Compatible Input/Output
Three-State Output
Standard JEDEC Pinout
Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max
18 Pin Package for High Density
On-Chip Address Register
Gated Inputs - No Pull Up or Pull Down Resistors
Required
Description
The HM-6504/883 is a 4096 x 1 static CMOS RAM
fabricated using self-aligned silicon gate technology. The
device utilizes synchronous circuitry to achieve high perfor-
mance and low power operation.
On-chip latches are provided for addresses, data input and
data output allowing efficient interfacing with microprocessor
systems. The data output can be forced to a high impedance
state for use in expanded memory arrays.
Gated inputs allow lower operating current and also elimi-
nate the need for pull up or pull down resistors. The
HM-6504/883 is a fully static RAM and may be maintained in
any state for an indefinite period of time.
Data retention supply voltage and supply current are guaran-
teed over temperature.
Ordering Information
Pinout
HM-6504/883 (CERDIP)
TOP VIEW
PACKAGE
TEMPERATURE RANGE
200ns
300ns
PKG. NO
CERDIP
-55
o
C to +125
o
C
HM1-6504B/883
HM1-6504/883
F18.3
PIN
DESCRIPTION
A
Address Input
E
Chip Enable
W
Write Enable
D
Data Input
Q
Data Output
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1
VCC
A7
A8
A9
A10
A11
D
A6
E
A0
A1
A2
A3
A4
A5
W
Q
GND
File Number
2993.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
6-135
Functional Diagram
NOTES:
1. All lines active high-positive logic.
2. Three-state Buffers: A high
output active.
3. Control and Data Latches: L low
Q = D and Q latches on rising edge of L.
4. Address Latches: Latch on falling edge of E.
5. Gated Decoders: Gate on rising edge of G.
A
6
A
6
G
64 x 64
MATRIX
64
GATED COLUMN
DECODER AND
DATA I/O
A
L
Q
L
Q
D
L
Q
D
LATCH
LATCH
LATCH
A
LATCHED
ADDRESS
REGISTER
L
LATCHED
ADDRESS
REGISTER
G
GATED
ROW
DECODER
A
6
6
64
L
D
Q
D
L
Q
A8
A7
A6
A0
A1
A2
LSB
E
W
D
A
LSB A11 A5 A4 A3 A9 A10
LATCH
HM-6504/883
6-136
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance
JA
JC
CERDIP Package . . . . . . . . . . . . . . . .
75
o
C/W
15
o
C/W
Maximum Storage Temperature Range . . . . . . . . .-65
o
C to +150
o
C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300
o
C
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6910 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +0.8V
Input High Voltage . . . . . . . . . . . . . . . . . . . VCC -2.0V to VCC +0.3V
TABLE 1. HM-6504/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER
SYMBOL
(NOTE 1)
CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Output Low Voltage
VOL
VCC = 4.5V,
IOL = 2mA
1, 2, 3
-55
o
C
T
A
+125
o
C
-
0.4
V
Output High Voltage
VOH
VCC = 4.5V,
IOH = -1.0mA
1, 2, 3
-55
o
C
T
A
+125
o
C
2.4
-
V
Input Leakage Current
II
VCC = 5.5V,
VI = GND or VCC
1, 2, 3
-55
o
C
T
A
+125
o
C
-1.0
+1.0
A
Output Leakage Current
IOZ
VCC = 5.5V,
VO = GND or VCC
1, 2, 3
-55
o
C
T
A
+125
o
C
-1.0
+1.0
A
Data Retention Supply Current
ICCDR
VCC = 2.0V,
E = VCC,
IO = 0mA
1, 2, 3
-55
o
C
T
A
+125
o
C
-
25
A
Operating Supply Current
ICCOP
VCC = 5.5V,
(Note 2),
E = 1MHz,
IO = 0mA
1, 2, 3
-55
o
C
T
A
+125
o
C
-
7
mA
Standby Supply Current
ICCSB
VCC = 5.0V,
E = VCC -0.3V,
IO = 0mA
1, 2, 3
-55
o
C
T
A
+125
o
C
-
50
A
NOTES:
1. All voltage referenced to device GND.
2. Typical derating 1.5mA/MHz increase in ICCOP.
HM-6504/883
6-137
TABLE 2. HM-6504/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER
SYMBOL
(NOTES 1, 2)
CONDITIONS
GROUP
A SUB-
GROUPS
TEMPERA-
TURE
LIMITS
UNITS
HM-6504S/883
HM-6504B/883
HM-6504/883
MIN
MAX
MIN
MAX
MIN
MAX
Chip Enable
Access Time
(1)
TELQV
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
-
120
-
200
-
300
ns
Address Access
Time
(2)
TAVQV
VCC = 4.5 and
5.5V, Note 3
9, 10, 11
-55
o
C
T
A
+125
o
C
-
120
-
220
-
320
ns
Chip Enable
Pulse Negative
Width
(5)
TELEH
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
120
-
200
-
300
-
ns
Chip Enable
Pulse Positive
Width
(6)
TEHEL
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
50
-
90
-
120
-
ns
Address Setup
Time
(7)
TAVEL
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
0
-
20
-
20
-
ns
Address Hold
Time
(8)
TELAX
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
40
-
50
-
50
-
ns
Write Enable
Pulse Width
(9)
TWLWH
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
20
-
60
-
80
-
ns
Write Enable
Pulse Setup
Time
(10)
TWLEH
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
70
-
150
-
200
-
ns
Early Write Pulse
Setup Time
(11)
TWLEL
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
0
-
0
-
0
-
ns
Early Write Pulse
Hold Time
(13)
TELWH
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
40
-
60
-
80
-
ns
Data Setup Time
(14)
TDVWL
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
0
-
0
-
0
-
ns
Early Write Data
Setup Time
(15)
TDVEL
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
0
-
0
-
0
-
ns
Data Hold Time
(16)
TWLDX
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
25
-
60
-
80
-
ns
Early Write Data
Hold Time
(17)
TELDX
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
25
-
60
-
80
-
ns
Read or Write
Cycle Time
(18)
TELEL
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
T
A
+125
o
C
170
-
290
-
420
-
ns
NOTES:
1. All voltages referenced to device GND.
2. Input pulse levels: 0.8V to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load:
1TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
3. TAVQV = TELQV + TAVEL.
HM-6504/883
6-138
f
TABLE 3. HM-6504/883 ELECTRICAL PERFORMANCE SPECIFICATIONS
PARAMETER
SYMBOL
CONDITIONS
NOTE
TEMPERATURE
HM-6504S/883
UNITS
LIMITS
MIN
MAX
Input Capacitance
CI
VCC = Open, f = 1MHz, All
Measurements Referenced
to Device Ground
1
T
A
= +25
o
C
-
8
pF
Output
Capacitance
CO
VCC = Open, f = 1MHz, All
Measurements Referenced
to Device Ground
1
T
A
= +25
o
C
-
10
pF
Chip Enable Output
Disable Time
(3)
TELQX
VCC = 4.5 and 5.5V
1
-55
o
C
T
A
+125
o
C
5
-
ns
Chip Enable Output
Disable Time
(4)
TEHQZ
VCC = 4.5 and 5.5V
HM-6504S/883
1
-55
o
C
T
A
+125
o
C
-
50
ns
VCC = 4.5 and 5.5V
HM-6504B/883
1
-55
o
C
T
A
+125
o
C
-
80
ns
VCC = 4.5 and 5.5V
HM-6504/883
1
-55
o
C
T
A
+125
o
C
-
100
ns
Write Enable Read
Mode Setup Time
(12)
TWHEL
VCC = 4.5 and 5.5V
1
-55
o
C
T
A
+125
o
C
0
-
ns
High Level Output
Voltage
VOHL
VCC = 4.5V, IO = -100
A
1
-55
o
C
T
A
+125
o
C
VCC -
0.4
-
V
NOTE:
1. The parameters listed in Table 3 are controlled via design, or process parameters are characterized upon initial design and after major
process and/or design changes.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
METHOD
SUBGROUPS
Initial Test
100%/5004
-
Interim Test
100%/5004
1, 7, 9
PDA
100%/5004
1
Final Test
100%/5004
2, 3, 8A, 8B, 10, 11
Group A
Samples/5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Groups C & D
Samples/5005
1, 7, 9
HM-6504/883
6-139
Timing Waveforms
The address information is latched in the on-chip registers
on the falling edge of E (T = 0). Minimum address set up and
hold time requirements must be met. After the required hold
time, the addresses may change state without affecting
device operation. During time (T = 1) the output becomes
enabled but the data is not valid until during time (T = 2). W
must remain high for the read cycle. After the output data
has been read, E may return high (T = 3). This will disable
the output buffer and all input, and ready the RAM for the
next memory cycle (T = 4).
TRUTH TABLE
TIME REFERENCE
INPUTS
OUTPUT
FUNCTION
E
W
A
Q
-1
H
X
X
Z
Memory Disabled
0
H
V
Z
Cycle Begins, Addresses are Latched
1
L
H
X
X
Output Enabled
2
L
H
X
V
Output Valid
3
H
X
V
Read Accomplished
4
H
X
X
Z
Prepare for Next Cycle (Same as -1)
5
H
V
Z
Cycle Ends, Next Cycle Begins (Same as 0)
A
(7)
NEXT ADD
TAVEL
(8)
TELAX
(7)
TAVEL
(4) TEHQZ
HIGH Z
VALID DATA OUTPUT
(3)
TELQX
HIGH Z
E
Q
W
HIGH
-1
TIME
0
1
2
3
4
5
REFERENCE
(6)
TEHEL
TELEL (18)
(5)
TELEH
(6)
TEHEL
(1) TELQV
FIGURE 1. READ CYCLE
ADD VALID
HM-6504/883
6-140
Timing Waveforms
(Continued)
The early write cycle is the only cycle where the output is
guaranteed not to become active. On the falling edge of E
(T = 0), the addresses, the write signal, and the data input
are latched in on-chip registers. The logic value of W at the
time E falls determines the state of the output buffer for that
cycle. Since W is low when E falls, the output buffer is
latched into the high impedance state and will remain in that
state until E returns high (T = 2). For this cycle, the data
input is latched by E going low; therefore, data set up and
hold times should be referenced to E. When E (T = 2)
returns to the high state, the output buffer and all inputs are
disabled and all signals are unlatched. The device is now
ready for the next cycle.
(7)
TAVEL
(7)
TAVEL
(11)
TWLEL
(15)
TDVEL
HIGH-Z
NEXT DATA
(11)
TWLEL
(15)
TDVEL
DATA VALID
HIGH-Z
-1
TIME
0
1
2
3
4
REFERENCE
(8)
TELAX
NEXT ADD
(18) TELEL
(6) TEHEL
(5) TELEH
(6)
TEHEL
(13)
TELWH
(17)
TELDX
D
W
Q
E
A
FIGURE 2. EARLY WRITE CYCLE
ADD VALID
TRUTH TABLE
TIME REFERENCE
INPUTS
OUTPUT
FUNCTION
E
W
A
D
Q
-1
H
X
X
X
Z
Memory Disabled
0
L
V
V
Z
Cycle Begins, Addresses are Latched
1
L
X
X
X
Z
Write in Progress Internally
2
X
X
X
Z
Write Completed
3
H
X
X
X
Z
Prepare for Next Cycle (Same as -1)
4
L
V
V
Z
Cycle Ends, Next Cycle Begins (Same as 0)
HM-6504/883
6-141
Timing Waveforms
(Continued)
The late write cycle is a cross between the early write cycle
and the read-modify-write cycle.
Recall that in the early write, the output is guaranteed to
remain high impedance, and in the read-modify-write, the
output is guaranteed valid at access time. The late write is
between these two cases. With this cycle the output may
become active, and may become valid data, or may remain
active but undefined. Valid data is written into the RAM if
data setup, data hold, write setup and write pulse widths are
observed.
(7)
TAVEL
(8)
TELAX
(7)
TAVEL
(14)
TDVWL
(16)
TWLDX
DATA VALID
(4)
TEHQZ
HIGH Z
A
E
W
D
Q
-1
TIME
0
1
2
3
4
5
REFERENCE
(18) TELEL
(5) TELEH
(6)
TEHEL
(6)
TEHEL
(10)
TWLEH
(9)
TWLWH
(3)
TELQX
FIGURE 3. LATE WRITE CYCLE
NEXT ADD
ADD VALID
HIGH Z
TRUTH TABLE
TIME
REFERENCE
INPUTS
OUTPUTS
FUNCTION
E
W
A
D
Q
-1
H
X
X
X
Z
Memory Disabled
0
H
V
X
Z
Cycle Begins, Addresses are Latched
1
L
X
V
X
Write Begins, Data is Latched
2
L
H
X
X
X
Write In Progress Internally
3
H
X
X
X
Write Completed
4
H
X
X
X
Z
Prepare for Next Cycle (Same as -1)
5
H
V
X
Z
Cycle Ends, Next Cycle Begins (Same as 0)
HM-6504/883
6-142
Test Load Circuit
NOTE:
1. Test head capacitance includes stray and jig capacitance.
Burn-In Circuit
HM-6504/883 CERDIP
NOTES:
All resistors 47k
5%.
F0 = 100kHz
10%.
F1 = F0
2, F2 = F1
2, F3 = F2
2 . . . F12 = F11
2.
VCC = 5.5V
0.5V.
VIH = 4.5V
10%.
VIL = -0.2V to +0.4V.
C1 = 0.01
F Min.
DUT
1.5V
IOL
IOH
+
-
(NOTE 1) CL
EQUIVALENT CIRCUIT
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1
A2
A3
A4
A5
Q
GND
VCC
A7
A9
A10
A11
D
C1
VCC
W
E
A0
A1
A6
A8
F3
F4
F5
F6
F7
F8
F2
F1
F9
F10
F11
F12
F13
F14
F2
F0
HM-6504/883
6-143
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Die Characteristics
DIE DIMENSIONS:
136 x 169 x 19
1mils
METALLIZATION:
Type: Si - Al
Thickness: 11k
2k
GLASSIVATION:
Type: SiO
2
Thickness: 8k
1k
WORST CASE CURRENT DENSITY:
1.79 x 10
5
A/cm
2
LEAD TEMPERATURE (10s soldering):
300
o
C
Metallization Mask Layout
HM-6504/883
NOTE:
1. Pin numbers correspond to DIP Package only.
A2
A3
A1
A0
VCC
A6
A7
A8
A9
A10
A11
D
E
GND
W
Q
A5
A4
HM-6504/883
PDF 
ZIP