1
FN4910.8
ICL3221E, ICL3222E, ICL3223E, ICL3232E,
ICL3241E, ICL3243E
+/-15kV ESD Protected, +3V to +5.5V,
1Microamp, 250kbps, RS-232
Transmitters/Receivers
The Intersil ICL32XXE devices are 3.0V to 5.5V powered
RS-232 transmitters/receivers which meet ElA/TIA-232 and
V.28/V.24 specifications, even at V
CC
= 3.0V. Additionally,
they provide
15kV ESD protection (IEC 1000-4-2 Air Gap
and Human Body Model) on transmitter outputs and receiver
inputs (RS-232 pins). Targeted applications are PDAs,
Palmtops, and notebook and laptop computers where the
low operational, and even lower standby, power
consumption is critical. Efficient on-chip charge pumps,
coupled with manual and automatic powerdown functions
(except for the ICL3232E), reduce the standby supply
current to a 1
A trickle. Small footprint packaging, and the
use of small, low value capacitors ensure board space
savings as well. Data rates greater than 250kbps are
guaranteed at worst case load conditions. This family is fully
compatible with 3.3V-only systems, mixed 3.3V and 5.0V
systems, and 5.0V-only systems.
The ICL324XE are 3-driver, 5-receiver devices that provide
a complete serial port suitable for laptop or notebook
computers. Both devices also include noninverting always-
active receivers for "wake-up" capability.
The ICL3221E, ICL3223E and ICL3243E, feature an
automatic powerdown function which powers down the on-
chip power-supply and driver circuits. This occurs when an
attached peripheral device is shut off or the RS-232 cable is
removed, conserving system power automatically without
changes to the hardware or operating system. These
devices power up again when a valid RS-232 voltage is
applied to any receiver input.
Table 1 summarizes the features of the devices represented
by this data sheet, while Application Note AN9863
summarizes the features of each device comprising the
ICL32XXE 3V family.
Features
ESD Protection for RS-232 I/O Pins to
15kV (IEC1000)
Drop in Replacements for MAX3221E, MAX3222E,
MAX3223E, MAX3232E, MAX3241E, MAX3243E,
SP3243E
ICL3221E is Low Power, Pin Compatible Upgrade for 5V
MAX221E
ICL3222E is Low Power, Pin Compatible Upgrade for 5V
MAX242E, and SP312E
ICL3232E is Low Power Upgrade for HIN232E/ICL232
and Pin Compatible Competitor Devices
Meets EIA/TIA-232 and V.28/V.24 Specifications at 3V
Latch-Up Free
On-Chip Voltage Converters Require Only Four External
0.1
F Capacitors
Manual and Automatic Powerdown Features
Guaranteed Mouse Driveability (ICL324XE Only)
Receiver Hysteresis For Improved Noise Immunity
Guaranteed Minimum Data Rate . . . . . . . . . . . . . 250kbps
Guaranteed Minimum Slew Rate . . . . . . . . . . . . . . . 6V/
s
Wide Power Supply Range . . . . . . . Single +3V to +5.5V
Low Supply Current in Powerdown State. . . . . . . . . . .1
A
Applications
Any System Requiring RS-232 Communication Ports
- Battery Powered, Hand-Held, and Portable Equipment
- Laptop Computers, Notebooks, Palmtops
- Modems, Printers and other Peripherals
- Digital Cameras
- Cellular/Mobile Phones
Related Literature
Technical Brief TB363 "Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)"
TABLE 1. SUMMARY OF FEATURES
PART
NUMBER
NO. OF
Tx.
NO. OF
Rx.
NO. OF
MONITOR Rx.
(R
OUTB
)
DATA
RATE
(kbps)
Rx. ENABLE
FUNCTION?
READY
OUTPUT?
MANUAL
POWER-
DOWN?
AUTOMATIC
POWERDOWN
FUNCTION?
ICL3221E
1
1
0
250
YES
NO
YES
YES
ICL3222E
2
2
0
250
YES
NO
YES
NO
ICL3223E
2
2
0
250
YES
NO
YES
YES
ICL3232E
2
2
0
250
NO
NO
NO
NO
ICL3241E
3
5
2
250
YES
NO
YES
NO
ICL3243E
3
5
1
250
NO
NO
YES
YES
Data Sheet
June 2003
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
2
Ordering Information
(Note 1)
PART NO.
(BRAND)
TEMP.
RANGE (
o
C)
PACKAGE
PKG. NO.
ICL3221ECA
0 to 70
16 Ld SSOP
M16.209
ICL3221EIA
-40 to 85
16 Ld SSOP
M16.209
ICL3221ECV
0 to 70
16 Ld TSSOP
M16.173
ICL3222ECA
0 to 70
20 Ld SSOP
M20.209
ICL3222EIA
-40 to 85
20 Ld SSOP
M20.209
ICL3222ECB
0 to 70
18 Ld SOIC
M18.3
ICL3222EIB
-40 to 85
18 Ld SOIC
M18.3
ICL3222ECP
0 to 70
18 Ld PDIP
E18.3
ICL3222ECV
0 to 70
20 Ld TSSOP
M20.173
ICL3222EIV
-40 to 85
20 Ld TSSOP
M20.173
ICL3223ECA
0 to 70
20 Ld SSOP
M20.209
ICL3223EIA
-40 to 85
20 Ld SSOP
M20.209
ICL3223ECP
0 to 70
20 Ld PDIP
E20.3
ICL3223ECV
0 to 70
20 Ld TSSOP
M20.173
ICL3223EIV
-40 to 85
20 Ld TSSOP
M20.173
ICL3232ECA
0 to 70
16 Ld SSOP
M16.209
ICL3232EIA
-40 to 85
16 Ld SSOP
M16.209
ICL3232ECB
0 to 70
16 Ld SOIC
M16.3
ICL3232ECBN
0 to 70
16 Ld SOIC (N)
M16.15
ICL3232EIB
-40 to 85
16 Ld SOIC
M16.3
ICL3232EIBN
-40 to 85
16 Ld SOIC (N)
M16.15
ICL3232ECP
0 to 70
16 Ld PDIP
E16.3
ICL3232ECV-16
0 to 70
16 Ld TSSOP
M16.173
ICL3232EIV-16
-40 to 85
16 Ld TSSOP
M16.173
ICL3232ECV-20
0 to 70
20 Ld TSSOP
M20.173
ICL3232EIV-20
-40 to 85
20 Ld TSSOP
M20.173
ICL3241ECA
0 to 70
28 Ld SSOP
M28.209
ICL3241EIA
-40 to 85
28 Ld SSOP
M28.209
ICL3241ECB
0 to 70
28 Ld SOIC
M28.3
ICL3241EIB
-40 to 85
28 Ld SOIC
M28.3
ICL3241ECV
0 to 70
28 Ld TSSOP
M28.173
ICL3241EIV
-40 to 85
28 Ld TSSOP
M28.173
ICL3243ECA
0 to 70
28 Ld SSOP
M28.209
ICL3243ECAH-T
(ICL3243ECA)
0 to 70
28 Ld SSOP Tape
& Reel (Note 2)
M28.209
ICL3243EIA
-40 to 85
28 Ld SSOP
M28.209
ICL3243ECB
0 to 70
28 Ld SOIC
M28.3
ICL3243EIB
-40 to 85
28 Ld SOIC
M28.3
ICL3243ECV
0 to 70
28 Ld TSSOP
M28.173
ICL3243EIV
-40 to 85
28 Ld TSSOP
M28.173
NOTES:
1. Most surface mount devices are available on tape and reel; add
"-T" to suffix.
2. Compatible with high temperature (260
o
C) reflow soldering
processes.
Ordering Information
(Note 1)
PART NO.
(BRAND)
TEMP.
RANGE (
o
C)
PACKAGE
PKG. NO.
Pinouts
ICL3221E (SSOP, TSSOP)
TOP VIEW
ICL3222E (PDIP, SOIC)
TOP VIEW
EN
C1+
V+
C1-
C2+
C2-
V-
R1
IN
FORCEOFF
GND
T1
OUT
FORCEON
T1
IN
R1
OUT
V
CC
INVALID
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
EN
C1+
V+
C1-
C2+
C2-
V-
T2
OUT
R2
IN
SHDN
GND
T1
OUT
R1
IN
R1
OUT
T2
IN
V
CC
T1
IN
R2
OUT
18
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
9
ICL3221E , ICL3222E , ICL3223E , ICL3232E , ICL3241E, ICL3243E
3
ICL3222E (SSOP, TSSOP)
TOP VIEW
ICL3223E (PDIP, SSOP, TSSOP)
TOP VIEW
ICL3232E (PDIP, SOIC, SSOP, TSSOP-16)
TOP VIEW
ICL3232E (TSSOP-20)
TOP VIEW
ICL3241E (SOIC, SSOP, TSSOP)
TOP VIEW
ICL3243E (SOIC, SSOP, TSSOP)
TOP VIEW
Pinouts
(Continued)
EN
C1+
V+
C1-
C2+
C2-
V-
T2
OUT
R2
IN
SHDN
GND
T1
OUT
R1
IN
R1
OUT
T1
IN
NC
V
CC
NC
T2
IN
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
R2
OUT
EN
C1+
V+
C1-
C2+
C2-
V-
T2
OUT
R2
IN
FORCEOFF
GND
T1
OUT
R1
IN
R1
OUT
T1
IN
INVALID
V
CC
FORCEON
T2
IN
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
R2
OUT
C1+
V+
C1-
C2+
C2-
V-
T2
OUT
R2
IN
V
CC
T1
OUT
R1
IN
R1
OUT
T1
IN
R2
OUT
GND
T2
IN
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
NC
C1+
V+
C1-
C2+
C2-
V-
T2
OUT
R2
IN
NC
GND
T1
OUT
R1
IN
R1
OUT
T1
IN
NC
V
CC
T2
IN
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
NC
R2
OUT
C2+
C2-
V-
R1
IN
R2
IN
R3
IN
R4
IN
R5
IN
T1
OUT
T3
OUT
T3
IN
T2
IN
T1
IN
C1+
V
CC
GND
C1-
EN
R1
OUTB
R1
OUT
R2
OUT
R3
OUT
R4
OUT
R5
OUT
V+
SHDN
R2
OUTB
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
T2
OUT
C2+
C2-
V-
R1
IN
R2
IN
R3
IN
R4
IN
R5
IN
T1
OUT
T3
OUT
T3
IN
T2
IN
T1
IN
C1+
V
CC
GND
C1-
FORCEON
INVALID
R1
OUT
R2
OUT
R3
OUT
R4
OUT
R5
OUT
V+
FORCEOFF
R2
OUTB
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
T2
OUT
ICL3221E , ICL3222E , ICL3223E , ICL3232E , ICL3241E, ICL3243E
4
Pin Descriptions
PIN
FUNCTION
V
CC
System power supply input (3.0V to 5.5V).
V+
Internally generated positive transmitter supply (+5.5V).
V-
Internally generated negative transmitter supply (-5.5V).
GND
Ground connection.
C1+
External capacitor (voltage doubler) is connected to this lead.
C1-
External capacitor (voltage doubler) is connected to this lead.
C2+
External capacitor (voltage inverter) is connected to this lead.
C2-
External capacitor (voltage inverter) is connected to this lead.
T
IN
TTL/CMOS compatible transmitter Inputs.
T
OUT
15kV ESD Protected
,
RS-232 level (nominally
5.5V) transmitter outputs.
R
IN
15kV ESD Protected
,
RS-232 compatible receiver inputs.
R
OUT
TTL/CMOS level receiver outputs.
R
OUTB
TTL/CMOS level, noninverting, always enabled receiver outputs.
INVALID
Active low output that indicates if no valid RS-232 levels are present on any receiver input.
EN
Active low receiver enable control; doesn't disable R
OUTB
outputs.
SHDN
Active low input to shut down transmitters and on-board power supply, to place device in low power mode.
FORCEOFF Active low to shut down transmitters and on-chip power supply. This overrides any automatic circuitry and FORCEON (see Table 2).
FORCEON Active high input to override automatic powerdown circuitry thereby keeping transmitters active. (FORCEOFF must be high).
Typical Operating Circuits
ICL3221E
15
V
CC
T1
OUT
T1
IN
T
1
0.1
F
+0.1
F
+
0.1
F
11
13
2
4
3
7
V+
V-
C1+
C1-
C2+
C2-
+
0.1
F
5
6
R1
OUT
R1
IN
R
1
8
9
5k
C
1
C
2
+ C
3
C
4
EN
1
GND
+3.3V
+
0.1
F
14
TTL/CMOS
LOGIC LEVELS
RS-232
LEVELS
FORCEON
FORCEOFF
12
16
V
CC
10
INVALID
TO POWER
CONTROL LOGIC
+
C
3
(OPTIONAL CONNECTION, NOTE)
NOTE: THE NEGATIVE TERMINAL OF C
3
CAN BE CONNECTED TO EITHER V
CC
OR GND
ICL3221E , ICL3222E , ICL3223E , ICL3232E , ICL3241E, ICL3243E
5
ICL3222E
ICL3223E
Typical Operating Circuits
(Continued)
17
V
CC
T1
OUT
T2
OUT
T1
IN
T2
IN
T
1
T
2
0.1
F
+
0.1
F
+
0.1
F
12
11
15
8
2
4
3
7
V+
V-
C1+
C1-
C2+
C2-
+
0.1
F
5
6
R1
OUT
R1
IN
14
5k
R2
OUT
R2
IN
9
10
5k
13
C
1
C
2
+ C
3
C
4
EN
SHDN
1
GND
18
+3.3V
+
0.1
F
16
V
CC
TTL/CMOS
LOGIC LEVELS
RS-232
LEVELS
R
1
R
2
+
C
3
(OPTIONAL CONNECTION, NOTE)
NOTE: THE NEGATIVE TERMINAL OF C
3
CAN BE CONNECTED TO EITHER V
CC
OR GND
19
V
CC
T1
OUT
T2
OUT
T1
IN
T2
IN
T
1
T
2
0.1
F
+0.1
F
+
0.1
F
13
12
17
8
2
4
3
7
V+
V-
C1+
C1-
C2+
C2-
+
0.1
F
5
6
R1
OUT
R1
IN
16
5k
R2
OUT
R2
IN
9
10
5k
15
C
1
C
2
+ C
3
C
4
EN
1
GND
+3.3V
+ 0.1
F
18
TTL/CMOS
LOGIC LEVELS
RS-232
LEVELS
R
1
R
2
FORCEON
FORCEOFF
14
20
V
CC
11
INVALID
TO POWER
CONTROL LOGIC
ICL3221E , ICL3222E , ICL3223E , ICL3232E , ICL3241E, ICL3243E
6
ICL3232E
Typical Operating Circuits
(Continued)
16
V
CC
T1
OUT
T2
OUT
T1
IN
T2
IN
T
1
T
2
0.1
F
+
0.1
F
+
0.1
F
11
10
14
7
1
3
2
6
V+
V-
C1+
C1-
C2+
C2-
+
0.1
F
4
5
R1
OUT
R1
IN
13
5k
R2
OUT
R2
IN
8
9
5k
12
C
1
C
2
+ C
3
C
4
GND
+3.3V
+
0.1
F
15
TTL/CMOS
LOGIC LEVELS
RS-232
LEVELS
R
1
R
2
+
C
3
(OPTIONAL CONNECTION, NOTE)
NOTE: THE NEGATIVE TERMINAL OF C
3
CAN BE CONNECTED TO EITHER V
CC
OR GND
ICL3221E , ICL3222E , ICL3223E , ICL3232E , ICL3241E, ICL3243E
7
ICL3241E
ICL3243E
Typical Operating Circuits
(Continued)
26
V
CC
T1
OUT
T2
OUT
T3
OUT
T1
IN
T2
IN
T3
IN
T
1
T
2
T
3
0.1
F
+
0.1
F
+
0.1
F
14
13
9
10
12
11
28
24
27
3
V+
V-
C1+
C1-
C2+
C2-
+
0.1
F
1
2
R1
OUT
R1
IN
4
5k
R2
OUT
R2
IN
5
18
5k
R3
OUT
R3
IN
6
17
5k
R4
OUT
R4
IN
7
16
5k
R5
OUT
R5
IN
R
5
8
15
5k
19
R2
OUTB
C
1
C
2
+ C
3
C
4
EN
SHDN
23
GND
22
+3.3V
+
0.1
F
20
25
V
CC
TTL/CMOS
LOGIC
RS-232
LEVELS
RS-232
LEVELS
R1
OUTB
21
R
1
R
2
R
3
R
4
LEVELS
26
V
CC
T1
OUT
T2
OUT
T3
OUT
T1
IN
T2
IN
T3
IN
T
1
T
2
T
3
0.1
F
+
0.1
F
+
0.1
F
14
13
9
10
12
11
28
24
27
3
V+
V-
C1+
C1-
C2+
C2-
+
0.1
F
1
2
R1
OUT
R1
IN
4
5k
R2
OUT
R2
IN
5
18
5k
R3
OUT
R3
IN
6
17
5k
R4
OUT
R4
IN
7
16
5k
R5
OUT
R5
IN
R
5
8
15
5k
19
R2
OUTB
C
1
C
2
+ C
3
C
4
FORCEON
FORCEOFF
23
GND
22
+3.3V
+
0.1
F
20
25
V
CC
TTL/CMOS
LOGIC
RS-232
LEVELS
RS-232
LEVELS
R
1
R
2
R
3
R
4
21
INVALID
TO POWER
CONTROL
LEVELS
LOGIC
ICL3221E , ICL3222E , ICL3223E , ICL3232E , ICL3241E, ICL3243E
8
Absolute Maximum Ratings
Thermal Information
V
CC
to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
V- to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V
Input Voltages
T
IN
, FORCEOFF, FORCEON, EN, SHDN . . . . . . . . . -0.3V to 6V
R
IN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25V
Output Voltages
T
OUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.2V
R
OUT
, INVALID . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V
CC
+0.3V
Short Circuit Duration
T
OUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table
Operating Conditions
Temperature Range
ICL32XXECX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to 70
o
C
ICL32XXEIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Thermal Resistance (Typical, Note 3)
JA
(
o
C/W)
16 Ld PDIP Package . . . . . . . . . . . . . . . . . . . . . . . .
90
18 Ld PDIP Package . . . . . . . . . . . . . . . . . . . . . . . .
80
20 Ld PDIP Package . . . . . . . . . . . . . . . . . . . . . . . .
77
16 Ld Wide SOIC Package . . . . . . . . . . . . . . . . . . .
100
16 Ld Narrow SOIC Package. . . . . . . . . . . . . . . . . .
115
18 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . .
75
28 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . .
75
16 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . .
135
20 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . .
122
16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . .
145
20 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . .
140
28 Ld SSOP and TSSOP Packages . . . . . . . . . . . .
100
Moisture Sensitivity (see Technical Brief TB363)
ICL3243ECAH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 4
All Other Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
Maximum Junction Temperature (Plastic Package) . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300
o
C
(SOIC, SSOP, TSSOP - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3.
JA
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Test Conditions: V
CC
= 3V to 5.5V, C
1
- C
4
= 0.1
F; Unless Otherwise Specified.
Typicals are at T
A
= 25
o
C
PARAMETER
TEST CONDITIONS
TEMP
(
o
C)
MIN
TYP
MAX
UNITS
DC CHARACTERISTICS
Supply Current, Automatic
Powerdown
All R
IN
Open, FORCEON = GND, FORCEOFF = V
CC
(ICL3221E, ICL3223E, ICL3243E Only)
25
-
1.0
10
A
Supply Current, Powerdown
FORCEOFF = SHDN = GND (Except ICL3232E)
25
-
1.0
10
A
Supply Current,
Automatic Powerdown Disabled
All Outputs Unloaded,
FORCEON = FORCEOFF =
SHDN = V
CC
V
CC
= 3.0V, ICL3241-43
25
-
0.3
1.0
mA
V
CC
= 3.15V, ICL3221-32
25
-
0.3
1.0
mA
LOGIC AND TRANSMITTER INPUTS AND RECEIVER OUTPUTS
Input Logic Threshold Low
T
IN
, FORCEON, FORCEOFF, EN, SHDN
Full
-
-
0.8
V
Input Logic Threshold High
T
IN
, FORCEON,
FORCEOFF, EN, SHDN
V
CC
= 3.3V
Full
2.0
-
-
V
V
CC
= 5.0V
Full
2.4
-
-
V
Input Leakage Current
T
IN
, FORCEON, FORCEOFF, EN, SHDN
Full
-
0.01
1.0
A
Output Leakage Current
(Except ICL3232E)
FORCEOFF = GND or EN = V
CC
Full
-
0.05
10
A
Output Voltage Low
I
OUT
= 1.6mA
Full
-
-
0.4
V
Output Voltage High
I
OUT
= -1.0mA
Full
V
CC
-0.6 V
CC
-0.1
-
V
AUTOMATIC POWERDOWN (ICL3221E, ICL3223E, ICL3243E Only, FORCEON = GND, FORCEOFF = V
CC
)
Receiver Input Thresholds to
Enable Transmitters
ICL32XXE Powers Up (See Figure 6)
Full
-2.7
-
2.7
V
Receiver Input Thresholds to
Disable Transmitters
ICL32XXE Powers Down (See Figure 6)
Full
-0.3
-
0.3
V
INVALID Output Voltage Low
I
OUT
= 1.6mA
Full
-
-
0.4
V
INVALID Output Voltage High
I
OUT
= -1.0mA
Full
V
CC
-0.6
-
-
V
ICL3221E , ICL3222E , ICL3223E , ICL3232E , ICL3241E, ICL3243E
9
Receiver Threshold to Transmitters
Enabled Delay (t
WU
)
25
-
100
-
s
Receiver Positive or Negative
Threshold to INVALID High Delay
(t
INVH
)
25
-
1
-
s
Receiver Positive or Negative
Threshold to INVALID Low Delay
(t
INVL
)
25
-
30
-
s
RECEIVER INPUTS
Input Voltage Range
25
-25
-
25
V
Input Threshold Low
V
CC
= 3.3V
25
0.6
1.2
-
V
V
CC
= 5.0V
25
0.8
1.5
-
V
Input Threshold High
V
CC
= 3.3V
25
-
1.5
2.4
V
V
CC
= 5.0V
25
-
1.8
2.4
V
Input Hysteresis
25
-
0.5
-
V
Input Resistance
25
3
5
7
k
TRANSMITTER OUTPUTS
Output Voltage Swing
All Transmitter Outputs Loaded with 3k
to Ground
Full
5.0
5.4
-
V
Output Resistance
V
CC
= V+ = V- = 0V, Transmitter Output =
2V
Full
300
10M
-
Output Short-Circuit Current
Full
-
35
60
mA
Output Leakage Current
V
OUT
=
12V, V
CC
= 0V or 3V to 5.5V,
Automatic Powerdown or FORCEOFF = SHDN = GND
Full
-
-
25
A
MOUSE DRIVEABILITY (ICL324XE Only)
Transmitter Output Voltage
(See Figure 9)
T1
IN
= T2
IN
= GND, T3
IN
= V
CC
, T3
OUT
Loaded with 3k
to GND, T1
OUT
and T2
OUT
Loaded with 2.5mA Each
Full
5
-
-
V
TIMING CHARACTERISTICS
Maximum Data Rate
R
L
= 3k
,
C
L
= 1000pF, One Transmitter Switching
Full
250
500
-
kbps
Receiver Propagation Delay
Receiver Input to Receiver
Output, C
L
= 150pF
t
PHL
25
-
0.15
-
s
t
PLH
25
-
0.15
-
s
Receiver Output Enable Time
Normal Operation (Except ICL3232E)
25
-
200
-
ns
Receiver Output Disable Time
Normal Operation (Except ICL3232E)
25
-
200
-
ns
Transmitter Skew
t
PHL
- t
PLH
(Note 4)
25
-
100
-
ns
Receiver Skew
t
PHL
- t
PLH
25
-
50
-
ns
Transition Region Slew Rate
V
CC
= 3.3V,
R
L
= 3k
to 7k
,
Measured from 3V to -3V or
-3V to 3V
C
L
= 150pF to 2500pF
25
4
-
30
V/
s
C
L
= 150pF to 1000pF
25
6
-
30
V/
s
ESD PERFORMANCE
RS-232 Pins (T
OUT
, R
IN
)
Human Body Model
25
-
15
-
kV
IEC1000-4-2 Contact Discharge
25
-
8
-
kV
IEC1000-4-2 Air Gap Discharge
25
-
15
-
kV
All Other Pins
Human Body Model
25
-
2
-
kV
NOTE:
4. Transmitter skew is measured at the transmitter zero crossing points.
Electrical Specifications
Test Conditions: V
CC
= 3V to 5.5V, C
1
- C
4
= 0.1
F; Unless Otherwise Specified.
Typicals are at T
A
= 25
o
C (Continued)
PARAMETER
TEST CONDITIONS
TEMP
(
o
C)
MIN
TYP
MAX
UNITS
ICL3221E , ICL3222E , ICL3223E , ICL3232E , ICL3241E, ICL3243E
10
Detailed Description
ICL32XXE interface ICs operate from a single +3V to +5.5V
supply, guarantee a 250kbps minimum data rate, require
only four small external 0.1
F capacitors, feature low power
consumption, and meet all ElA RS-232C and V.28
specifications. The circuit is divided into three sections:
charge pump, transmitters and receivers.
Charge-Pump
Intersil's new ICL32XXE family utilizes regulated on-chip
dual charge pumps as voltage doublers, and voltage
inverters to generate
5.5V transmitter supplies from a V
CC
supply as low as 3.0V. This allows these devices to maintain
RS-232 compliant output levels over the
10% tolerance
range of 3.3V powered systems. The efficient on-chip power
supplies require only four small, external 0.1
F capacitors
for the voltage doubler and inverter functions at V
CC
= 3.3V.
See the "Capacitor Selection" section, and Table 3 for
capacitor recommendations for other operating conditions.
The charge pumps operate discontinuously (i.e., they turn off
as soon as the V+ and V- supplies are pumped up to the
nominal values), resulting in significant power savings.
Transmitters
The transmitters are proprietary, low dropout, inverting
drivers that translate TTL/CMOS inputs to EIA/TIA-232
output levels. Coupled with the on-chip
5.5V supplies,
these transmitters deliver true RS-232 levels over a wide
range of single supply system voltages.
Except for the ICL3232E, all transmitter outputs disable and
assume a high impedance state when the device enters the
powerdown mode (see Table 2). These outputs may be
driven to
12V when disabled.
All devices guarantee a 250kbps data rate for full load
conditions (3k
and 1000pF), V
CC
3.0V, with one
transmitter operating at full speed. Under more typical
conditions of V
CC
3.3V, R
L
= 3k
, and C
L
= 250pF, one
transmitter easily operates at 900kbps.
Transmitter inputs float if left unconnected, and may cause
I
CC
increases. Connect unused inputs to GND for the best
performance.
Receivers
All the ICL32XXE devices contain standard inverting
receivers that three-state (except for the ICL3232E) via the
EN or FORCEOFF control lines. Additionally, the two
ICL324XE products include noninverting (monitor) receivers
(denoted by the R
OUTB
label) that are always active,
regardless of the state of any control lines. All the receivers
convert RS-232 signals to CMOS output levels and accept
inputs up to
25V while presenting the required 3k
to 7k
input impedance (see Figure 1) even if the power is off
(V
CC
= 0V). The receivers' Schmitt trigger input stage uses
hysteresis to increase noise immunity and decrease errors
due to slow input signal transitions.
The ICL3221E/22E/23E/41E inverting receivers disable only
when EN is driven high. ICL3243E receivers disable during
forced (manual) powerdown, but not during automatic
powerdown (see Table 2).
ICL324XE monitor receivers remain active even during
manual powerdown and forced receiver disable, making them
extremely useful for Ring Indicator monitoring. Standard
receivers driving powered down peripherals must be disabled
to prevent current flow through the peripheral's protection
diodes (see Figures 2 and 3). This renders them useless for
wake up functions, but the corresponding monitor receiver
can be dedicated to this task as shown in Figure 3.
Low Power Operation
These 3V devices require a nominal supply current of
0.3mA, even at V
CC
= 5.5V, during normal operation (not in
powerdown mode). This is considerably less than the 5mA
to 11mA current required by comparable 5V RS-232
devices, allowing users to reduce system power simply by
switching to this new family.
Pin Compatible Replacements for 5V Devices
The ICL3221E/22E/32E are pin compatible with existing 5V
RS-232 transceivers - see the Features section on the front
page for details.
This pin compatibility coupled with the low I
CC
and wide
operating supply range, make the ICL32XXE potential lower
power, higher performance drop-in replacements for existing
5V applications. As long as the
5V RS-232 output swings
are acceptable, and transmitter input pull-up resistors aren't
required, the ICL32XXE should work in most 5V
applications.
When replacing a device in an existing 5V application, it is
acceptable to terminate C
3
to V
CC
as shown on the Typical
Operating Circuit. Nevertheless, terminate C
3
to GND if
possible, as slightly better performance results from this
configuration.
Powerdown Functionality (Except
ICL3232E)
The already low current requirement drops significantly
when the device enters powerdown mode. In powerdown,
supply current drops to 1
A, because the on-chip charge
pump turns off (V+ collapses to V
CC
, V- collapses to GND),
and the transmitter outputs three-state. Inverting receiver
outputs may or may not disable in powerdown; refer to
Table 2 for details. This micro-power mode makes these
devices ideal for battery powered and portable applications.
R
XOUT
GND
V
ROUT
V
CC
5k
R
XIN
-25V
V
RIN
+25V
GND
V
CC
FIGURE 1. INVERTING RECEIVER CONNECTIONS
ICL3221E , ICL3222E , ICL3223E , ICL3232E , ICL3241E, ICL3243E
11
Software Controlled (Manual) Powerdown
Most devices in the ICL32XXE family provide pins that allow
the user to force the IC into the low power, standby state.
On the ICL3222E and ICL3241E, the powerdown control is
via a simple shutdown (SHDN) pin. Driving this pin high
enables normal operation, while driving it low forces the IC
into its powerdown state. Connect SHDN to V
CC
if the
powerdown function isn't needed. Note that all the receiver
outputs remain enabled during shutdown (see Table 2). For
the lowest power consumption during powerdown, the
receivers should also be disabled by driving the EN input
high (see next section, and Figures 2 and 3).
The ICL3221E, ICL3223E, and ICL3243E utilize a two pin
approach where the FORCEON and FORCEOFF inputs
determine the IC's mode. For always enabled operation,
FORCEON and FORCEOFF are both strapped high. To
switch between active and powerdown modes, under logic
or software control, only the FORCEOFF input need be
driven. The FORCEON state isn't critical, as FORCEOFF
dominates over FORCEON. Nevertheless, if strictly manual
control over powerdown is desired, the user must strap
FORCEON high to disable the automatic powerdown
circuitry. ICL3243E inverting (standard) receiver outputs also
disable when the device is in manual powerdown, thereby
eliminating the possible current path through a shutdown
peripheral's input protection diode (see Figures 2 and 3).
TABLE 2. POWERDOWN AND ENABLE LOGIC TRUTH TABLE
RS-232
SIGNAL
PRESENT
AT
RECEIVER
INPUT?
FORCEOFF
OR SHDN
INPUT
FORCEON
INPUT
EN
INPUT
TRANSMITTER
OUTPUTS
RECEIVER
OUTPUTS
(NOTE 5)
R
OUTB
OUTPUTS
INVALID
OUTPUT
MODE OF OPERATION
ICL3222E, ICL3241E
N.A.
L
N.A.
L
High-Z
Active
Active
N.A.
Manual Powerdown
N.A.
L
N.A.
H
High-Z
High-Z
Active
N.A.
Manual Powerdown w/Rcvr. Disabled
N.A.
H
N.A.
L
Active
Active
Active
N.A.
Normal Operation
N.A.
H
N.A.
H
Active
High-Z
Active
N.A.
Normal Operation w/Rcvr. Disabled
ICL3221E, ICL3223E
NO
H
H
L
Active
Active
N.A.
L
Normal Operation
(Auto Powerdown Disabled)
NO
H
H
H
Active
High-Z
N.A.
L
YES
H
L
L
Active
Active
N.A.
H
Normal Operation
(Auto Powerdown Enabled)
YES
H
L
H
Active
High-Z
N.A.
H
NO
H
L
L
High-Z
Active
N.A.
L
Powerdown Due to Auto Powerdown
Logic
NO
H
L
H
High-Z
High-Z
N.A.
L
YES
L
X
L
High-Z
Active
N.A.
H
Manual Powerdown
YES
L
X
H
High-Z
High-Z
N.A.
H
Manual Powerdown w/Rcvr. Disabled
NO
L
X
L
High-Z
Active
N.A.
L
Manual Powerdown
NO
L
X
H
High-Z
High-Z
N.A.
L
Manual Powerdown w/Rcvr. Disabled
ICL3243E
NO
H
H
N.A.
Active
Active
Active
L
Normal Operation
(Auto Powerdown Disabled)
YES
H
L
N.A.
Active
Active
Active
H
Normal Operation
(Auto Powerdown Enabled)
NO
H
L
N.A.
High-Z
Active
Active
L
Powerdown Due to Auto Powerdown
Logic
YES
L
X
N.A.
High-Z
High-Z
Active
H
Manual Powerdown
NO
L
X
N.A.
High-Z
High-Z
Active
L
Manual Powerdown
NOTE:
5. Applies only to the ICL3241E and ICL3243E.
ICL3221E , ICL3222E , ICL3223E , ICL3232E , ICL3241E, ICL3243E
12
The INVALID output always indicates whether or not a valid
RS-232 signal is present at any of the receiver inputs (see
Table 2), giving the user an easy way to determine when the
interface block should power down. In the case of a
disconnected interface cable where all the receiver inputs
are floating (but pulled to GND by the internal receiver pull
down resistors), the INVALID logic detects the invalid levels
and drives the output low. The power management logic
then uses this indicator to power down the interface block.
Reconnecting the cable restores valid levels at the receiver
inputs, INVALID switches high, and the power management
logic wakes up the interface block. INVALID can also be
used to indicate the DTR or RING INDICATOR signal, as
long as the other receiver inputs are floating, or driven to
GND (as in the case of a powered down driver). Connecting
FORCEOFF and FORCEON together disables the
automatic powerdown feature, enabling them to function as
a manual SHUTDOWN input (see Figure 4).
With any of the above control schemes, the time required to
exit powerdown, and resume transmission is only 100
s. A
mouse, or other application, may need more time to wake up
from shutdown. If automatic powerdown is being utilized, the
RS-232 device will reenter powerdown if valid receiver levels
aren't reestablished within 30
s of the ICL32XXE powering
up. Figure 5 illustrates a circuit that keeps the ICL32XXE
from initiating automatic powerdown for 100ms after
powering up. This gives the slow-to-wake peripheral circuit
time to reestablish valid RS-232 output levels.
Automatic Powerdown (ICL3221E/23E/43E Only)
Even greater power savings is available by using the
devices which feature an automatic powerdown function.
When no valid RS-232 voltages (see Figure 6) are sensed
on any receiver input for 30
s, the charge pump and
transmitters powerdown, thereby reducing supply current to
1
A. Invalid receiver levels occur whenever the driving
peripheral's outputs are shut off (powered down) or when
the RS-232 interface cable is disconnected. The ICL32XXE
powers back up whenever it detects a valid RS-232 voltage
level on any receiver input. This automatic powerdown
feature provides additional system power savings without
changes to the existing operating system.
FIGURE 2. POWER DRAIN THROUGH POWERED DOWN
PERIPHERAL
OLD
V
CC
POWERED
GND
SHDN = GND
V
CC
Rx
Tx
V
CC
CURRENT
V
OUT
=
V
CC
FLOW
RS-232 CHIP
DOWN
UART
FIGURE 3. DISABLED RECEIVERS PREVENT POWER DRAIN
ICL324XE
TRANSITION
R
X
T
X
R2
OUTB
R2
OUT
T1
IN
FORCEOFF = GND
V
CC
V
CC
TO
R2
IN
T1
OUT
V
OUT
=
HI-Z
POWERED
OR SHDN = GND, EN = V
CC
DETECTOR
DOWN
UART
WAKE-UP
LOGIC
FIGURE 4. CONNECTIONS FOR MANUAL POWERDOWN
WHEN NO VALID RECEIVER SIGNALS ARE
PRESENT
PWR
FORCEOFF
INVALID
CPU
I/O
FORCEON
ICL3221E/23E/43E
MGT
LOGIC
UART
FIGURE 5. CIRCUIT TO PREVENT AUTO POWERDOWN FOR
100ms AFTER FORCED POWERUP
ICL3221E/23E/43E
FORCEOFF
FORCEON
POWER
MASTER POWERDOWN LINE
1M
0.1
F
MANAGEMENT
UNIT
ICL3221E , ICL3222E , ICL3223E , ICL3232E , ICL3241E, ICL3243E
13
Automatic powerdown operates when the FORCEON input
is low, and the FORCEOFF input is high. Tying FORCEON
high disables automatic powerdown, but manual powerdown
is always available via the overriding FORCEOFF input.
Table 2 summarizes the automatic powerdown functionality.
Devices with the automatic powerdown feature include an
INVALID output signal, which switches low to indicate that
invalid levels have persisted on all of the receiver inputs for
more than 30
s (see Figure 7). INVALID switches high 1
s
after detecting a valid RS-232 level on a receiver input.
INVALID operates in all modes (forced or automatic
powerdown, or forced on), so it is also useful for systems
employing manual powerdown circuitry. When automatic
powerdown is utilized, INVALID = 0 indicates that the
ICL32XXE is in powerdown mode.
The time to recover from automatic powerdown mode is
typically 100
s.
Receiver ENABLE Control (ICL3221E/22E/23E/41E
Only)
Several devices also feature an EN input to control the
receiver outputs. Driving EN high disables all the inverting
(standard) receiver outputs placing them in a high
impedance state. This is useful to eliminate supply current,
due to a receiver output forward biasing the protection diode,
when driving the input of a powered down (V
CC
= GND)
peripheral (see Figure 2). The enable input has no effect on
transmitter nor monitor (R
OUTB
) outputs.
Capacitor Selection
The charge pumps require 0.1
F capacitors for 3.3V
operation. For other supply voltages refer to Table 3 for
capacitor values. Do not use values smaller than those listed
in Table 3. Increasing the capacitor values (by a factor of 2)
reduces ripple on the transmitter outputs and slightly
reduces power consumption. C
2
, C
3
, and C
4
can be
increased without increasing C
1
's value, however, do not
increase C
1
without also increasing C
2
, C
3
, and C
4
to
maintain the proper ratios (C
1
to the other capacitors).
When using minimum required capacitor values, make sure
that capacitor values do not degrade excessively with
temperature. If in doubt, use capacitors with a larger nominal
value. The capacitor's equivalent series resistance (ESR)
usually rises at low temperatures and it influences the
amount of ripple on V+ and V-.
Power Supply Decoupling
In most circumstances a 0.1
F bypass capacitor is
adequate. In applications that are particularly sensitive to
power supply noise, decouple V
CC
to ground with a
capacitor of the same value as the charge-pump capacitor C
1
.
Connect the bypass capacitor as close as possible to the IC.
Transmitter Outputs when Exiting
Powerdown
Figure 8 shows the response of two transmitter outputs
when exiting powerdown mode. As they activate, the two
transmitter outputs properly go to opposite RS-232 levels,
with no glitching, ringing, nor undesirable transients. Each
transmitter is loaded with 3k
in parallel with 2500pF. Note
that the transmitters enable only when the magnitude of the
supplies exceed approximately 3V.
FIGURE 6. DEFINITION OF VALID RS-232 RECEIVER LEVELS
0.3V
-0.3V
-2.7V
2.7V
INVALID LEVEL - POWERDOWN OCCURS AFTER 30
s
VALID RS-232 LEVEL - ICL32XXE IS ACTIVE
VALID RS-232 LEVEL - ICL32XXE IS ACTIVE
INDETERMINATE - POWERDOWN MAY OR
INDETERMINATE - POWERDOWN MAY OR
MAY NOT OCCUR
MAY NOT OCCUR
RECEIVER
INPUTS
TRANSMITTER
OUTPUTS
INVALID
OUTPUT
V+
V
CC
0
V-
V
CC
0
t
INVL
t
INVH
INVALID
REGION
}
FIGURE 7. AUTOMATIC POWERDOWN AND INVALID
TIMING DIAGRAMS
AUTOPWDN
PWR UP
TABLE 3. REQUIRED CAPACITOR VALUES
V
CC
(V)
C
1
(
F)
C
2
, C
3
, C
4
(
F)
3.0 to 3.6
0.1
0.1
4.5 to 5.5
0.047
0.33
3.0 to 5.5
0.1
0.47
ICL3221E , ICL3222E , ICL3223E , ICL3232E , ICL3241E, ICL3243E
14
Mouse Driveability
The ICL324XE have been specifically designed to power a
serial mouse while operating from low voltage supplies.
Figure 9 shows the transmitter output voltages under
increasing load current. The on-chip switching regulator
ensures the transmitters will supply at least
5V during worst
case conditions (15mA for paralleled V+ transmitters, 7.3mA
for single V- transmitter). The Automatic Powerdown feature
does not work with a mouse, so FORCEOFF and
FORCEON should be connected to V
CC
.
High Data Rates
The ICL32XXE maintain the RS-232
5V minimum
transmitter output voltages even at high data rates.
Figure 10 details a transmitter loopback test circuit, and
Figure 11 illustrates the loopback test result at 120kbps. For
this test, all transmitters were simultaneously driving RS-232
loads in parallel with 1000pF, at 120kbps. Figure 12 shows
the loopback results for a single transmitter driving 1000pF
and an RS-232 load at 250kbps. The static transmitters were
also loaded with an RS-232 receiver.
TIME (20
s/DIV.)
T1
T2
2V/DIV.
5V/DIV.
V
CC
= +3.3V
FORCEOFF
FIGURE 8. TRANSMITTER OUTPUTS WHEN EXITING
POWERDOWN
C1 - C4 = 0.1
F
FIGURE 9. TRANSMITTER OUTPUT VOLTAGE vs LOAD
CURRENT (PER TRANSMITTER, i.e., DOUBLE
CURRENT AXIS FOR TOTAL V
OUT+
CURRENT)
TRA
N
SMI
TTER O
U
TPUT VO
LTAG
E
(V)
LOAD CURRENT PER TRANSMITTER (mA)
0
2
4
6
8
10
-6
-4
-2
0
2
4
6
-5
-3
-1
1
3
5
1
3
5
7
9
V
OUT
+
V
OUT
-
V
CC
V
OUT
+
V
OUT
-
T1
T2
T3
V
CC
= 3.0V
ICL3241E/43E
FIGURE 10. TRANSMITTER LOOPBACK TEST CIRCUIT
FIGURE 11. LOOPBACK TEST AT 120kbps
FIGURE 12. LOOPBACK TEST AT 250kbps
ICL32XXE
V
CC
FORCEOFF
C
1
C
2
C
4
C
3
+
+
+
+
1000pF
V+
V-
5k
T
IN
R
OUT
C1+
C1-
C2+
C2-
R
IN
T
OUT
+
V
CC
0.1
F
V
CC
EN
SHDN OR
T1
IN
T1
OUT
R1
OUT
5
s/DIV.
V
CC
= +3.3V
5V/DIV.
C1 - C4 = 0.1
F
T1
IN
T1
OUT
R1
OUT
2
s/DIV.
5V/DIV.
V
CC
= +3.3V
C1 - C4 = 0.1
F
ICL3221E , ICL3222E , ICL3223E , ICL3232E , ICL3241E, ICL3243E
15
Interconnection with 3V and 5V Logic
The ICL32XX directly interface with 5V CMOS and TTL logic
families. Nevertheless, with the ICL32XX at 3.3V, and the logic
supply at 5V, AC, HC, and CD4000 outputs can drive ICL32XX
inputs, but ICL32XX outputs do not reach the minimum V
IH
for
these logic families. See Table 4 for more information.
15kV ESD Protection
All pins on ICL32XX devices include ESD protection
structures, but the ICL32XXE family incorporates advanced
structures which allow the RS-232 pins (transmitter outputs
and receiver inputs) to survive ESD events up to
15kV. The
RS-232 pins are particularly vulnerable to ESD damage
because they typically connect to an exposed port on the
exterior of the finished product. Simply touching the port
pins, or connecting a cable, can cause an ESD event that
might destroy unprotected ICs. These new ESD structures
protect the device whether or not it is powered up, protect
without allowing any latchup mechanism to activate, and
don't interfere with RS-232 signals as large as
25V.
Human Body Model (HBM) Testing
As the name implies, this test method emulates the ESD
event delivered to an IC during human handling. The tester
delivers the charge through a 1.5k
current limiting resistor,
making the test less severe than the IEC-1000 test which
utilizes a 330
limiting resistor. The HBM method
determines an ICs ability to withstand the ESD transients
typically present during handling and manufacturing. Due to
the random nature of these events, each pin is tested with
respect to all other pins. The RS-232 pins on "E" family
devices can withstand HBM ESD events to
15kV.
IEC1000-4-2 Testing
The IEC 1000 test method applies to finished equipment,
rather than to an individual IC. Therefore, the pins most likely
to suffer an ESD event are those that are exposed to the
outside world (the RS-232 pins in this case), and the IC is
tested in its typical application configuration (power applied)
rather than testing each pin-to-pin combination. The lower
current limiting resistor coupled with the larger charge
storage capacitor yields a test that is much more severe than
the HBM test. The extra ESD protection built into this
device's RS-232 pins allows the design of equipment
meeting level 4 criteria without the need for additional board
level protection on the RS-232 port.
AIR-GAP DISCHARGE TEST METHOD
For this test method, a charged probe tip moves toward the
IC pin until the voltage arcs to it. The current waveform
delivered to the IC pin depends on approach speed,
humidity, temperature, etc., so it is difficult to obtain
repeatable results. The "E" device RS-232 pins withstand
15kV air-gap discharges.
CONTACT DISCHARGE TEST METHOD
During the contact discharge test, the probe contacts the
tested pin before the probe tip is energized, thereby
eliminating the variables associated with the air-gap
discharge. The result is a more repeatable and predictable
test, but equipment limits prevent testing devices at voltages
higher than
8kV. All "E" family devices survive
8kV contact
discharges on the RS-232 pins.
TABLE 4. LOGIC FAMILY COMPATIBILITY WITH VARIOUS
SUPPLY VOLTAGES
SYSTEM POWER-
SUPPLY VOLTAGE
(V)
V
CC
SUPPLY
VOLTAGE
(V)
COMPATIBILITY
3.3
3.3
Compatible with all CMOS
families.
5
5
Compatible with all TTL and
CMOS logic families.
5
3.3
Compatible with ACT and HCT
CMOS, and with TTL. ICL32XX
outputs are incompatible with AC,
HC, and CD4000 CMOS inputs.
Typical Performance Curves
V
CC
= 3.3V, T
A
= 25
o
C
FIGURE 13. TRANSMITTER OUTPUT VOLTAGE vs LOAD
CAPACITANCE
FIGURE 14. SLEW RATE vs LOAD CAPACITANCE
-6
-4
-2
0
2
4
6
1000
2000
3000
4000
5000
0
LOAD CAPACITANCE (pF)
TR
ANSMI
TTER O
U
TPUT
VO
LTAG
E
(V)
1 TRANSMITTER AT 250kbps
V
OUT
+
V
OUT
-
1 OR 2 TRANSMITTERS AT 30kbps
LOAD CAPACITANCE (pF)
SLEW
RATE
(V/
s)
0
1000
2000
3000
4000
5000
5
10
15
20
25
+SLEW
-SLEW
ICL3221E , ICL3222E , ICL3223E , ICL3232E , ICL3241E, ICL3243E
16
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
ICL3221E: 286
ICL3222E: 338
ICL3223E: 357
ICL3232E: 296
ICL324XE: 464
PROCESS:
Si Gate CMOS
FIGURE 15. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
FIGURE 16. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
FIGURE 17. SUPPLY CURRENT vs LOAD CAPACITANCE
WHEN TRANSMITTING DATA
FIGURE 18. SUPPLY CURRENT vs SUPPLY VOLTAGE
Typical Performance Curves
V
CC
= 3.3V, T
A
= 25
o
C (Continued)
0
5
10
15
20
25
30
45
35
40
0
1000
2000
3000
4000
5000
LOAD CAPACITANCE (pF)
SUPP
L
Y
CURRENT
(m
A)
20kbps
250kbps
120kbps
ICL3221E
0
5
10
15
20
25
30
45
35
40
0
1000
2000
3000
4000
5000
LOAD CAPACITANCE (pF)
SUPP
L
Y
CURRENT
(
m
A)
20kbps
250kbps
120kbps
ICL3222E - ICL3232E
0
5
10
15
20
25
30
45
35
40
0
1000
2000
3000
4000
5000
LOAD CAPACITANCE (pF)
SUPP
L
Y
CURRENT
(
m
A)
20kbps
250kbps
120kbps
ICL324XE
SUP
P
L
Y
CURRENT
(m
A)
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0
0.5
1.0
1.5
2.0
SUPPLY VOLTAGE (V)
2.5
3.0
3.5
NO LOAD
ALL OUTPUTS STATIC
ICL3221E - ICL3232E
ICL324XE
ICL324XE
ICL3221E , ICL3222E , ICL3223E , ICL3232E , ICL3241E, ICL3243E
17
ICL3221E , ICL3222E , ICL3223E , ICL3232E , ICL3241E, ICL3243E
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in JE-
DEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and
are measured with the leads constrained to be perpendic-
ular to datum
.
7. e
B
and e
C
are measured at the lead tips with the leads unconstrained.
e
C
must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
e
A
-C-
CL
E
e
A
C
e
B
e
C
-B-
E1
INDEX
1 2 3
N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1
B
e
D
D1
A
A2
L
A1
-A-
0.010 (0.25)
C A
M
B S
E16.3
(JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
B1
0.045
0.070
1.15
1.77
8, 10
C
0.008
0.014
0.204
0.355
-
D
0.735
0.775
18.66
19.68
5
D1
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
2.54 BSC
-
e
A
0.300 BSC
7.62 BSC
6
e
B
-
0.430
-
10.92
7
L
0.115
0.150
2.93
3.81
4
N
16
16
9
Rev. 0 12/93
18
ICL3221E , ICL3222E , ICL3223E , ICL3232E , ICL3241E, ICL3243E
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and
are measured with the leads constrained to be perpendic-
ular to datum
.
7. e
B
and e
C
are measured at the lead tips with the leads unconstrained.
e
C
must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
e
A
-C-
CL
E
e
A
C
e
B
e
C
-B-
E1
INDEX
1 2 3
N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1
B
e
D
D1
A
A2
L
A1
-A-
0.010 (0.25)
C A
M
B S
E18.3
(JEDEC MS-001-BC ISSUE D)
18 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
B1
0.045
0.070
1.15
1.77
8, 10
C
0.008
0.014
0.204
0.355
-
D
0.845
0.880
21.47
22.35
5
D1
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
2.54 BSC
-
e
A
0.300 BSC
7.62 BSC
6
e
B
-
0.430
-
10.92
7
L
0.115
0.150
2.93
3.81
4
N
18
18
9
Rev. 0 12/93
19
ICL3221E , ICL3222E , ICL3223E , ICL3232E , ICL3241E, ICL3243E
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the "MO Series Symbol List" in Section 2.2
of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and
are measured with the leads constrained to be perpen-
dicular to datum
.
7. e
B
and e
C
are measured at the lead tips with the leads uncon-
strained. e
C
must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dam-
bar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
e
A
-C-
CL
E
e
A
C
e
B
e
C
-B-
E1
INDEX
1 2 3
N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1
B
e
D
D1
A
A2
L
A1
-A-
0.010 (0.25)
C A
M
B S
E20.3
(JEDEC MS-001-AD ISSUE D)
20 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
B1
0.045
0.070
1.55
1.77
8
C
0.008
0.014
0.204
0.355
-
D
0.980
1.060
24.89
26.9
5
D1
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
2.54 BSC
-
e
A
0.300 BSC
7.62 BSC
6
e
B
-
0.430
-
10.92
7
L
0.115
0.150
2.93
3.81
4
N
20
20
9
Rev. 0 12/93
20
ICL3221E , ICL3222E , ICL3223E , ICL3232E , ICL3241E, ICL3243E
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the "MO Series Symbol List" in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension "D" does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension "E" does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. "L" is the length of terminal for soldering to a substrate.
7. "N" is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width "B", as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
INDEX
AREA
E
D
N
1
2
3
-B-
0.25(0.010)
C A
M
B S
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45
o
C
H
0.25(0.010)
B
M
M
M16.15
(JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
0.053
0.069
1.35
1.75
-
A1
0.004
0.010
0.10
0.25
-
B
0.014
0.019
0.35
0.49
9
C
0.007
0.010
0.19
0.25
-
D
0.386
0.394
9.80
10.00
3
E
0.150
0.157
3.80
4.00
4
e
0.050 BSC
1.27 BSC
-
H
0.228
0.244
5.80
6.20
-
h
0.010
0.020
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
16
16
7
0
o
8
o
0
o
8
o
-
Rev. 1 02/02
21
ICL3221E , ICL3222E , ICL3223E , ICL3232E , ICL3241E, ICL3243E
Thin Shrink Small Outline Plastic Packages (TSSOP)
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension "D" does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension "E1" does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. "L" is the length of terminal for soldering to a substrate.
7. "N" is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension "b" does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of "b" dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact. (Angles in degrees)
INDEX
AREA
E1
D
N
1
2
3
-B-
0.10(0.004)
C A
M
B S
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
c
E
0.25(0.010)
B
M
M
L
0.25
0.010
GAUGE
PLANE
A2
0.05(0.002)
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
-
0.043
-
1.10
-
A1
0.002
0.006
0.05
0.15
-
A2
0.033
0.037
0.85
0.95
-
b
0.0075
0.012
0.19
0.30
9
c
0.0035
0.008
0.09
0.20
-
D
0.193
0.201
4.90
5.10
3
E1
0.169
0.177
4.30
4.50
4
e
0.026 BSC
0.65 BSC
-
E
0.246
0.256
6.25
6.50
-
L
0.020
0.028
0.50
0.70
6
N
16
16
7
0
o
8
o
0
o
8
o
-
Rev. 1 2/02
22
ICL3221E , ICL3222E , ICL3223E , ICL3232E , ICL3241E, ICL3243E
Small Outline Plastic Packages (SSOP)
NOTES:
1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension "D" does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078
inch) per side.
4. Dimension "E" does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. "L" is the length of terminal for soldering to a substrate.
7. "N" is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension "B" does not include dambar protrusion. Allowable dambar
protrusion shall be 0.13mm (0.005 inch) total in excess of "B" dimen-
sion at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA
E
D
N
1
2
3
-B-
0.25(0.010)
C A
M
B S
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
C
H
0.25(0.010)
B
M
M
0.25
0.010
GAUGE
PLANE
A2
M16.209
(JEDEC MO-150-AC ISSUE B)
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
-
0.078
-
2.00
-
A1
0.002
-
0.05
-
-
A2
0.065
0.072
1.65
1.85
-
B
0.009
0.014
0.22
0.38
9
C
0.004
0.009
0.09
0.25
-
D
0.233
0.255
5.90
6.50
3
E
0.197
0.220
5.00
5.60
4
e
0.026 BSC
0.65 BSC
-
H
0.292
0.322
7.40
8.20
-
L
0.022
0.037
0.55
0.95
6
N
16
16
7
0
o
8
o
0
o
8
o
-
Rev. 2 3/95
23
ICL3221E , ICL3222E , ICL3223E , ICL3232E , ICL3241E, ICL3243E
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension "D" does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension "E" does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. "L" is the length of terminal for soldering to a substrate.
7. "N" is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA
E
D
N
1
2
3
-B-
0.25(0.010)
C A
M
B S
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45
o
C
H
0.25(0.010)
B
M
M
M16.3
(JEDEC MS-013-AA ISSUE C)
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.3977
0.4133
10.10
10.50
3
E
0.2914
0.2992
7.40
7.60
4
e
0.050 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
N
16
16
7
0
o
8
o
0
o
8
o
-
Rev. 0 12/93
24
ICL3221E , ICL3222E , ICL3223E , ICL3232E , ICL3241E, ICL3243E
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension "D" does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension "E" does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. "L" is the length of terminal for soldering to a substrate.
7. "N" is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA
E
D
N
1
2
3
-B-
0.25(0.010)
C A
M
B S
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45
o
C
H
0.25(0.010)
B
M
M
M18.3
(JEDEC MS-013-AB ISSUE C)
18 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.4469
0.4625
11.35
11.75
3
E
0.2914
0.2992
7.40
7.60
4
e
0.050 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
N
18
18
7
0
o
8
o
0
o
8
o
-
Rev. 0 12/93
25
ICL3221E , ICL3222E , ICL3223E , ICL3232E , ICL3241E, ICL3243E
Thin Shrink Small Outline Plastic Packages (TSSOP)
INDEX
AREA
E1
D
N
1
2
3
-B-
0.10(0.004)
C A
M
B S
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
c
E
0.25(0.010)
B
M
M
L
0.25
0.010
GAUGE
PLANE
A2
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension "D" does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension "E1" does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. "L" is the length of terminal for soldering to a substrate.
7. "N" is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension "b" does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
0.05(0.002)
M20.173
20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
-
0.047
-
1.20
-
A1
0.002
0.006
0.05
0.15
-
A2
0.031
0.051
0.80
1.05
-
b
0.0075
0.0118
0.19
0.30
9
c
0.0035
0.0079
0.09
0.20
-
D
0.252
0.260
6.40
6.60
3
E1
0.169
0.177
4.30
4.50
4
e
0.026 BSC
0.65 BSC
-
E
0.246
0.256
6.25
6.50
-
L
0.0177
0.0295
0.45
0.75
6
N
20
20
7
0
o
8
o
0
o
8
o
-
Rev. 1 6/98
26
ICL3221E , ICL3222E , ICL3223E , ICL3232E , ICL3241E, ICL3243E
Shrink Small Outline Plastic Packages (SSOP)
NOTES:
1. Symbols are defined in the "MO Series Symbol List" in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension "D" does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension "E" does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. "L" is the length of terminal for soldering to a substrate.
7. "N" is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension "B" does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess
of "B" dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
INDEX
AREA
E
D
N
1
2
3
-B-
0.25(0.010)
C A
M
B S
e
-A-
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
C
H
0.25(0.010)
B
M
M
L
0.25
0.010
GAUGE
PLANE
A2
M20.209
(JEDEC MO-150-AE ISSUE B)
20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
0.068
0.078
1.73
1.99
A1
0.002
0.008'
0.05
0.21
A2
0.066
0.070'
1.68
1.78
B
0.010'
0.015
0.25
0.38
9
C
0.004
0.008
0.09
0.20'
D
0.278
0.289
7.07
7.33
3
E
0.205
0.212
5.20'
5.38
4
e
0.026 BSC
0.65 BSC
H
0.301
0.311
7.65
7.90'
L
0.025
0.037
0.63
0.95
6
N
20
20
7
0 deg.
8 deg.
0 deg.
8 deg.
Rev. 3 11/02
27
ICL3221E , ICL3222E , ICL3223E , ICL3232E , ICL3241E, ICL3243E
Thin Shrink Small Outline Plastic Packages (TSSOP)
INDEX
AREA
E1
D
N
1
2
3
-B-
0.10(0.004)
C A
M
B S
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
c
E
0.25(0.010)
B
M
M
L
0.25
0.010
GAUGE
PLANE
A2
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AE, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension "D" does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension "E1" does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. "L" is the length of terminal for soldering to a substrate.
7. "N" is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension "b" does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
0.05(0.002)
M28.173
28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
-
0.047
-
1.20
-
A1
0.002
0.006
0.05
0.15
-
A2
0.031
0.051
0.80
1.05
-
b
0.0075
0.0118
0.19
0.30
9
c
0.0035
0.0079
0.09
0.20
-
D
0.378
0.386
9.60
9.80
3
E1
0.169
0.177
4.30
4.50
4
e
0.026 BSC
0.65 BSC
-
E
0.246
0.256
6.25
6.50
-
L
0.0177
0.0295
0.45
0.75
6
N
28
28
7
0
o
8
o
0
o
8
o
-
Rev. 0 6/98
28
ICL3221E , ICL3222E , ICL3223E , ICL3232E , ICL3241E, ICL3243E
Shrink Small Outline Plastic Packages (SSOP)
NOTES:
1. Symbols are defined in the "MO Series Symbol List" in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension "D" does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension "E" does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.20mm (0.0078 inch)
per side.
5. The chamfer on the body is optional. If it is not present, a visual in-
dex feature must be located within the crosshatched area.
6. "L" is the length of terminal for soldering to a substrate.
7. "N" is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension "B" does not include dambar protrusion. Allowable dam-
bar protrusion shall be 0.13mm (0.005 inch) total in excess of "B"
dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
INDEX
AREA
E
D
N
1
2
3
-B-
0.25(0.010)
C A
M
B S
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
C
H
0.25(0.010)
B
M
M
0.25
0.010
GAUGE
PLANE
A2
M28.209
(JEDEC MO-150-AH ISSUE B)
28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
-
0.078
-
2.00
-
A1
0.002
-
0.05
-
-
A2
0.065
0.072
1.65
1.85
-
B
0.009
0.014
0.22
0.38
9
C
0.004
0.009
0.09
0.25
-
D
0.390
0.413
9.90
10.50
3
E
0.197
0.220
5.00
5.60
4
e
0.026 BSC
0.65 BSC
-
H
0.292
0.322
7.40
8.20
-
L
0.022
0.037
0.55
0.95
6
N
28
28
7
0
o
8
o
0
o
8
o
-
Rev. 1 3/95
29
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
ICL3221E , ICL3222E , ICL3223E , ICL3232E , ICL3241E, ICL3243E
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the "MO Series Symbol List" in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension "D" does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension "E" does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. "L" is the length of terminal for soldering to a substrate.
7. "N" is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width "B", as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
INDEX
AREA
E
D
N
1
2
3
-B-
0.25(0.010)
C A
M
B S
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45
o
C
H
0.25(0.010)
B
M
M
M28.3
(JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.6969
0.7125
17.70
18.10
3
E
0.2914
0.2992
7.40
7.60
4
e
0.05 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.01
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
N
28
28
7
0
o
8
o
0
o
8
o
-
Rev. 0 12/93
PDF 
ZIP