3-31
August 1997
ICL7129
4
1
/
2
Digit LCD,
Single-Chip A/D Converter
Features
19,999 Count A/D Converter Accurate to
4 Count
10
V Resolution on 200mV Scale
110dB CMRR
Direct LCD Display Drive
True Differential Input and Reference
Low Power Consumption
Decimal Point Drive Outputs
Overrange and Underrange Outputs
Low Battery Detection and Indication
10:1 Range Change Input
Description
The Intersil ICL7129 is a very high performance 4
1
/
2
-digit,
analog-to-digital converter that directly drives a multiplexed
liquid crystal display. This single chip CMOS integrated cir-
cuit requires only a few passive components and a reference
to operate. It is ideal for high resolution hand-held digital
multimeter applications.
The performance of the ICL7129 has not been equaled
before in a single chip A/D converter. The successive integra-
tion technique used in the ICL7129 results in accuracy better
than 0.005% of full scale and resolution down to 10
V/count.
The ICL7129, drawing only 1mA from a 9V battery, is well
suited for battery powered instruments. Provision has been
made for the detection and indication of a "LOW/BATTERY"
condition. Autoranging instruments can be made with the
ICL7129 which provides overrange and underrange outputs
and 10:1 range changing input. The ICL7129 instantly checks
for continuity, giving both a visual indication and a logic level
output which can enable an external audible transducer. These
features and the high performance of the ICL7129 make it an
extremely versatile and accurate instrument-on-a-chip.
Pinouts
Ordering Information
PART NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG. NO.
ICL7129CPL
0 to 70
40 Ld PDIP
E40.6
ICL7129RCPL
0 to 70
40 Ld PDIP
E40.6
ICL7129CM44
0 to 70
44 Ld MQFP
Q44.10x10
NOTE: "R" indicates device with reversed leads.
ICL7129 (PDIP)
TOP VIEW
ICL7129 (MQFP)
TOP VIEW
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
OSC1
OSC3
ANNUNCIATOR
B
1
, C
1
, CONT
A
1
, G
1
, D
1
F
1
, E
1
, DP
1
B
2
, C
2
, LO BAT
A
2
, G
2
, D
2
F
2
, E
2
, DP
2
B
3
, C
3
, MINUS
A
3
, G
3
, D
3
F
3
, E
3
, DP
3
B
4
, C
4
, BC
5
A
4
, D
4
, G
4
F
4
, E
4
, DP
4
BP3
BP2
BP1
V
DISP
DP
4
/OR
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC2
DP
1
DP
2
RANGE
DGND
REF LO
REF HI
IN HI
IN LO
BUFF
C
REF-
C
REF+
COMMON
CONTINUITY
INT OUT
INT IN
V+
V-
LATCH/HOLD
DP
3
/UR
DRIVE
DISPLA
Y OUTPUT LINES
OSC 1
OSC 2
DP
1
DP
2
RANGE
DGND
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17
OSC 3
NC
NC
ANNUNCE
B
1
, C
1
, CONT
A
1
, G
1
, D
1
F
1
, E
1
, DP
1
B
2
, C
2
, LO B
A
T
A
2
, G
2
, D
2
F
2
, E
2
, DP
2
B
3
, C
3
, MINUS
28
27
26
25
24
23
22
21
20
19
18
A
3
, G
3
, D
3
F
3
, E
3
, DP
3
B
4
, C
4
, BC
5
A
4
, D
4
, G
4
F
4
, E
4
, DP
4
BP3
BP2
BP1
V
DISP
DP
4
/OR
DP
3
/UR
39 38 37 36 35 34
33
32
31
30
29
44 43 42 41 40
IN HI
IN LO
CONTINUITY
B
UFF
INT IN
V+
V-
NC
NC
LATCH/
REF HI
REF LO
C
REF
+
C
REF
-
COMMON
DRIVE
HOLD
INT OUT
File Number
3085.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
3-32
Functional Block Diagram
Typical Application Schematic
LOW BATTERY CONTINUITY
SEGMENT DRIVES
BACKPLANE
DRIVES
ANNUNCIATOR DRIVE
LATCH, DECODE DISPLAY MULTIPLEXER
UP/DOWN RESULTS COUNTER
SEQUENCE COUNTER/DECODER
CONTROL LOGIC
OSC3
OSC2
OSC1
ANALOG SECTION
V
DISP
DP
1
DP
2
UR
DP
3
OR
DP
3
DGND
V-
V+
CONT
L/H
RANGE
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
+
ICL7129
150k
10k
+
-
9V
1.0
F
0.1
F
20K
100k
+
-
V
IN
6.8
F
ICL8069
V+
V+
270K
10pF
5pF
0.1
F
560pF
120kHz
LOW BATTERY CONTINUITY
1.2k
(MICA)
(MICA)
ICL7129
3-33
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V
Reference Voltage (REF HI or REF LO). . . . . . . . . . . . . . . . V+ to V-
Input Voltage (Note 1), IN HI or IN LO . . . . . . . . . . . . . . . . . V+ to V-
V
DISP
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DGND -0.3V to V+
Digital Input Pins
1, 2, 19, 20, 21, 22, 27, 37, 38, 39, 40 . . . . . . . . . . . . . DGND to V+
Thermal Resistance (Typical, Note 2)
JA
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(MQFP - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Input voltages may exceed the supply voltages provided that input current is limited to 1400mA. Currents above this value may result in
valid display readings but will not destroy the device if limited to
1mA.
2.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
V- to V+ = 9V, V
REF
= 1.00V, T
A
= 25
o
C, f
CLK
= 120kHz, Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Zero Input Reading
V
IN
= 0V, 200mV Scale
-0000
0000
+0000
Counts
Zero Reading Drift
V
IN
= 0V, 0
o
C To 70
o
C
-
0.5
-
V/
o
C
Ratiometric Reading
V
IN
= V
REF
= 1000mV, RANGE = 2V
9996
9999
10000
Counts
Range Change Accuracy
V
IN
= 0.10000V on Low,
Range
V
IN
= 1.0000V on High Range
0.9999
1.0000
1.0001
Ratio
Rollover Error
-V
IN
= +V
IN
= 199mV
-
1.5
3.0
Counts
Linearity Error
200mV Scale
-
1.0
-
Counts
Input Common-Mode Rejection Ratio
V
CM
= 1V,V
IN
= 0V, 200mV Scale
-
110
-
dB
Input Common-Mode Voltage Range
V
IN
= 0V, 200mV Scale
-
(V-) +1.5
(V+) -1.0
-
V
Noise (Peak-To-Peak Value not Exceeded 95% of Time) V
IN
= 0V 200mV Scale
-
14
-
V
Input Leakage Current
V
IN
= 0V, Pin 32, 33
-
1
10
pA
Scale Factor Tempco
V
IN
= 199mV 0
o
C To 70
o
C
External V
REF
= 0ppm/
o
C
-
2
7
ppm/
o
C
COMMON Voltage
V+ to Pin 28
2.8
3.2
3.5
V
COMMON Sink Current
Common = + 0.1V
-
0.6
-
mA
COMMON Source Current
Common = -0.1V
-
10
-
A
DGND VoItage
V+ to Pin 36, V+ to V- = 9V
4.5
5.3
5.8
V
DGND Sink Current
DGND = +0.5V
-
1.2
-
mA
Supply Voltage Range
V+ to V- (Note 3)
6
9
12
V
Supply Current Excluding COMMON Current
V+ to V- = 9V
-
1.0
1.5
mA
Clock Frequency
(Note 3)
-
120
360
kHz
V
DISP
Resistance
V
DISP
to V+
-
50
-
k
Low Battery Flag Activation Voltage
V+ to V-
6.3
7.2
7.7
V
CONTINUITY Comparator Threshold Voltages
V
OUT
Pin 27 = HI
100
200
-
mV
V
OUT
Pin 27 = LO
-
200
400
mV
Pull-Down Current
Pins 37, 38, 39
-
2
10
A
"Weak Output" Current Sink/Source
Pins 20, 21 Sink/Source
-
3/3
-
A
Pin 27 Sink/Source
-
3/9
-
A
Pin 22 Source Current
-
40
-
A
Pin 22 Sink Current
-
3
-
A
NOTE:
3. Device functionality is guaranteed at the stated Min/Max limits. However, accuracy can degrade under these conditions.
ICL7129
3-34
Pin Descriptions
PIN
SYMBOL
DESCRIPTION
1
OSC
1
Input to first clock inverter.
2
OSC
3
Output of second clock inverter.
3
ANNUNCIATOR
DRIVE
Backplane squarewave output for
driving annunciators.
4
B
1
, C
1
, CONT
Output to display segments.
5
A
1
, G
1
, D
1
Output to display segments.
6
F
1
, E
1
, DP
1
Output to display segments.
7
B
2
, C
2
, LO BATT
Output to display segments.
8
A
2
, G
2
, D
2
Output to display segments.
9
F
2
, E
2
, DP
2
Output to display segments.
10
B
3
, C
3
, MINUS
Output to display segments.
11
A
3
, G
3
, D
3
Output to display segments.
12
F
3
, E
3
, DP
3
Output to display segments.
13
B
4
, C
4
, BC
5
Output to display segments.
14
A
4
, D
4
, G
4
Output to display segments.
15
F
4
, E
4
, DP
4
Output to display segments.
16
BP
3
Backplane #3 output to display.
17
BP
2
Backplane #2 output to display.
18
BP
1
Backplane #1 output to display.
19
V
DlSP
Negative rail for display drivers.
20
DP
4
/OR
INPUT: When HI, turns on most
significant decimal point.
OUTPUT: Pulled HI when result
count exceeds
19,999.
21
DP
3
/UR
INPUT: Second most significant
decimal point on when HI.
OUTPUT: Pulled HI when result
count is less than
1,000.
22
LATCH/HOLD
INPUT: When floating, A/D converter
operates in the free-run mode. When
pulled HI, the last displayed reading is
held. When pulled LO, the result
counter contents are shown
incrementing during the de-integrate
phase of cycle.
OUTPUT: Negative going edge
occurs when the data latches are
updated. Can be used for converter
status signal.
23
V-
Negative power supply terminal.
24
V+
Positive power supply terminal, and
positive rail for display drivers.
25
INT IN
Input to integrator amplifier.
26
INT OUT
Output of integrator amplifier.
27
CONTINUITY
INPUT: When LO, continuity flag on
the display is off. When HI,
continuity flag is on.
OUTPUT: HI when voltage between
inputs is less than +200mV. LO
when voltage between inputs is
more than +200mV.
28
COMMON
Sets common-mode voltage of 3.2V
below V+ for DE, 10X, etc., Can be
used as pre-regulator for external
reference.
29
C
REF
+
Positive side of external reference
capacitor.
30
C
REF
-
Negative side of external reference
capacitor.
31
BUFFER
Output of buffer amplifier.
32
IN LO
Negative input voltage terminal.
33
IN HI
Positive input voltage terminal.
34
REF
HI
Positive reference voltage input
terminal.
35
REF
LO
Negative reference voltage input
terminal.
36
DGND
Ground reference for digital section.
37
RANGE
3
A pull-down for 200mV scale.
Pulled HIGH externally for 2V scale.
38
DP
2
Internal 3
A pull-down. When HI,
decimal point 2 will be on.
39
DP
1
Internal 3
A pull-down. When HI,
decimal point 1 will be on.
40
OSC2
Output of first clock inverter. Input of
second clock inverter.
PIN
SYMBOL
DESCRIPTION
ICL7129
3-35
Detailed Description
The ICL7129 is a uniquely designed single chip A/D converter.
It features a new "successive integration" technique to achieve
10
V resolution on a 200mV full-scale range. To achieve this
resolution a 10:1 improvement in noise performance over
previous monolithic CMOS A/D converters was accomplished.
Previous integrating converters used an external capacitor to
store an offset correction voltage. This technique worked well
but greatly increased the equivalent noise bandwidth of the
converter. The ICL7129 removes this source of error (noise) by
not using an auto-zero capacitor. Offsets are cancelled using
digital techniques instead. Savings in external parts cost are
realized as well as improved noise performance and elimination
of a source of electromagnetic and electrostatic pick-up.
In the overall Functional Block Diagram of the ICL7129 the
heart of this A/D converter is the sequence counter/decoder
which drives the control logic and keeps track of the many
separate phases required for each conversion cycle. The
sequence counter is constantly running and is a separate
counter from the up/down results counter which is activated
only when the integrator is de-integrating. At the end of a con-
version the data remaining in the results counter is latched,
decoded and multiplexed to the liquid crystal display.
The analog section block diagram shown in Figure 1
includes all of the analog switches used to configure the volt-
age sources and amplifiers in the different phases of the
cycle. The input and reference switching schemes are very
similar to those in other less accurate integrating A/D con-
verters. There are 5 basic configurations used in the full con-
version cycle. Figure 2 illustrates a typical waveform on the
integrator output. INT, INT
1
, and INT
2
all refer to the signal
integrate phase where the input voltage is applied to the
integrator amplifier via the buffer amplifier. In this phase, the
integrator ramps over a fixed period of time in a direction
opposite to the polarity of the input voltage.
DE
1
, DE
2
, and DE
3
are the de-integrate phases where the
reference capacitor is switched in series with the buffer ampli-
fier and the integrator ramps back down to the level it started
from before integrating. However, since the de-integrate phase
can terminate only at a clock pulse transition, there is always a
small overshoot of the integrator past the starting point. The
ICL7129 amplifies this overshoot by 10 and DE
2
begins. Simi-
larly DE
2
's overshoot is amplified by 10 and DE
3
begins. At the
end of DE3 the results counter holds a number with 5
1
/
2
digits
of resolution. This was obtained by feeding counts into the
results counter at the 3
1
/
2
digit level during DE
1
, into the 4
1
/
2
digit level during DE
2
and the 5
1
/
2
digit level for DE
3
. The
effects of offset in the buffer, integrator, and comparator can
now be cancelled by repeating this entire sequence with the
inputs shorted and subtracting the results from the original
reading. For this phase INT
2
switch is closed to give the same
common-mode voltage as the measurement cycle. This
assures excellent CMRR. At the end of the cycle the data in the
up/down results counter is accurate to 0.02% of full scale and is
sent to the display driver for decoding and multiplexing.
FIGURE 1. ANALOG BLOCK DIAGRAM
FIGURE 2. INTEGRATOR WAVEFORM FOR NEGATIVE INPUT VOLTAGE SHOWING SUCCESSIVE INTEGRATION PHASES AND
RESIDUE VOLTAGE
+
-
+
-
+
-
+
-
COMPARATOR 1
COMPARATOR 2
INTEGRATOR
100
10
X10
BUFFER
REST, INT
2
INT
1
, INT
2
BUFFER
REF HI
REF LO
INT, IN
INT OUT
IN HI
COMMON
IN LO
INT
TO DIGITAL
SECTION
Z1, X10
DE
DE
INT
1
C
INT
R
INT
C
REF
DE+
DE-
DE-
DE+
REST X10
DE
2
REST
X10
DE
3
DE
1
DE-INTEGRATE
ZERO-INTEGRATE
INT
1
INTEGRATE
ZERO-INTEGRATE
AND LATCH
INTEGRATOR
RESIDUE
VOLTAGE
2000
CLOCKS
1000 CLOCKS
10,000 CLOCKS
NOTE: Shaded area greatly expanded
in time and amplitude.
1000 CLOCKS
ICL7129
3-36
COMMON, DGND, and "Low Battery"
The COMMON and DGND (Digital GrouND) outputs of the
ICL7129 are generated from internal zener diodes
(Figure 3). COMMON is included primarily to set the com-
mon-mode voltage for battery operation or for any system
where the input signals float with respect to the power sup-
plies. It also functions as a pre-regulator for an external pre-
cision reference voltage source. The voltage between DGND
and V+ is the supply voltage for the logic section of the
ICL7129 including the display multiplexer and drivers. Both
COMMON and DGND are capable of sinking current from
external loads, but caution should be taken to ensure that
these outputs are not overloaded. Figure 4 shows the con-
nection of external logic circuitry to the ICL7129. This con-
nection will work providing that the supply current
requirements of the logic do not exceed the current sink
capability of the DGND pin. If more supply current is
required, the buffer in Figure 5 can be used to keep the load-
ing on DGND to a minimum. COMMON can source approxi-
mately 12mA while DGND has no source capability.
The "LOW BATTERY" annunciator of the display is turned on
when the voltage between V+ and V- drops below 7.2V typi-
cally. The exact point at which this occurs is determined by
the 6.3V zener diode and the threshold voltage of the
N-Channel transistor connected to the V- rail in Figure 3. As
the supply voltage decreases, the N-Channel transistor
connected to the V-rail eventually turns off and the "LOW
BATTERY" input to the logic section is pulled HIGH, turning
on the "LOW BATTERY" annunciator.
I/O Ports
Four pins of the ICL7129 can be used as either inputs or out-
puts. The specific pin numbers and functions are described
in the Pin Description table. If the output function of the pin is
not desired in an application it can easily be overridden by
connecting the pin to V+ (HI) or DGND (LO). This connection
will not damage the device because the output impedance of
these pins is quite high. A simplified schematic of these
input/output pins is shown in Figure 6. Since there is approx-
imately 500k
in series with the output driver, the pin (when
used as an output) can only drive very light loads such as
4000 series, 74CXX type CMOS logic, or other high input
impedance devices. The output drive capability of these four
pins is limited to 3
A, nominally, and the input switching
threshold is typically DGND + 2V.
LATCH/HOLD, Overrange, and Underrange Timing
The LATCH/HOLD output (pin 22) will be pulled low during
the last 100 clock cycles of each full conversion cycle. Dur-
ing this time the final data from the ICL7129 counter is
latched and transferred to the display decoder and multi-
plexer. The conversion cycle and LATCH/HOLD timing are
directly related to the clock frequency. A full conversion cycle
takes 30,000 clock cycles which is equivalent to 60,000
oscillator cycles. OverRange (OR pin 20) and UnderRange
N
+
-
"LOW
BATTERY"
P
N
24
V+
28 COMMON
36
DGND
23
V-
3.2V
5V
LOGIC
SECTION
FIGURE 3. BIASING STRUCTURE FOR COMMON AND DGND
V+
EXTERNAL
LOGIC
ICL7129
DGND
36
24
I
LOGIC
23
V-
FIGURE 4. DGND SINK CURRENT
V+
EXTERNAL
LOGIC
ICL7129
DGND
36
24
23
V-
-
+
EXTERNAL
LOGIC
CURRENT
FIGURE 5. BUFFERED DGND
DP4/OR PIN 20
DP3/UR PIN 21
LATCH/HOLD PIN 22
CONTINUITY PIN 27
ICL7129
500k
FIGURE 6. "WEAK OUTPUT"
ICL7129
3-37
(UR pin 21) outputs are latched on the falling edge of
LATCH/HOLD and remain in that state until the end of the
next conversion cycle. In addition, digits 1 through 4 are
blanked during overrange. All three of these pins are "weak
outputs" and can be overridden with external drivers or pull-
up resistors to enable their input functions as described in
the Pin Description table.
Instant Continuity
A comparator with a built-in 200mV offset is connected
directly between INPUT HI and INPUT LO of the ICL7129
(Figure 7). The CONTINUITY output (pin 27) will be pulled
high whenever the voltage between the analog inputs is less
than 200mV. This will also turn on the "CONTINUITY"
annunciator on the display. The CONTINUITY output may be
used to enable an external alarm or buzzer, thereby giving
the ICL7129 an audible continuity checking capability.
Since the CONTINUITY output is one of the four "weak out-
puts" of the ICL7129, the "continuity" annunciator on the dis-
play can be driven by an external source if desired. The
continuity function can be overridden with a pull-down resistor
connected between CONTINUITY pin and DGND (pin 36).
Display Configuration
The ICL7129 is designed to drive a triplexed liquid crystal
display. This type of display has three backplanes and is driven
in a multiplexed format similar to the ICM7231 display driver
family. The specific display format is shown in Figure 8. Notice
that the polarity sign, decimal points, "LOW BATTERY", and
"CONTINUITY" annunciators are directly driven by the
ICL7129. The individual segments and annunciators are
addressed in a manner similar to row-column addressing. Each
backplane (row) is connected to one-third of the total number of
segments. BP1 has all F, A, and B segments of the four least
significant digits. BP2 has all of the C, E, and G segments. BP3
has all D segments, decimal points, and annunciators. The seg-
ment lines (columns) are connected in groups of three bringing
all segments of the display out on just 12 lines.
Annunciator Drive
A special display driver output is provided on the ICL7129
which is intended to drive various kinds of annunciators on
custom multiplexed liquid crystal displays. The ANNUNClATOR
DRIVE output (pin 3) is a squarewave signal running at the
backplane frequency, approximately 100Hz. This signal
swings from V
DISP
to V+ and is in sync with the three back-
plane outputs BP1, BP2, and BP3. Figure 9 shows these
four outputs on the same time and voltage scales.
Any annunciator associated with any of the three backplanes
can be turned on simply by connecting it to the ANNUNClA-
TOR DRIVE pin. To turn an annunciator off connect if to its
backplane. An example of a display and annunciator drive
scheme is shown in Figure 10.
+
-
BUFFER
500k
IN HI
COMMON
IN LO
V
200mV
+
-
+
-
CONTINUITY
TO DISPLAY
DRIVER
(NOT LATCHED)
FIGURE 7. "INSTANT CONTINUITY" COMPARATOR AND
OUTPUT STRUCTURE
a
b
c
d
f
g
e
a
b
c
d
f
g
e
B1, C1, CONTINUITY
BACKPLANE
CONNECTIONS
BP1
BP2
BP3
A1, G1, D1
F1, E1, DP1
B2, C2, LOW BATTERY
A2, G2, D2
F2, E2, DP2
F4, E4, DP4
A4, G4, D4
B4, C4, BC5
F3, E3, DP3
A3, G3, D3
B3, C3, MINUS
f
e
a
b
c
d
f
g
e
a
b
c
d
f
g
e
LOW BATTERY CONTINUITY
c
a
b
c
d
f
g
e
a
b
c
d
f
g
e
f
e
a
b
c
d
f
g
e
a
b
c
d
f
g
e
LOW BATTERY CONTINUITY
c
FIGURE 8. TRIPLEXED LIQUID CRYSTAL DISPLAY LAYOUT FOR ICL7129
ICL7129
3-38
Display Temperature Compensation
For most applications an adequate display can be obtained by
connecting V
DlSP
(pin 19) to DGND (pin 36). In applications
where a wide temperature range is encountered, the voltage
drive levels for some triplexed liquid crystal displays may need
to vary with temperature in order to maintain good display
contrast and viewing angle. The amount of temperature
compensation will depend upon the type of liquid crystal used.
Display manufacturers can supply the temperature compen-
sation requirements for their displays. Figure 11 shows two
circuits that can be adjusted to give a temperature compensa-
tion of
+10mV/
o
C between V+ and V
DISP
. The diode
between DGND and V
DISP
should have a low turn-on voltage
to assure that no forward current is injected into the chip if
V
DISP
is more negative than DGND.
Component Selection
There are only three passive components around the
ICL7129 that need special consideration in selection. They
are the reference capacitor, integrator resistor, and integrator
capacitor. There is no auto-zero capacitor like that found in
earlier integrating A/D converter designs.
The integrating resistor is selected to be high enough to
assure good current Iinearity from the buffer amplifier and
integrator and low enough that PC board leakage is not a
problem. A value of 150k
should be optimum for most appli-
cations. The integrator capacitor is selected to give an opti-
mum integrator swing at full-scale. A large integrator swing will
reduce the effect of noise sources in the comparator but will
affect rollover error if the swing gets too close to the positive
rail (
0.7V). This gives an optimum swing of
2.5V at full-
scale. For a 150k
integrating resistor and 2 conversions per
second the value is 0.1
F. For different conversion rates, the
value will change in inverse proportion. A second requirement
for good linearity is that the capacitor have low dielectric
absorption. Polypropylene caps give good performance at a
reasonable price. Finally the foil side of the cap should be
connected to the integrator output to shield against pickup.
The only requirement for the reference cap is that it be low
leakage. In order to reduce the effects of stray capacitance,
a 1
F value is recommended.
Clock Oscillator
The ICL7129 achieves its digital range changing by integrat-
ing the input signal for 1000 clock pulses (2,000 oscillator
cycles) on the 2V scale and 10,000 clock pulses on the
200mV scale. To achieve complete rejection of 60Hz on both
scales, an oscillator frequency of 120kHz is required, giving
two conversions per second.
ON SEG.
BP1
BP2
BP3
FIGURE 9. TYPICAL BACKPLANE AND ANNUNCIATOR
DRIVE WAVEFORM
FIGURE 10. MULTIMETER EXAMPLE SHOWING USE OF
ANNUNCIATOR DRIVE OUTPUT
LOW BATTERY CONTINUITY
m
K
M
BACKPLANE
ANNUNCIATOR
AMPS
VOLTS
BACKPLANE
ANNUNCIATOR
V
DISP
ICL7129
DGND
+
-
19
36
23
24
1N4148
5K
75K
39K
200K
ICL7611
V+
V-
V
DISP
ICL7129
DGND
19
36
23
24
V+
V-
18K
39K
20K
2N2222
FIGURE 11. TWO METHODS FOR TEMPERATURE COMPENSATING THE LIQUID CRYSTAL DISPLAY
ICL7129
3-39
In low resolution applications, where the converter uses only
3
1
/
2
digits and 100
V resolution, an R-C type oscillator is ade-
quate. In this application a C of 51pF is recommended and the
resistor value selected from f
OSC
= 0.45/RC. However, when
the converter is used to its full potential (4
1
/
2
digits and 10
V
resolution) a crystal oscillator is recommended to prevent the
noise from increasing as the input signal is increased due to
frequency jitter of the R-C oscillator. Both R-C and crystal oscil-
lator circuits are shown in Figure 12.
Powering the ICL7129
The ICL7129 may be operated as a battery powered hand-held
instrument or integrated into larger systems that have more
sophisticated power supplies. Figures 13, 14, and 15 show
various powering modes that may be used with the ICL7129.
The standard supply connection using a 9V battery is shown
in the Typical Application Schematic.
The power connection for systems with +5V and -5V sup-
plies available is shown in Figure 13. Notice that measure-
ments are with respect to ground. COMMON is also tied to
INLO to remove any common-mode voltage swing on the
integrator amplifier inputs.
It is important to notice that in Figure 13, digital ground of the
ICL7129 (DGND pin 36) is not directly connected to power
supply ground. DGND is set internally to approximately 5V
less than the V+ terminal and is not intended to be used as a
power input pin. It may be used as the ground reference for
external logic, as shown in Figure 4 and 5. In Figure 4, DGND
is used as the negative supply rail for external logic provided
that the supply current for the external logic does not cause
excessive loading on DGND. The DGND output can be buff-
ered as shown in Figure 5. Here, the logic supply current is
shunted away from the ICL7129 keeping the load on DGND
low. This treatment of the DGND output is necessary to insure
compatibility when the external logic is used to interface
directly with the logic inputs and outputs of the ICL7129.
When a battery voltage between 3.8V and 6V is desired for
operation, a voltage doubling circuit should be used to bring
the voltage on the ICL7129 up to a level within the power sup-
ply voltage range. This operating mode is shown in Figure 14.
Again measurements are made with respect to COMMON
since the entire system is floating. Voltage doubling is
accomplished by using an ICL7660 CMOS voltage converter
and two inexpensive electrolytic capacitors. The same princi-
ple applies in Figure 15 where the ICL7129 is being used in
a system with only a single +5V power supply. Here mea-
surements are made with respect to power supply ground.
ICL7129
2
40
75k
51pF
1
ICL7129
2
40
27k
10pF
1
120kHz
5pF
V+
V-
CRYSTAL MODE:
PARALLEL
R
S
< 50k
C
L
< 12pF
C
O
< 5pF
FIGURE 12. RC AND CRYSTAL OSCILLATOR CIRCUITS
ICL7129
24
34
35
28
33
32
23
36
ICL8089
+5V
-5V
0.1
F
0.1
F
0.1
F
V
IN
V-
V+
REF HI
REF LO
DGND
COM
IN HI
IN LO
FIGURE 13. POWERING THE ICL7129 FROM +5V AND -5V
ICL7129
24
34
35
28
33
32
23
36
10
F
V
IN
V-
V+
+
-
2
4
5
+
10
F
ICL7660
3
+
8
3.8V TO
6V
+
-
REF HI
REF LO
DGND COM
IN HI
IN LO
FIGURE 14. POWERING THE ICL7129 FROM A 3.8V TO 6V BATTERY
ICL7129
24
34
35
28
33
32
23
36
ICL8089
+5V
10
F
0.1
F
0.1
F
V
IN
V-
V+
+
-
2
4
5
+
10
F
ICL7660
3
+
8
FIGURE 15. POWERING THE ICL7129 FROM A SINGLE
POLARITY POWER SUPPLY
ICL7129
3-40
A single polarity power supply can be used to power the
ICL7129 in applications where battery operation is not
appropriate or convenient only if the power supply is isolated
from system ground. Measurements must be made with
respect to COMMON or some other voltage within its input
common-mode range.
Voltage References
The COMMON output of the ICL7129 has a temperature
coefficient of
80ppm/
o
C typically. This voltage is only suit-
able as a reference voltage for applications where ambient
temperature variations are expected to be minimal. When
the ICL7129 is used in most environments, other voltage ref-
erences should be considered. The diagram in the Typical
Application Schematic and Figure 15 show the ICL8069
1.2V band-gap voltage source used as the reference for the
ICL7129, and the COMMON output as its pre-regulator. The
reference voltage for the ICL7129 is set to 1.000V for both
2V and 200mV full-scale operation.
Multiple Integration A/D Converter
Equations
Oscillator Frequency
f
OSC
= 0.45/RC
C
OSC
> 50pF; R
OSC
> 50k
f
OSC
(Typ) = 120kHz
or
f
OSC
= 120kHz Crystal (Recommended)
Oscillator Period
t
OSC
= 1/f
OSC
Integration Clock Period
t
CLOCK
= 2
*
t
OSC
Integration Period
t
INT(2V)
= 1000
*
t
CLOCK
(Range = 1)
t
INT(200mV)
= 10,000
*
t
CLOCK
(Range = 0)
60/50Hz Rejection Criterion
t
INT
/t
60Hz
or t
INT
/t
50Hz
= Integer
Optimum Integration Current
I
INT
= 13
A
Full Scale Analog Input Voltage
V
INFS
(Typ) = 200mV or 2V
Integrate Resistor
R
INT
= V
INFS
/I
INT
R
INT
(Typ) = 150k
Integrate Capacitor
Integrator Output Voltage Swing
V
INT
Maximum Swing:
(V- + 0.5V) < V
INT
< (V+ - 0.7V)
Display Count
(2V Range)
(200mV Range)
Minimum V
REF
: 500mV
Common Mode Input Voltage
(V- + 1V) < V
IN
< (V+ - 0.5V)
Auto Zero Capacitor: C
AZ
not used
Reference Capacitor: 0.1
F < C
REF
< 1
F
V
COM
Biased Between V+ and V-.
V
COM
V+ -2.9V
Regulation lost when V+ to V- <
6.4V.
If V
COM
is externally pulled down to (V+ to V-)/2, the
V
COM
circuit will turn off.
Power Supply: Single 9V
V+ - V- = 9V
Digital supply is generated internally
V
GND
V+ - 4.5V
Display: Triplexed LCD
Continuity Output On if
V
INHI
to V
INLO
< 200mV
Conversion Cycle (In Both Ranges)
t
CYC
= t
CLOCK
x 30,000
C
INT
t
INT
(
)
I
INT
(
)
V
INT
----------------------------------
=
V
INT
t
INT
(
)
I
INT
(
)
C
INT
----------------------------------
=
COUNT
10 000
V
IN
V
REF
-----------------
Range = 1
(
)
,
=
COUNT
10 000
V
IN
10
V
REF
-----------------------
Range = 0
(
)
,
=
REST X10
DE
2
REST
X10
DE
3
DE
1
DE-INTEGRATE
ZERO-INTEGRATE
INT
1
INTEGRATE
ZERO-INTEGRATE
AND LATCH
INTEGRATOR
RESIDUE
VOLTAGE
2000
CLOCKS
1000 CLOCKS
10,000 CLOCKS
NOTE: Shaded area greatly expanded
in time and amplitude.
1000 CLOCKS
ICL7129
3-41
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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Intersil Corporation
P. O. Box 883, Mail Stop 53-204
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TEL: (407) 724-7000
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TEL: (32) 2.724.2111
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Taiwan Limited
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FAX: (886) 2 2715 3029
ICL7129
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