3-36
TM
FN3179.2
ICL7660S
Super Voltage Converter
The ICL7660S Super Voltage Converter is a monolithic
CMOS voltage conversion IC that guarantees significant
performance advantages over other similar devices. It is a
direct replacement for the industry standard ICL7660 offering
an extended operating supply voltage range up to 12V, with
lower supply current. No external diode is needed for the
ICL7660S. In addition, a Frequency Boost pin has been
incorporated to enable the user to achieve lower output
impedance despite using smaller capacitors. All
improvements are highlighted in the Electrical Specifications
section. Critical parameters are guaranteed over the entire
commercial, industrial and military temperature ranges.
The ICL7660S performs supply voltage conversion from
positive to negative for an input range of 1.5V to 12V,
resulting in complementary output voltages of -1.5V to -12V.
Only 2 non-critical external capacitors are needed for the
charge pump and charge reservoir functions. The ICL7660S
can be connected to function as a voltage doubler and will
generate up to 22.8V with a 12V input. It can also be used as
a voltage multiplier or voltage divider.
The chip contains a series DC power supply regulator, RC
oscillator, voltage level translator, and four output power
MOS switches. The oscillator, when unloaded, oscillates at a
nominal frequency of 10kHz for an input supply voltage of
5.0V. This frequency can be lowered by the addition of an
external capacitor to the "OSC" terminal, or the oscillator
may be over-driven by an external clock.
The "LV" terminal may be tied to GND to bypass the internal
series regulator and improve low voltage (LV) operation. At
medium to high voltages (3.5V to 12V), the LV pin is left
floating to prevent device latchup.
Features
Guaranteed Lower Max Supply Current for All
Temperature Ranges
Wide Operating Voltage Range 1.5V to 12V
100% Tested at 3V
No External Diode Over Full Temperature and Voltage
Range
Boost Pin (Pin 1) for Higher Switching Frequency
Guaranteed Minimum Power Efficiency of 96%
Improved Minimum Open Circuit Voltage Conversion
Efficiency of 99%
Improved SCR Latchup Protection
Simple Conversion of +5V Logic Supply to
5V Supplies
Simple Voltage Multiplication V
OUT
= (-)nV
IN
Easy to Use - Requires Only 2 External Non-Critical
Passive Components
Improved Direct Replacement for Industry Standard
ICL7660 and Other Second Source Devices
Applications
Simple Conversion of +5V to
5V Supplies
Voltage Multiplication V
OUT
=
nV
IN
Negative Supplies for Data Acquisition Systems and
Instrumentation
RS232 Power Supplies
Supply Splitter, V
OUT
=
V
S
/2
Pinouts
ICL7660S (PDIP, SOIC)
TOP VIEW
ICL7660S (CAN)
TOP VIEW
Ordering Information
PART
NUMBER
TEMP.
RANGE
(
o
C)
PACKAGE
PKG. NO.
ICL7660SCBA
0
to 70
8 Ld P SOIC (N)
M8.15
ICL7660SCPA
0
to 70
8 Ld PDIP
E8.3
ICL7660SIBA
-40
to 85
8 Ld P SOIC (N)
M8.15
ICL7660SIPA
-40
to 85
8 Ld PDIP
E8.3
ICL7660SMTV
(Note)
-55 to 125
8 Pin Metal Can
T8.C
NOTE: Add /883B to part number if 883B processing is required.
BOOST
CAP+
GND
CAP-
1
2
3
4
8
7
6
5
V+
OSC
LV
V
OUT
V+ (AND CASE)
LV
CAP+
CAP-
BOOST
GND
OSC
V
OUT
2
4
6
1
3
7
5
8
Data Sheet
April 1999
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002. All Rights Reserved
3-37
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13.0V
LV and OSC Input Voltage (Note 1)
V+ < 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V+ + 0.3V
V+ > 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . V+ -5.5V to V+ +0.3V
Current into LV (Note 1)
V+ > 3.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
A
Output Short Duration
V
SUPPLY
5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Continuous
Storage Temperature Range . . . . . . . . . . . . . . . . . . -65
o
C to 150
o
C
Operating Conditions
Temperature Range
ICL7660SM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
ICL7660SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
ICL7660SC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to 70
o
C
Thermal Resistance (Typical, Note 2)
JA
(
o
C/W)
JC
(
o
C/W)
PDIP. . . . . . . . . . . . . . . . . . . . . . . . . . .
150
N/A
Plastic SOIC. . . . . . . . . . . . . . . . . . . . .
170
N/A
Metal Can. . . . . . . . . . . . . . . . . . . . . . .
155
70
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Connecting any terminal to voltages greater than V+ or less than GND may cause destructive latchup. It is recommended that no inputs from
sources operating from external supplies be applied prior to "power up" of ICL7660S.
2.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
V+ = 5V, T
A
= 25
o
C, OSC = Free running, Test Circuit Figure 12, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Supply Current (Note 5)
I+
R
L
=
, 25
o
C
-
80
160
A
0
o
C < T
A
< +70
o
C
-
-
180
A
-40
o
C < T
A
< 85
o
C
-
-
180
A
-55
o
C < T
A
< 125
o
C
-
-
200
A
Supply Voltage Range - High
(Note 6)
V+
H
R
L
= 10K, LV Open, T
MIN
< T
A
< T
MAX
3.0
-
12
V
Supply Voltage Range - Low
V+
L
R
L
= 10K, LV to GND, T
MIN
< T
A
< T
MAX
1.5
-
3.5
V
Output Source Resistance
R
OUT
I
OUT
= 20mA
-
60
100
I
OUT
= 20mA, 0
o
C < T
A
< 70
o
C
-
-
120
I
OUT
= 20mA, -25
o
C < T
A
< 85
o
C
-
-
120
I
OUT
= 20mA, -55
o
C < T
A
< 125
o
C
-
-
150
I
OUT
= 3mA, V+ = 2V, LV = GND,
0
o
C < T
A
< 70
o
C
-
-
250
I
OUT
= 3mA, V+ = 2V, LV = GND,
-40
o
C < T
A
< 85
o
C
-
-
300
I
OUT
= 3mA, V+ = 2V, LV = GND,
-55
o
C < T
A
< 125
o
C
-
-
400
Oscillator Frequency (Note 5)
f
OSC
C
OSC
= 0, Pin 1 Open or GND
5
10
-
kHz
C
OSC
= 0, Pin 1 = V+
-
35
-
kHz
Power Efficiency
P
EFF
R
L
= 5k
96
98
-
%
T
MIN
< T
A
< T
MAX
R
L
= 5k
95
97
-
-
Voltage Conversion Efficiency
V
OUT
EFF
R
L
=
99
99.9
-
%
ICL7660S
3-38
Oscillator Impedance
Z
OSC
V+ = 2V
-
1
-
M
V+ = 5V
-
100
-
k
NOTES:
3. Derate linearly above 50
o
C by 5.5mW/
o
C
4. In the test circuit, there is no external capacitor applied to pin 7. However, when the device is plugged into a test socket, there is usually a very
small but finite stray capacitance present, of the order of 5pF.
5. The Intersil ICL7660S can operate without an external diode over the full temperature and voltage range. This device will function in existing
designs which incorporate an external diode with no degradation in overall circuit performance.
6. All significant improvements over the industry standard ICL7660 are highlighted.
Electrical Specifications
V+ = 5V, T
A
= 25
o
C, OSC = Free running, Test Circuit Figure 12, Unless Otherwise Specified (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Typical Performance Curves
(Test Circuit Figure 12)
FIGURE 1. OPERATING VOLTAGE AS A
FUNCTION OF TEMPERATURE
FIGURE 2. OUTPUT SOURCE RESISTANCE AS A
FUNCTION OF SUPPLY VOLTAGE
FIGURE 3. OUTPUT SOURCE RESISTANCE AS A
FUNCTION OF TEMPERATURE
FIGURE 4. POWER CONVERSION EFFICIENCY AS A
FUNCTION OF OSCILLATOR FREQUENCY
-55
-25
0
25
50
100
125
12
10
8
6
4
2
0
SU
P
P
L
Y
VO
L
T
A
G
E (
V
)
TEMPERATURE (
o
C)
SUPPLY VOLTAGE RANGE
(NO DIODE REQUIRED)
250
200
150
100
50
0
0
2
4
6
8
10
12
SUPPLY VOLTAGE (V)
O
U
T
P
UT
S
O
URCE
RE
S
I
S
T
ANCE
(
)
T
A
= 125
o
C
T
A
= 25
o
C
T
A
= -55
o
C
350
300
250
200
150
100
50
0
O
U
T
P
UT
S
O
URC
E
RE
S
I
S
T
ANCE
(
)
-50
-25
0
25
50
75
100
125
TEMPERATURE (
o
C)
I
OUT
= 20mA,
V+ = 12V
I
OUT
= 20mA ,
V+ = 5V
I
OUT
= 20mA,
V+ = 5V
I
OUT
= 3mA,
V+ = 2V
98
96
94
92
90
88
86
84
82
80
P
O
W
E
R CO
N
V
E
R
S
I
O
N
E
F
F
I
CIE
NCY
(
%
)
100
1k
10k
50k
OSC FREQUENCY F
OSC
(Hz)
V+ = 5V
T
A
= 25
o
C
I
OUT
= 1mA
ICL7660S
3-39
FIGURE 5. FREQUENCY OF OSCILLATION AS A FUNCTION
OF EXTERNAL OSCILLATOR CAPACITANCE
FIGURE 6. UNLOADED OSCILLATOR FREQUENCY AS A
FUNCTION OF TEMPERATURE
FIGURE 7. OUTPUT VOLTAGE AS A FUNCTION
OF OUTPUT CURRENT
FIGURE 8. SUPPLY CURRENT AND POWER CONVERSION
EFFICIENCY AS A FUNCTION OF LOAD
CURRENT
FIGURE 9. OUTPUT VOLTAGE AS A FUNCTION OF OUTPUT
CURRENT
FIGURE 10. SUPPLY CURRENT AND POWER CONVERSION
EFFICIENCY AS A FUNCTION OF LOAD CURRENT
Typical Performance Curves
(Test Circuit Figure 12) (Continued)
1
10
100
1k
O
S
CI
L
L
A
T
O
R
F
R
E
Q
UE
NCY
f
OS
C
(k
H
z
)
10
9
8
7
6
5
4
3
2
1
0
C
OSC
(pF)
V+ = 5V
T
A
= 25
o
C
O
S
CIL
L
A
T
O
R
F
R
E
Q
UE
NCY
f
OS
C
(k
H
z
)
20
18
16
14
12
10
8
-55
-25
0
25
50
75
100
125
TEMPERATURE (
o
C)
V+ = 10V
V+ = 5V
O
U
T
P
UT
V
O
L
T
AG
E
(
V
)
1
0
-1
-2
-3
-4
-5
0
10
20
30
40
LOAD CURRENT (mA)
V+ = 5V
T
A
= 25
o
C
P
O
W
E
R CO
NV
E
R
S
I
O
N
E
F
F
I
CIE
NCY
(
%
)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
LOAD CURRENT (mA)
0
10
20
30
40
50
60
V+ = 5V
T
A
= 25
o
C
S
U
P
P
L
Y
CURRE
NT
(
m
A)
O
U
T
P
UT
V
O
L
T
AG
E
(
V
)
2
1
0
-1
-2
0
1
2
3
4
5
6
7
8
9
LOAD CURRENT (mA)
T
A
= 25
o
C
V+ = 2V
100
90
80
70
60
50
40
30
20
10
0
16
14
12
10
8
6
4
2
0
0
1.5
3
4.5
6
7.5
9
LOAD CURRENT (mA)
V+ = 2V
T
A
= 25
o
C
P
O
W
E
R CO
NV
E
R
S
I
O
N
E
F
F
I
CIE
NCY
(
%
)
S
U
P
P
L
Y
CURRE
NT
(
m
A)
(
N
O
T
E
8
)
ICL7660S
3-40
Detailed Description
The ICL7660S contains all the necessary circuitry to
complete a negative voltage converter, with the exception of
2 external capacitors which may be inexpensive 10
F
polarized electrolytic types. The mode of operation of the
device may be best understood by considering Figure 13,
which shows an idealized negative voltage converter.
Capacitor C
1
is charged to a voltage, V+, for the half cycle
when switches S
1
and S
3
are closed. (Note: Switches S
2
and S
4
are open during this half cycle.) During the second
half cycle of operation, switches S
2
and S
4
are closed, with
S
1
and S
3
open, thereby shifting capacitor C
1
to C
2
such
that the voltage on C
2
is exactly V+, assuming ideal switches
and no load on C
2
. The ICL7660S approaches this ideal
situation more closely than existing non-mechanical circuits.
In the ICL7660S, the 4 switches of Figure 13 are MOS
power switches; S
1
is a P-Channel devices and S
2
, S
3
and
S
4
are N-Channel devices. The main difficulty with this
approach is that in integrating the switches, the substrates of
S
3
and S
4
must always remain reverse biased with respect
to their sources, but not so much as to degrade their "ON"
resistances. In addition, at circuit start up, and under output
short circuit conditions (V
OUT
= V+), the output voltage must
be sensed and the substrate bias adjusted accordingly.
Failure to accomplish this would result in high power losses
and probable device latchup.
This problem is eliminated in the ICL7660S by a logic network
which senses the output voltage (V
OUT
) together with the
level translators, and switches the substrates of S
3
and S
4
to
the correct level to maintain necessary reverse bias.
The voltage regulator portion of the ICL7660S is an integral
part of the anti-latchup circuitry, however its inherent voltage
drop can degrade operation at low voltages. Therefore, to
improve low voltage operation "LV" pin should be connected
to GND, disabling the regulator. For supply voltages greater
than 3.5V the LV terminal must be left open to insure latchup
proof operation, and prevent device damage.
Theoretical Power Efficiency
Considerations
In theory a voltage converter can approach 100% efficiency
if certain conditions are met:
1. The drive circuitry consumes minimal power.
2. The output switches have extremely low ON resistance
and virtually no offset.
3. The impedance of the pump and reservoir capacitors are
negligible at the pump frequency.
FIGURE 11. OUTPUT SOURCE RESISTANCE AS A FUNCTION OF OSCILLATOR FREQUENCY
NOTE:
7. These curves include in the supply current that current fed directly into the load R
L
from the V+ (See Figure 12). Thus, approximately half the
supply current goes directly to the positive side of the load, and the other half, through the ICL7660S, to the negative side of the load. Ideally,
V
OUT
2V
IN
, I
S
2I
L
, so V
IN
x I
S
V
OUT
x I
L
.
Typical Performance Curves
(Test Circuit Figure 12) (Continued)
O
U
T
P
U
T
RE
S
I
S
T
ANCE
(
)
400
300
200
100
0
100
1k
10k
100k
OSCILLATOR FREQUENCY (Hz)
V+ = 5V
T
A
= 25
o
C
I = 10mA
C
1
= C
2
=
10
F
C
1
= C
2
=
1
F
C
1
= C
2
=
100
F
1
2
3
4
8
7
6
5
+
-
C
1
10
F
I
S
V+
(+5V)
I
L
R
L
-
V
OUT
C
2
10
F
ICL7660S
V+
+
-
NOTE: For large values of C
OSC
(>1000pF) the values of C
1
and C
2
should be increased to 100
F.
FIGURE 12. ICL7660S TEST CIRCUIT
ICL7660S
3-41
The ICL7660S approaches these conditions for negative
voltage conversion if large values of C
1
and C
2
are used.
ENERGY IS LOST ONLY IN THE TRANSFER OF CHARGE
BETWEEN CAPACITORS IF A CHANGE IN VOLTAGE
OCCURS. The energy lost is defined by:
E =
1
/
2
C
1
(V
1
2
- V
2
2
)
where V
1
and V
2
are the voltages on C
1
during the pump
and transfer cycles. If the impedances of C
1
and C
2
are
relatively high at the pump frequency (refer to Figure 13)
compared to the value of R
L
, there will be substantial
difference in the voltages V
1
and V
2
. Therefore it is not only
desirable to make C
2
as large as possible to eliminate output
voltage ripple, but also to employ a correspondingly large
value for C
1
in order to achieve maximum efficiency of
operation.
Do's and Don'ts
1. Do not exceed maximum supply voltages.
2. Do not connect LV terminal to GND for supply voltage
greater than 3.5V.
3. Do not short circuit the output to V
+
supply for supply
voltages above 5.5V for extended periods, however, tran-
sient conditions including start-up are okay.
4. When using polarized capacitors, the + terminal of C
1
must be connected to pin 2 of the ICL7660S and the +
terminal of C
2
must be connected to GND.
5. If the voltage supply driving the ICL7660S has a large
source impedance (25
- 30
), then a 2.2
F capacitor
from pin 8 to ground may be required to limit rate of rise
of input voltage to less than 2V/
s.
6. User should insure that the output (pin 5) does not go
more positive than GND (pin 3). Device latch up will occur
under these conditions.
A 1N914 or similar diode placed in parallel with C
2
will
prevent the device from latching up under these condi-
tions. (Anode pin 5, Cathode pin 3).
Typical Applications
Simple Negative Voltage Converter
The majority of applications will undoubtedly utilize the
ICL7660S for generation of negative supply voltages. Figure
14 shows typical connections to provide a negative supply
where a positive supply of +1.5V to +12V is available. Keep
in mind that pin 6 (LV) is tied to the supply negative (GND)
for supply voltage below 3.5V.
The output characteristics of the circuit in Figure 14 can be
approximated by an ideal voltage source in series with a
resistance as shown in Figure 14B. The voltage source has
a value of -(V+). The output impedance (R
O
) is a function of
the ON resistance of the internal MOS switches (shown in
Figure 13), the switching frequency, the value of C
1
and C
2
,
and the ESR (equivalent series resistance) of C
1
and C
2
. A
good first order approximation for R
O
is:
Combining the four R
SWX
terms as R
SW
, we see that:
R
SW
, the total switch resistance, is a function of supply
voltage and temperature (See the Output Source Resistance
graphs), typically 23
at 25
o
C and 5V. Careful selection of C
1
and C
2
will reduce the remaining terms, minimizing the output
impedance. High value capacitors will reduce the 1/(f
PUMP
x
C
1
) component, and low ESR capacitors will lower the ESR
term. Increasing the oscillator frequency will reduce the
1/(f
PUMP
x C
1
) term, but may have the side effect of a net
increase in output impedance when C
1
> 10
F and is not long
V
OUT
=
-
V
IN
C
2
V
IN
C
1
S
3
S
4
S
1
S
2
8
2
4
3
3
5
7
FIGURE 13. IDEALIZED NEGATIVE VOLTAGE CONVERTER
R
O
2(R
SW1
+ R
SW3
+ ESR
C1
) + 2(R
SW2
+ R
SW
4 + ESR
C1
)
+
1
+ ESR
C2
f
PUMP
x
C
1
(f
PUMP
=
f
OSC
, R
SWX
= MOSFET switch resistance)
2
R
O
2 x R
SW
+
1
+ 4 x ESR
C1
+ ESR
C2
f
PUMP
x
C
1
1
2
3
4
8
7
6
5
+
-
10
F
10
F
ICL7660S
V
OUT
=
-
V+
V+
+
-
R
O
V
OUT
V+
+
-
14A.
14B.
FIGURE 14. SIMPLE NEGATIVE CONVERTER AND ITS
OUTPUT EQUIVALENT
ICL7660S
3-42
enough to fully charge the capacitors every cycle. In a typical
application where f
OSC
= 10kHz and C = C
1
= C
2
= 10
F:
Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5, a high value could
potentially swamp out a low 1/f
PUMP
x C
1
) term, rendering
an increase in switching frequency or filter capacitance
ineffective. Typical electrolytic capacitors may have ESRs as
high as 10
.
Output Ripple
ESR also affects the ripple voltage seen at the output. The
total ripple is determined by 2 voltages, A and B, as shown in
Figure 15. Segment A is the voltage drop across the ESR of
C
2
at the instant it goes from being charged by C
1
(current
flowing into C
2
) to being discharged through the load
(current flowing out of C
2
). The magnitude of this current
change is 2 x I
OUT
, hence the total drop is 2 x I
OUT
x
ESR
C2
V. Segment B is the voltage change across C
2
during
time t
2
, the half of the cycle when C
2
supplies current the
load. The drop at B is I
OUT
x t
2
/C
2
V. The peak-to-peak ripple
voltage is the sum of these voltage drops:
Again, a low ESR capacitor will result in a higher
performance output.
Paralleling Devices
Any number of ICL7660S voltage converters may be
paralleled to reduce output resistance. The reservoir
capacitor, C
2
, serves all devices while each device requires
its own pump capacitor, C
1
. The resultant output resistance
would be approximately:
Cascading Devices
The ICL7660S may be cascaded as shown to produce larger
negative multiplication of the initial supply voltage. However,
due to the finite efficiency of each device, the practical limit is
10 devices for light loads. The output voltage is defined by:
V
OUT
= -n(V
IN
),
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be
approximately the weighted sum of the individual ICL7660S
R
OUT
values.
Changing the ICL7660S Oscillator Frequency
It may be desirable in some applications, due to noise or other
considerations, to alter the oscillator frequency. This can be
achieved simply by one of several methods described below.
By connecting the Boost Pin (Pin 1) to V+, the oscillator
charge and discharge current is increased and, hence, the
oscillator frequency is increased by approximately 3
1
/
2
times. The result is a decrease in the output impedance and
ripple. This is of major importance for surface mount
applications where capacitor size and cost are critical.
Smaller capacitors, e.g. 0.1
F, can be used in conjunction
with the Boost Pin in order to achieve similar output currents
compared to the device free running with C
1
= C
2
= 10
F or
100
F. (Refer to graph of Output Source Resistance as a
Function of Oscillator Frequency).
Increasing the oscillator frequency can also be achieved by
overdriving the oscillator from an external clock, as shown in
Figure 18. In order to prevent device latchup, a 1k
resistor
must be used in series with the clock output. In a situation
where the designer has generated the external clock
frequency using TTL logic, the addition of a 10k
pullup
resistor to V+ supply is required. Note that the pump
frequency with external clocking, as with internal clocking,
will be
1
/
2
of the clock frequency. Output transitions occur on
the positive going edge of the clock.
It is also possible to increase the conversion efficiency of the
ICL7660S at low load levels by lowering the oscillator
frequency. This reduces the switching losses, and is shown
in Figure 19. However, lowering the oscillator frequency will
cause an undesirable increase in the impedance of the
pump (C
1
) and reservoir (C
2
) capacitors; this is overcome by
increasing the values of C
1
and C
2
by the same factor that
the frequency has been reduced. For example, the addition
of a 100pF capacitor between pin 7 (OSC and V+ will lower
the oscillator frequency to 1kHz from its nominal frequency
of 10kHz (a multiple of 10), and thereby necessitate
corresponding increase in the value of C
1
and C
2
(from
10
F to 100
F).
R
O
2 x 23 +
1
+ 4 x ESR
C1
+
ESR
C2
(5 x 10
3
x 10 x 10
-6
)
R
O
46 + 20 + 5 x ESR
C
R
OUT
=
R
OUT
(of ICL7660S)
n (number of devices)
V
R IPPL E
1
2
f
PUM P
C
2
--------------------------------------------
2 ESRC
2
I
OUT
+
1
2
3
4
8
7
6
5
+
-
10
F
ICL7660S
V
OUT
V+
+
-
10
F
V+
CMOS
GATE
1k
FIGURE 15. EXTERNAL CLOCKING
ICL7660S
3-43
Positive Voltage Doubling
The ICL7660S may be employed to achieve positive voltage
doubling using the circuit shown in Figure 20. In this
application, the pump inverter switches of the ICL7660S are
used to charge C
1
to a voltage level of V+ -V
F
(where V+ is
the supply voltage and V
F
is the forward voltage on C
1
plus
the supply voltage (V+) is applied through diode D
2
to
capacitor C
2
. The voltage thus created on C
2
becomes
(2V+) - (2V
F
) or twice the supply voltage minus the
combined forward voltage drops of diodes D
1
and D
2
.
The source impedance of the output (V
OUT
) will depend on
the output current, but for V+ = 5V and an output current of
10mA it will be approximately 60
.
Combined Negative Voltage Conversion and
Positive Supply Doubling
Figure 21 combines the functions shown in Figure 14 and
Figure 20 to provide negative voltage conversion and
positive voltage doubling simultaneously. This approach
would be, for example, suitable for generating +9V and -5V
from an existing +5V supply. In this instance capacitors C
1
and C
3
perform the pump and reservoir functions
respectively for the generation of the negative voltage, while
capacitors C2 and C
4
are pump and reservoir respectively
for the doubled positive voltage. There is a penalty in this
configuration which combines both functions, however, in
that the source impedances of the generated supplies will be
somewhat higher due to the finite impedance of the common
charge pump driver at pin 2 of the device.
Voltage Splitting
The bidirectional characteristics can also be used to split a
high supply in half, as shown in Figure 22. The combined
load will be evenly shared between the two sides, and a high
value resistor to the LV pin ensures start-up. Because the
switches share the load in parallel, the output impedance is
much lower than in the standard circuits, and higher currents
can be drawn from the device. By using this circuit, and then
the circuit of Figure 17, +15V can be converted (via +7.5,
and -7.5 to a nominal -15V, although with rather high series
output resistance (
250
).
Regulated Negative Voltage Supply
In Some cases, the output impedance of the ICL7660S can
be a problem, particularly if the load current varies
substantially. The circuit of Figure 23 can be used to
overcome this by controlling the input voltage, via an
ICL7611 low-power CMOS op amp, in such a way as to
maintain a nearly constant output voltage. Direct feedback is
inadvisable, since the ICL7660S's output does not respond
instantaneously to change in input, but only after the
switching delay. The circuit shown supplies enough delay to
accommodate the ICL7660S, while maintaining adequate
feedback. An increase in pump and storage capacitors is
desirable, and the values shown provides an output
impedance of less than 5
to a load of 10mA.
1
2
3
4
8
7
6
5
+
-
ICL7660S
V
OUT
V+
+
-
C
2
C
1
C
OSC
FIGURE 16. LOWERING OSCILLATOR FREQUENCY
1
2
3
4
8
7
6
5
ICL7660S
V+
D
1
D
2
C
1
C
2
V
OUT
=
(2V+)
-
(2V
F
)
+
-
+
-
NOTE: D
1
and D
2
can be any suitable diode.
FIGURE 17. POSITIVE VOLTAGE DOUBLER
1
2
3
4
8
7
6
5
ICL7660S
V+
D
1
D
2
C
4
V
OUT
= (2V+) -
(V
FD1
) - (V
FD2
)
+
-
C
2
+
-
C
3
+
-
V
OUT
= -V
IN
C
1
+
-
FIGURE 18. COMBINED NEGATIVE VOLTAGE CONVERTER
AND POSITIVE DOUBLER
1
2
3
4
8
7
6
5
+
-
+
-
50
F
50
F
+
-
50
F
R
L1
V
OUT
= V+
-
V
-
2
ICL7660S
V+
V-
R
L2
FIGURE 19. SPLITTING A SUPPLY IN HALF
ICL7660S
3-44
Other Applications
Further information on the operation and use of the
ICL7660S may be found in AN051 "Principles and
Applications of the ICL7660 CMOS Voltage Converter".
1
2
3
4
8
7
6
5
+
-
100
F
ICL7660S
100
F
V
OUT
+
-
10
F
ICL7611
+
-
100
50k
+8V
100k
50k
ICL8069
56k
+8V
800k
250k
VOLTAGE
ADJUST
+
-
FIGURE 20. REGULATING THE OUTPUT VOLTAGE
1
2
3
4
8
7
6
5
+
-
ICL7660S
+
-
10
F
16
TTL DATA
INPUT
15
4
10
F
13
14
12
11
+5V LOGIC SUPPLY
RS232
DATA
OUTPUT
IH5142
1
3
+5V
-5V
FIGURE 21. RS232 LEVELS FROM A SINGLE 5V SUPPLY
ICL7660S
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