1
File Number 3181.3
ICL7662
CMOS Voltage Converter
The Intersil ICL7662 is a monolithic high-voltage CMOS
power supply circuit which offers unique performance ad-
vantages over previously available devices. The ICL7662
performs supply voltage conversion from positive to negative
for an input range of +4.5V to +20.0V, resulting in
complementary output voltages of -4.5V to -20V. Only 2
noncritical external capacitors are needed for the charge
pump and charge reservoir functions. The ICL7662 can also
function as a voltage doubler, and will generate output
voltages up to +38.6V with a +20V input.
Contained on chip are a series DC power supply regulator,
RC oscillator, voltage level translator, four output power MOS
switches. A unique logic element senses the most negative
voltage in the device and ensures that the output N-Channel
switch source-substrate junctions are not forward biased.
This assures latchup free operation.
The oscillator, when unloaded, oscillates at a nominal
frequency of 10kHz for an input supply voltage of 15.0V. This
frequency can be lowered by the addition of an external
capacitor to the "OSC" terminal, or the oscillator may be
overdriven by an external clock.
The "LV" terminal may be tied to GROUND to bypass the
internal series regulator and improve low voltage (LV)
operation. At medium to high voltages (+10V to +20V), the
LV pin is left floating to prevent device latchup.
Features
No External Diode Needed Over Entire Temperature
Range
Pin Compatible With ICL7660
Simple Conversion of +15V Supply to -15V Supply
Simple Voltage Multiplication (V
OUT
= (-)nV
IN
)
99.9% Typical Open Circuit Voltage Conversion
Efficiency
96% Typical Power Efficiency
Wide Operating Voltage Range 4.5V to 20.0V
Easy to Use - Requires Only 2 External Non-Critical
Passive Components
Applications
On Board Negative Supply for Dynamic RAMs
Localized
Processor (8080 Type) Negative Supplies
Inexpensive Negative Supplies
Data Acquisition Systems
Up to -20V for Op Amps
Pinouts
ICL7662CBD-0 (SOIC)
TOP VIEW
ICL7662CBD AND IBD (SOIC)
TOP VIEW
ICL7662 (CAN)
TOP VIEW
ICL7662 (PDIP)
TOP VIEW
TEST
NC
CAP+
NC
GND
NC
CAP-
V+
OSC
NC
LV
NC
NC
V
OUT
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NC
TEST
NC
CAP+
GND
NC
NC
V+
NC
OSC
LV
NC
V
OUT
CAP-
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V+
LV
CAP+
TEST
GND
OSC
V
OUT
2
4
6
1
3
7
5
8
TEST
CAP+
GND
CAP-
1
2
3
4
8
7
6
5
V+
OSC
LV
V
OUT
Data Sheet
April 1999
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002. All Rights Reserved
2
Functional Block Diagram
Ordering Information
PART
NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
PKG. NO.
ICL7662CTV
0
to 70
8 Pin Metal Can T8.C
ICL7662CPA
0
to 70
8 Ld PDIP
E8.3
ICL7662CBD-0
0
to 70
14 Ld SOIC (N)
M14.15
ICL7662CBD
0
to 70
14 Ld SOIC (N)
M14.15
ICL7662ITV
-40
to 85
8 Pin Metal Can T8.C
ICL7662IPA
-40
to 85
8 Ld PDIP
E8.3
ICL7662IBD
-40
to 85
14 Ld SOIC (N)
M14.15
ICL7662MTV
(Note 1)
-55
to 125
8 Pin Metal Can T8.C
NOTE:
1. Add /883 to part number if /883B processing is required.
RC
OSCILLATOR
2
VOLTAGE
REGULATOR
LOGIC
NETWORK
OSC
LV
V+
CAP+
CAP-
V
OUT
VOLTAGE
LEVEL
TRANSLATOR
TEST
P
N
ICL7662
3
Absolute Maximum Ratings
Thermal Information
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22V
Oscillator Input Voltage . . . . . . . . -0.3V to (V+ +0.3V) for V+ < 10V
. . . . . . . . . . . . . . . . . (Note 2) (V+ -10V) to (V+ +0.3V) for V+ > 10V
Current Into LV (Note 2). . . . . . . . . . . . . . . . . . . . 20
A for V+ > 10V
Output Short Duration . . . . . . . . . . . . . . . . . . . . . . . . . . .Continuous
Thermal Resistance (Typical, Note 3)
JA
(
o
C/W)
JC
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . .
150
N/A
Plastic SOIC Package . . . . . . . . . . . . .
120
N/A
Metal Can. . . . . . . . . . . . . . . . . . . . . . .
156
68
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2. Connecting any terminal to voltages greater than V+ or less than GND may cause destructive latchup. It is recommended that no inputs from
sources operating from external supplies be applied prior to "power up" of ICL7660S.
3.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
V+ = 15V, T
A
= 25
o
C, C
OSC
= 0, Unless Otherwise Specified. Refer to Figure 14.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage Range - Lo
V+L
R
L
= 10k
, LV = GND
Min < T
A
< Max
4.5
-
11
V
Supply Voltage Range - Hi
V+H
R
L
= 10k
, LV = Open
Min < T
A
< Max
9
-
20
V
Supply Current
I+
R
L
=
, LV = Open
T
A
= 25
o
C
-
0.25
0.60
mA
0
o
C < T
A
< 70
o
C
-40
o
C < T
A
< 85
o
C
-
0.30
0.85
mA
-55
o
C < T
A
< 125
o
C
-
0.40
1.0
mA
Output Source Resistance
R
O
I
O
= 20mA,
LV = Open
T
A
= 25
o
C
-
60
100
0
o
C < T
A
< 70
o
C
-40
o
C < T
A
< 85
o
C
-
70
120
-55
o
C < T
A
< 125
o
C
-
90
150
Supply Current
I+
V+ = 5V, R
L
=
,
LV = GND
T
A
= 25
o
C
-
20
150
A
0
o
C < T
A
< 70
o
C
-40
o
C < T
A
< 85
o
C
-
25
200
A
-55
o
C < T
A
< 125
o
C
-
30
250
A
Output Source Resistance
R
O
V+ = 5V, I
O
= 3mA,
LV = GND
T
A
= 25
o
C
-
125
200
0
o
C < T
A
< 70
o
C
-40
o
C < T
A
< 85
o
C
-
150
250
-55
o
C < T
A
< 125
o
C
-
200
350
Oscillator Frequency
FOSC
-
10
-
kHz
Power Efficiency
P
EFF
R
L
= 2k
T
A
= 25
o
C
93
96
-
%
Min < T
A
< Max
90
95
-
%
Voltage Conversion Efficiency
VoEf
R
L
=
Min < T
A
< Max
97
99.9
-
%
Oscillator Sink or Source
Current
I
OSC
V+ = 5V (V
OSC
= 0V to +5V)
-
0.5
-
A
V+ = 15V (V
OSC
= +5V to +15V)
-
4.0
-
A
NOTE:
4. Pin 1 is a Test pin and is not connected in normal use. When the TEST pin is connected to V+, an internal transmission gate disconnects any
external parasitic capacitance from the oscillator which would otherwise reduce the oscillator frequency from its nominal value.
ICL7662
4
Typical Performance Curves
(See Figure 14, Test Circuit)
FIGURE 1. OUTPUT SOURCE RESISTANCE AS A
FUNCTION OF SUPPLY VOLTAGE
FIGURE 2. OUTPUT SOURCE RESISTANCE AS A
FUNCTION OF SUPPLY VOLTAGE
FIGURE 3. OUTPUT SOURCE RESISTANCE AS A
FUNCTION OF TEMPERATURE
FIGURE 4. POWER CONVERSION EFFICIENCY AND
OUTPUT SOURCE RESISTANCE AS A
FUNCTION OF OSCILLATOR FREQUENCY
FIGURE 5. OSClLLATOR FREQUENCY vs SUPPLY VOLTAGE
FIGURE 6. FREQUENCY OF OSCILLATION AS A FUNCTION
OF EXTERNAL OSCILLATOR CAPACITANCE
NOTE: All typical values have been characterized but are not tested.
O
U
T
P
UT
RE
S
I
S
T
ANCE
(
)
190
170
150
130
110
90
70
50
30
0
2
4
6
8
10
12
14
16
18
20
V+ (V)
LV = GND
LV = OPEN
I
L
= 20mA
T
A
= 25
o
C
C
OSC
= 0pF
V+ (V)
0
2
4
6
8
10
12
14
16
18
20
190
170
150
130
110
90
70
50
30
O
U
T
P
UT
RE
S
I
S
T
ANCE
(
)
I
L
= 3mA
T
A
= 25
o
C
C
OSC
= 0pF
LV = GND
LV = OPEN
TEMPERATURE (
o
C)
-55
-20
0
25
70
125
180
170
160
150
140
130
120
110
100
90
80
70
60
50
O
U
T
P
UT
RE
S
I
S
T
ANCE
(
)
V+ = 5V
I
L
= 3mA
V+ = 15V
I
L
= 20mA
P
O
W
E
R CO
NV
E
R
S
I
O
N
E
F
F
I
CIE
NCY
(
%
)
O
U
T
P
UT
RE
S
I
S
T
ANCE
(
)
F
OSC
(Hz)
100
95
90
85
80
75
70
65
350
300
250
200
150
100
50
100
1K
10K
100K
V+ = 5V
I
L
= 3mA
T
A
= 25
o
C
P
EFF
R
O
11
10
9
8
7
6
5
4
3
2
O
S
CIL
L
AT
O
R
F
R
E
Q
UE
NCY
(
k
Hz
)
0
2
4
6
8
10
12
14
16
18
20
SUPPLY VOLTAGE (V)
LV = GND
LV = OPEN
R
L
=
T
A
= 25
o
C
C
OSC
= 0pF
C
OSC
(pF)
O
S
CIL
L
AT
O
R
F
R
E
Q
UE
NCY
(
H
z
)
10K
1K
100
10
1
10
100
1000
10K
V+ = 15V
T
A
= 25
o
C
R
L
=
ICL7662
5
FIGURE 7. UNLOADED OSClLLATOR FREQUENCY
AS A FUNCTION OF TEMPERATURE
FIGURE 8. OUTPUT VOLTAGE AS A FUNCTION
OF LOAD CURRENT
FIGURE 9. OUTPUT VOLTAGE AS A FUNCTION
OF LOAD CURRENT
FIGURE 10. SUPPLY CURRENT AND POWER CONVERSION
EFFICIENCY AS A FUNCTION OF LOAD
FIGURE 11. SUPPLY CURRENT AND POWER CONVERSION
EFFICIENCY AS A FUNCTION OF LOAD
CURRENT
FIGURE 12. FREQUENCY OF OSCILLATION AS A
FUNCTION OF SUPPLY VOLTAGE
Typical Performance Curves
(See Figure 14, Test Circuit) (Continued)
TEMPERATURE (
o
C)
15K
14K
13K
12K
11K
10K
9K
8K
7K
6K
5K
O
S
CIL
L
A
T
O
R F
R
E
Q
UE
NCY
(
H
z
)
-55
-20
0
25
70
125
V+ = 15V
C
OSC
= 0pF
O
U
TP
U
T
V
O
LTA
G
E
V
O
(V
)
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
-13
-14
-15
10
20
30
40
50
60
70
80
90
100
LOAD CURRENT I
L
(mA)
SLOPE = 65
V+ = 15V
T
A
= 25
o
C
LV = OPEN
2
1
0
-1
-2
-3
-4
-5
0
2
4
6
8
10
12
14
16
18
20
LOAD CURRENT I
L
(mA)
O
U
TP
U
T
V
O
LTA
G
E
V
O
(V
)
V+ = 5V
T
A
= 25
o
C
LV = GND
SLOPE = 14
100
95
90
85
80
75
70
65
P
O
W
E
R CO
NV
E
R
S
I
O
N
E
F
F
I
CIE
NCY
(
%
)
40
32
24
16
8
S
U
P
P
L
Y
CURRE
NT
I+ (
m
A)
0
2
4
6
8
10
12
14
16
18
20
LOAD CURRENT I
L
(mA)
V+ = 5V
T
A
= 25
o
C
PBFF
I+
P
O
W
E
R CO
NV
E
R
S
I
O
N
E
F
F
I
CIE
NCY
(
%
) 100
95
90
85
80
75
70
65
0
10
20
30
40
50
60
70
80
90
100
200
160
120
80
40
S
U
P
P
L
Y
CURRE
NT
I+ (
m
A
)
V+ = 15V
T
A
= 25
o
C
PBFF
I+
LOAD CURRENT I
L
(mA)
11
10
9
8
7
6
5
4
3
2
O
S
CIL
L
AT
O
R
F
R
E
Q
UE
NCY
(
k
Hz
)
0
2
4
6
8
10
12
14
16
18
20
SUPPLY VOLTAGE (V)
LV = GND
LV = OPEN
R
L
=
T
A
= 25
o
C
C
OSC
= 0pF
ICL7662
6
Circuit Description
The ICL7662 contains all the necessary circuitry to complete
a negative voltage converter, with the exception of 2 external
capacitors which may be inexpensive 10
F polarized
electrolytic capacitors. The mode of operation of the device
may be best understood by considering Figure 15, which
shows an idealized negative voltage converter. Capacitor C
1
is charged to a voltage, V+, for the half cycle when switches
S
1
and S
3
are closed. (Note: Switches S
2
and S
4
are open
during this half cycle.) During the second half cycle of
operation, switches S
2
and S
4
are closed, with S
1
and S
3
open, thereby shifting capacitor C
1
negatively by V+ volts.
Charge is then transferred from C
1
to C
2
such that the
voltage on C
2
is exactly V+, assuming ideal switches and no
load on C
2
. The lCL7662 approaches this ideal situation
more closely than existing non-mechanical circuits.
In the lCL7662, the 4 switches of Figure 15 are MOS power
switches; S
1
is a P-Channel device and S
2
, S
3
and S
4
are
N-Channel devices. The main difficulty with this approach is
that in integrating the switches, the substrates of S
3
and S
4
must always remain reverse biased with respect to their
sources, but not so much as to degrade their "ON"
resistances. In addition, at circuit startup, and under output
short circuit conditions (V
OUT
= V+), the output voltage must
be sensed and the substrate bias adjusted accordingly.
Failure to accomplish this would result in high power losses
and probable device latchup.
This problem is eliminated in the ICL7662 by a logic network
which senses the output voltage (V
OUT
) together with the
level translators, and switches the substrates of S
3
and S
4
to
the correct level to maintain necessary reverse bias.
The voltage regulator portion of the ICL7662 is an integral part
of the anti-latchup circuitry, however its inherent voltage drop
can degrade operation at low voltages. Therefore, to improve
low voltage operation the "LV" pin should be connected to
GROUND, disabling the regulator. For supply voltages
greater than 10V the LV terminal must be left open to insure
latchup proof operation, and prevent device damage.
FIGURE 13. SUPPLY CURRENT AS A FUNCTION OF
OSCILLATOR FREQUENCY
NOTE:
5. These curves include in the supply current that current fed directly into the load R
L
from the V+ (See Figure 14). Thus, approximately half the
supply current goes directly to the positive side of the load, and the other half, through the ICL7662, to the negative side of the load. Ideally,
V
OUT
2V
IN
, I
S
2I
L
, so V
IN
x I
S
V
OUT
x I
L
.
Typical Performance Curves
(See Figure 14, Test Circuit) (Continued)
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
S
U
P
P
L
Y
CURRE
NT
I+ (
A)
10
100
1K
10K
OSCILLATOR FREQUENCY (Hz)
1
2
3
4
8
7
6
5
+
-
C
1
(+5V)
I
L
R
L
-V
OUT
C
2
10
F
ICL7662
C
OSC
+
-
I
S
V+
(NOTE)
NOTE: For large value of C
OSC
(> 1000pF) the values of C
1
and C
2
should be increased to 100
F.
FIGURE 14. ICL7662 TEST CIRCUIT
ICL7662
7
Theoretical Power Efficiency
Considerations
In theory a voltage multiplier can approach 100% efficiency if
certain conditions are met:
1. The drive circuitry consumes minimal power.
2. The output switches have extremely low ON resistance
and virtually no offset.
3. The impedances of the pump and reservoir capacitors are
negligible at the pump frequency.
The ICL7662 approaches these conditions for negative
voltage multiplication if large values of C
1
and C
2
are used.
ENERGY IS LOST ONLY IN THE TRANSFER OF
CHARGE BETWEEN CAPACITORS IF A CHANGE IN
VOLTAGE OCCURS. The energy lost is defined by:
E = 1/2C
1
(V
1
2
- V
2
2
)
where V
1
and V
2
are the voltages on C
1
during the pump
and transfer cycles. If the impedances of C
1
and C
2
are
relatively high at the pump frequency (refer to Figure 15)
compared to the value of R
L
, there will be a substantial
difference in the voltages V
1
and V
2
. Therefore it is not only
desirable to make C
2
as large as possible to eliminate output
voltage ripple, but also to employ a correspondingly large
value for C
1
in order to achieve maximum efficiency of
operation.
Do's and Don'ts
1. Do not exceed maximum supply voltages.
2. Do not connect LV terminal to GROUND for supply volt-
ages greater than 10V.
3. When using polarized capacitors, the + terminal of C
1
must be connected to pin 2 of the ICL7662 and the + ter-
minal of C
2
must be connected to GROUND.
4. If the voltage supply driving the 7662 has a large source
impedance (25
- 30
), then a 2.2
F capacitor from pin
8 to ground may be required to limit rate of rise of input
voltage to less than 2V/
s.
5. User should insure that the output (pin 5) does not go
more positive than GND (pin 3). Device latch up will occur
under these conditions.
A 1N914 or similar diode placed in parallel with C
2
will
prevent the device from latching up under these conditions.
(Anode pin 5, Cathode pin 3).
Typical Applications
Simple Negative Voltage Converter
The majority of applications will undoubtedly utilize the
ICL7662 for generation of negative supply voltages. Figure
16 shows typical connections to provide a negative supply
where a positive supply of +4.5V to 20.0V is available. Keep
in mind that pin 6 (LV) is tied to the supply negative (GND)
for supply voltages below 10V.
The output characteristics of the circuit in Figure 16A can be
approximated by an ideal voltage source in series with a
resistance as shown in Figure 16B. The voltage source has
a value of -(V+). The output impedance (R
O
) is a function of
the ON resistance of the internal MOS switches (shown in
Figure 2), the switching frequency, the value of C
1
and C
2
,
and the ESR (equivalent series resistance) of C
1
and C
2
. A
good first order approximation for R
O
is:
Combining the four R
SWX
terms as R
SW
, we see that
R
SW
, the total switch resistance, is a function of supply
voltage and temperature (See the Output Source Resistance
graphs), typically 24
at +25
o
C and 15V, and 53
at +25
o
C
and 5V. Careful selection of C
1
and C
2
will reduce the
remaining terms, minimizing the output impedance. High
value capacitors will reduce the 1/(f
PUMP
x C
1
) component,
and low FSR capacitors will lower the ESR term. Increasing
the oscillator frequency will reduce the 1/(f
PUMP
x C
1
) term,
but may have the side effect of a net increase in output
impedance when C
1
> 10
F and there is no longer enough
time to fully charge the capacitors every cycle. In a typical
application where f
OSC
= 10kHz and C = C
1
= C
2
= 10
F:
Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5, a high value could
potentially swamp out a low 1/(f
PUMP
x C
1
) term, rendering
an increase in switching frequency or filter capacitance
ineffective. Typical electrolytic capacitors may have ESRs as
high as 10
.
V
OUT
= -V
IN
C
2
V
IN
C
1
S
3
S
4
S
1
S
2
8
2
4
5
3
3
7
FIGURE 15. IDEALIZED NEGATIVE CONVERTER
R
O
2(R
SW1
+ R
SW3
+ ESRC
1
)
+ 2(R
SW2
+ R
SW4
+ ESRC
1
) +
1
+ ESRC
2
f
PUMP
x C
1
(f
PUMP
=
f
OSC
,
R
SWX
= MOSFET switch resistance)
2
R
O
2 x R
SW
+
1
+ 4 x ESRC
1
+ ESRC
2
f
PUMP
x C
1
R
O
2 x 23 +
1
+ 4 ESRC
1
+ ESRC
2
(5 x 10
3
x 10 x 10
-6
)
R
O
46 + 20 + 5 x ESR
C
ICL7662
8
Output Ripple
ESR also affects the ripple voltage seen at the output. The
total ripple is determined by 2V, A and B, as shown in Figure
16. Segment A is the voltage drop across the ESR of C
2
at
the instant it goes from being charged by C
1
(current flowing
into C
2
) to being discharged through the load (current
flowing out of C
2
). The magnitude of this current change is 2
x I
OUT
, hence the total drop is 2 x I
OUT
x ESRC
2
V.
Segment B is the voltage change across C
2
during time t
2
,
the half of the cycle when C
2
supplies current the load. The
drop at B is I
OUT
x t
2
/C
2
V. The peak-to-peak ripple voltage
is the sum of these voltage drops:
Again, a low ESR capacitor will result in a higher
performance output.
Paralleling Devices
Any number of ICL7662 voltage converters may be
paralleled (Figure 18) to reduce output resistance. The
reservoir capacitor, C
2
, serves all devices while each device
requires its own pump capacitor, C
1
. The resultant output
resistance would be approximately:
Cascading Devices
The ICL7662 may be cascaded as shown in Figure 19 to
produce larger negative multiplication of the initial supply
voltage. However, due to the finite efficiency of each device,
the practical limit is 10 devices for light loads. The output
voltage is defined by:
V
OUT
= -n(V
IN
),
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be
approximately the weighted sum of the individual ICL7662
R
OUT
values.
1
2
3
4
8
7
6
5
+
-
10
F
10
F
ICL7662
V
OUT
= -V+ V+
+
-
R
O
V
OUT
V+
+
-
16A.
16B.
C
1
C
2
FIGURE 16. SIMPLE NEGATIVE CONVERTER AND ITS
OUTPUT EQUIVALENT
V
RIPPLE
1
2 f
PUMP
C
2
-----------------------------------------
2 ESRC
2
I
OUT
+
R
OUT
=
R
OUT
(of ICL7662)
n (number of devices)
FIGURE 17. OUTPUT RIPPLE
FIGURE 18. PARALLELING DEVICES
A
t
2
t
1
B
0
-(V+)
V
1
2
3
4
8
7
6
5
ICL7662
V+
C
1
"1"
1
2
3
4
8
7
6
5
ICL7662
C
1
"N"
R
L
C
2
+
-
ICL7662
9
Changing the ICL7662 Oscillator Frequency
It may be desirable in some applications, due to noise or other
considerations, to increase the oscillator frequency. This is
achieved by overdriving the oscillator from an external clock, as
shown in Figure 20. In order to prevent possible device latchup,
a 1k
resistor must be used in series with the clock output. In
the situation where the designer has generated the external
clock frequency using TTL logic, the addition of a 10k
pullup
resistor to V+ supply is required. Note that the pump frequency
with external clocking, as with internal clocking, will be 1/2 of
the clock frequency. Output transitions occur on the positive-
going edge of the clock.
It is also possible to increase the conversion efficiency of the
ICL7662 at low load levels by lowering the oscillator frequency.
This reduces the switching losses, and is achieved by
connecting an additional capacitor, COSC, as shown in Figure
21. However, lowering the oscillator frequency will cause an
undesirable increase in the impedance of the pump (C
1
) and
reservoir (C
2
) capacitors; this is overcome by increasing the
values of C
1
and C
2
by the same factor that the frequency has
been reduced. For example, the addition of a 100pF capacitor
between pin 7 (OSC) and V+ will lower the oscillator frequency
to 1kHz from its nominal frequency of 10kHz (a multiple of 10),
and thereby necessitate a corresponding increase in the value
of C
1
and C
2
(from 10mF to 100mF).
Positive Voltage Doubling
The ICL7662 may be employed to achieve positive voltage
doubling using the circuit shown in Figure 22. In this
application, the pump inverter switches of the ICL7662 are
used to charge C
1
to a voltage level of V+ -V
F
(where V+ is
the supply voltage and V
F
is the forward voltage drop of
diode D
1
). On the transfer cycle, the voltage on C
1
plus the
supply voltage (V+) is applied through diode C
2
to capacitor
C
2
. The voltage thus created on C
2
becomes (2V+) (2V
F
) or
twice the supply voltage minus the combined forward
voltage drops of diodes D
1
and D
2
.
The source impedance of the output (V
OUT
) will depend on
the output current, but for V+ = 15V and an output current of
10mA it will be approximately 70
.
FIGURE 19. CASCADING DEVICES FOR INCREASED OUTPUT VOLTAGE
1
2
3
4
8
7
6
5
ICL7662
V+
"1"
1
2
3
4
8
7
6
5
ICL7662
"N"
10
F
+
-
10
F
-
+
V
OUT
-
+
10
F
10
F
-
+
1
2
3
4
8
7
6
5
+
-
10
F
ICL7662
V
OUT
V
+
+
-
10
F
V
+
CMOS
GATE
1k
FIGURE 20. EXTERNAL CLOCKING
1
2
3
4
8
7
6
5
+
-
ICL7662
V
OUT
V
+
+
-
C
2
C
1
C
OSC
FIGURE 21. LOWERING OSCILLATOR FREQUENCY
1
2
3
4
8
7
6
5
ICL7662
V+
D
2
C
1
C
2
V
OUT
=
(2V+) - (2V
F
)
+
-
+
-
D
1
NOTE: D
1
and D
2
can be any suitable diode.
FIGURE 22. POSITIVE VOLTAGE DOUBLER
ICL7662
10
Combined Negative Voltage Conversion and Posi-
tive Supply Doubling
Figure 23 combines the functions shown in Figure 16 and
Figure 22 to provide negative voltage conversion and
positive voltage doubling simultaneously. This approach
would be, for example, suitable for generating +9V and -5V
from an existing +5V supply. In this instance capacitors C
1
and C
3
perform the pump and reservoir functions
respectively for the generation of the negative voltage, while
capacitors C
2
and C
4
are pump and reservoir respectively
for the doubled positive voltage. There is a penalty in this
configuration which combines both functions, however, in
that the source impedances of the generated supplies will be
somewhat higher due to the finite impedance of the common
charge pump driver at pin 2 of the device.
Voltage Splitting
The bidirectional characteristics can also be used to split a
higher supply in half, as shown in Figure 24. The combined
load will be evenly shared between the two sides and, a high
value resistor to the LV pin ensures start-up. Because the
switches share the load in parallel, the output impedance is
much lower than in the standard circuits, and higher currents
can be drawn from the device. By using this circuit, and then
the circuit of Figure 19, +30V can be converted (via +15V,
and -15V) to a nominal -30V, although with rather high series
output resistance (~250
).
Regulated Negative Voltage Supply
In some cases, the output impedance of the ICL7662 can be a
problem, particularly if the load current varies substantially. The
circuit of Figure 25 can be used to overcome this by controlling
the input voltage, via an ICL7611 low-power CMOS op amp, in
such a way as to maintain a nearly constant output voltage.
Direct feedback is inadvisable, since the ICL7662s output does
not respond instantaneously to a change in input, but only after
the switching delay. The circuit shown supplies enough delay to
accommodate the ICL7662, while maintaining adequate
feedback. An increase in pump and storage capacitors is
desirable, and the values shown provides an output impedance
of less than 5
to a load of 10mA.
Other Applications
Further information on the operation and use of the ICL7662
may be found in AN051 "Principles and Applications of the
ICL7660 CMOS Voltage Converter".
1
2
3
4
8
7
6
5
ICL7662
V+
D
1
D
2
C
4
V
OUT
= (2V+) -
(V
FD1
) - (V
FD2
)
+
-
C
2
+
-
C
3
+
-
V
OUT
=
- (nV
IN
- V
FDX
)
C
1
+
-
FIGURE 23. COMBINED NEGATIVE CONVERTER
AND POSITIVE DOUBLER
1
2
3
4
8
7
6
5
+
-
+
-
50
F
50
F
+
-
50
F
R
L1
V
OUT
=
V+ - V-
2
ICL7662
V+
V-
R
L2
FIGURE 24. SPLITTING A SUPPLY IN HALF
1
2
3
4
8
7
6
5
+
-
100
F
ICL7662
100
F
V
OUT
+
-
10
F
ICL7611
+
-
100
50K
+8V
100K
50K
ICL8069
56K
+8V
800K
250K
VOLTAGE
ADJUST
+
-
FIGURE 25. REGULATING THE OUTPUT VOLTAGE
ICL7662
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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