1
File Number
2865.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
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Copyright
Intersil Corporation 1999
ICL8048
Log Amplifier
The ICL8048 is a monolithic logarithmic amplifier capable of
handling six decades of current input, or three decades of
voltage input. It is fully temperature compensated and is
nominally designed to provide 1V of output for each decade
change of input. For increased flexibility, the scale factor,
reference current and offset voltage are externally
adjustable.
Pinout
ICL8048
(CERDIP)
TOP VIEW
Features
Full Scale Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . 0.5%
Temperature Compensated Operation . . . . . . 0
o
C to 70
o
C
Scale Factor, Adjustable . . . . . . . . . . . . . . . . . 1V/Decade
Dynamic Current Range. . . . . . . . . . . . . . . . . . . . . 120dB
Dynamic Voltage Range . . . . . . . . . . . . . . . . . . . . . . 60dB
Dual JFET Input Op Amps
Functional Diagram
ICL8048
Ordering Information
PART
NUMBER
ERROR
(25
o
C)
TEMPERATURE
RANGE (
o
C)
PACKAGE
PKG.
NO.
ICL8048BCJE
30mV
0 to 70
16 Ld CERDIP F16.3
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
GND
I
IN
NC
V-
NC
A
1
OUTPUT
I
REF
NC
A
2
OFFSET
V+
V
OUT
NC
GAIN
NULL
A
2
OFFSET
NULL
A
1
OFFSET
NULL
A
1
OFFSET
NULL
V
REF
I
REF
16
7
15
2
V
IN
GND
A
1
OUTPUT
GAIN
Q
2
A
1
+
-
A
2
+
-
Q
1
1
f
IN
V
OUT
10
Data Sheet
August 1999
2
Absolute Maximum Ratings
Thermal Information
Supply Voltage
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18V
I
IN
(Input Current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2mA
I
REF
(Reference Current). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2mA
Voltage Between Offset Null and V+ . . . . . . . . . . . . . . . . . . . .
0.5V
Output Short Circuit Duration. . . . . . . . . . . . . . . . . . . . . . . Indefinite
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to 70
o
C
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
JC
(
o
C/W)
CERDIP Package . . . . . . . . . . . . . . . . .
75
22
Maximum Junction Temperature (Hermetic Package or Die) . . .175
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
Die Characteristics
Number of Transistors or Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
V
S
=
15V, T
A
= 25
o
C, I
REF
= 1mA, Scale Factor Adjusted for 1V/Decade, Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
ICL4048BC
UNITS
MIN
TYP
MAX
Dynamic Range
I
IN
(1nA - 1mA)
R
IN
= 10k
120
-
-
dB
V
IN
(10mV - 10V)
60
-
-
dB
Error, % of Full Scale
I
IN
= 1nA to 1mA
-
0.20
0.5
%
T
A
= 0
o
C to 70
o
C,
I
IN
= 1nA to 1mA
-
0.60
1.25
%
Error, Absolute Value
I
IN
= 1nA to 1mA
-
12
30
mV
T
A
= 0
o
C to 70
o
C,
I
IN
= 1nA to 1mA
-
36
75
mV
Temperature Coefficient of V
OUT
I
IN
= 1nA to 1mA
-
0.8
-
mV/
o
C
Power Supply Rejection Ratio
Referred to Output
-
2.5
-
mV/V
Offset Voltage (A
1
and A
2
)
Before Nulling
-
15
25
mV
Wideband Noise
At Output, for I
IN
= 100
A
-
250
-
V
RMS
Output Voltage Swing
R
L
= 10k
12
14
-
V
R
L
= 2k
10
13
-
V
Power Consumption
-
150
200
mW
Supply Current
-
5
6.7
mA
Typical Performance Curves
FIGURE 1. TRANSFER FUNCTION FOR VOLTAGE INPUTS
FIGURE 2. TRANSFER FUNCTION FOR CURRENT INPUTS
INPUT VOLTAGE (V)
OUTPUT V
O
L
T
A
GE (V)
+4
+3
+2
+1
0
-1
-2
-3
-4
1mV
10mV
100mV
1V
10V
I
REF
= 100nA
I
REF
= 10
A
I
REF
= 1mA
R
IN
= 10k
INPUT CURRENT (A)
OUTPUT V
O
L
T
A
GE (V)
+8
+6
+4
+2
0
-2
-4
-6
-8
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
10
-3
I
REF
= 1nA
I
REF
= 1
A
I
REF
= 1mA
ICL8048
3
ICL8048 Detailed Description
The ICL8048 relies for its operation on the well known
exponential relationship between the collector current and
the base emitter voltage of a transistor:
For base emitter voltages greater than 100mV, Equation 1
becomes
From Equation 2, it can be shown that for two identical
transistors operating at different collector currents, the V
BE
difference (
V
BE
) is given by:
Referring to Figure 7 it is clear that the potential at the
collector of Q
2
is equal to the
V
BE
between Q
1
and Q
2
. The
output voltage is
V
BE
multiplied by the gain of A
2
:
The expression
has a numerical value of 59mV at
25
o
C; thus in order to generate 1V/decade at the output, the
ratio (R
1
+ R
2
)/R
2
is chosen to be 16.9. For this scale factor
to hold constant as a function of temperature, the
(R
1
+ R
2
)/R
2
term must have a 1/T characteristic to
compensate for kT/q.
In the ICL8048 this is achieved by making R
1
a thin film
resistor, deposited on the monolithic chip. It has a nominal
value of 15.9k
at 25
o
C, and its temperature coefficient is
FIGURE 3. SMALL SIGNAL BANDWIDTH vs INPUT
CURRENT
FIGURE 4. MAXIMUM ERROR VOLTAGE AT THE OUTPUT vs
INPUT CURRENT
FIGURE 5. MAXIMUM ERROR VOLTAGE AT THE OUTPUT vs
INPUT VOLTAGE
FIGURE 6. SMALL SIGNAL VOLTAGE GAIN vs INPUT
VOLTAGE FOR R
S
= 10k
Typical Performance Curves
(Continued)
INPUT CURRENT (A)
SMALL SIGNAL B
AND
WIDTH (Hz)
100K
10K
1K
100
10
10
-11
10
-9
10
-7
10
-5
10
-3
I
REF
= 1mA
INPUT CURRENT (A)
MAXIMUM ERR
OR V
O
L
T
A
GE (
mV)
200
175
150
125
100
75
50
25
0
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
10
-3
8048BC (0
o
C TO 70
o
C)
8048BC (25
o
C)
MAXIMUM ERR
OR V
O
L
T
A
GE (
mV)
200
175
150
125
100
75
50
25
0
8048BC (0
o
C TO 70
o
C)
8048BC (25
o
C)
INPUT VOLTAGE (V)
10mV
100mV
1V
10V
R
IN
= 10k
INPUT VOLTAGE (V)
1mV
10mV
100mV
1V
10V
V
O
L
T
A
GE GAIN
0.01
0.1
1
10
100
434
1000
4343
V
IN
=
V
/
V
V
OUT
log
10
e
V
IN
=
VOLTAGE GAIN =
R
IN
= 10k
V
IN
I
C
I
S
exp
qV
B
E
kT
---------------
1
=
(EQ. 1)
I
C
I
S
exp
qV
BE
kT
----------------
=
(EQ. 2)
V
BE
-2.303
kT
q
-------
log
10
I
C1
I
C2
---------
=
(EQ. 3)
V
OUT
-2.303
R
1
R
2
+
R
2
----------------------
kT
q
-------
log
10
I
IN
I
REF
--------------
=
(EQ. 4)
2.303
kT
q
-------
ICL8048
4
carefully designed to provide the necessary compensation.
Resistor R
2
is external and should be a low T.C. type; it
should have a nominal value of 1k
to provide 1V/decade,
and must have an adjustment range of
20% to allow for
production variations in the absolute value of R
1
.
ICL8048 Offset and Scale Factor
Adjustment
A log amp, unlike an op amp, cannot be offset adjusted by
simply grounding the input. This is because the log of zero
approaches minus infinity; reducing the input current to zero
starves Q
1
of collector current and opens the feedback loop
around A
1
. Instead, it is necessary to zero the offset voltage
of A
1
and A
2
separately, and then to adjust the scale factor.
Referring to Figure 7, this is done as follows:
1. Temporarily connect a 10k
resistor (R
0
) between pins 2
and 7. With no input voltage, adjust R
4
until the output of
A
1
(pin 7) is zero. Remove R
0
.
Note that for a current input, this adjustment is not neces-
sary since the offset voltage of A
1
does not cause any er-
ror for current source inputs.
2. Set I
IN
= I
REF
= 1mA. Adjust R
5
such that the output of A
2
(pin 10) is zero.
3. Set I
IN
= 1
A, I
REF
= 1mA. Adjust R
2
for V
OUT
= 3V (for
a 1V/decade scale factor) or 6V (for a 2V/decade scale
factor).
Step #3 determines the scale factor. Setting I
IN
= 1
A
optimizes the scale factor adjustment over a fairly wide dynamic
range, from 1mA to 1nA. Clearly, if the ICL8048 is to be used
for inputs which only span the range 100
A to 1mA, it would be
better to set I
IN
= 100
A in Step #3. Similarly, adjustment for
other scale factors would require different I
IN
and V
OUT
values.
Applications Information
ICL8048 Scale Factor Adjustment
The scale factor adjustment procedures outlined previously
for the ICL8048, are primarily directed towards setting up 1V
(
V
OUT
) per decade (
I
IN
or
V
IN
) for the log amp, or one
decade (
V
OUT
) per volt (
V
IN
) for the antilog amp.
This corresponds to K = 1 in the respective transfer functions:
By adjusting R
2
(Figure 7) the scale factor "K" in Equation 5
can be varied. The effect of changing K is shown graphically
in Figure 8 for the log amp. The nominal value of R
2
required
to give a specific value of K can be determined from
Equation 6. It should be remembered that R
1
has a
20%
tolerance in absolute value, so that allowance shall be made
for adjusting the nominal value of R
2
by
20%.
ICL8048 Automatic Offset Nulling Circuit
The ICL8048 is fundamentally a logarithmic current
amplifier. It can be made to act as a voltage amplifier by
placing a resistor between the current input and the voltage
source but, since I
IN
= (V
IN
- V
OFFSET
)/R
IN
, this conversion
is accurate only when V
IN
is much greater than the offset
voltage. A substantial reduction of V
OFFSET
would allow
voltage operation over a 120dB range.
I
IN
R
IN
A
1
+
-
R
4
2k
V+
5
4
A
2
+
-
R
5
2k
V+
GND
1
2
C
1
Q
1
Q
2
R
3
7
R
2
R
1
1k
15.9k
GAIN
A
1
OUTPUT
R
0
10k
680
(LOW T.C.)
150pF
R
REF
I
REF
V
REF
(+15V)
16
10
V
OUT
15
V
IN
FIGURE 7. ICL8048 OFFSET AND SCALE FACTOR ADJUSTMENT
V
OUT
-K log
10
I
IN
I
REF
--------------
=
(EQ. 5)
R
2
941
K
0.059
(
)
-----------------------------
=
(EQ. 6)
INPUT CURRENT (A)
0
-2
10
I
REF
= 1mA
OUTPUT V
O
L
T
A
GE (V)
12
K = 2
K = 1
K = 0.5
8
6
4
2
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
10
-3
FIGURE 8. EFFECT OF VARYING "K" ON THE LOG AMPLIFIER
ICL8048
5
Figure 9 shows the ICL8048 in an automatic offset nulling
configuration using the ICL7650S. The extremely low offset
voltage of the ICL7650S forces its non-inverting input (and thus
pin 2 of the ICL8048) to the same potential as its inverting input
by nulling the first stage of the log amp. Since V
OFFSET
is now
within a few
V of ground potential, R
IN
can perform its voltage
to current conversion much more accurately, and without an
offset trimmer pot. Step 1 of the offset and scale factor
adjustment is eliminated, simplifying calibration.
NOTE: The ICL7650S op amp has a maximum supply voltage of
18V. The ICL8048 will operate at this voltage, but I
REF
must be
limited to 200
A or less for proper calibration and operation. Best
performance will be achieved when the ICL7650S has a
3V to
8V
supply and the ICL8048 is at its recommended
15V supply. See
A053 for a method of powering the ICL7650S from a
15V source.
Frequency Compensation
Although the op amps in the ICL8048 are compensated for
unity gain, some additional frequency compensation is
required. This is because the log transistors in the feedback
loop add to the loop gain. In the ICL8048, 150pF should be
connected between Pins 2 and 7 (Figure 7).
Error Analysis
Performing a meaningful error analysis of a circuit containing a
log and antilog amplifiers is more complex than dealing with a
similar circuit involving only op amps. In this data sheet every
effort has been made to simplify the analysis task, without in
any way compromising the validity of the resultant numbers.
The key difference in making error calculations in log/antilog
amps, compared with op amps, is that the gain of the former
is a function of the input signal level. Thus, it is necessary,
when referring errors from output to input, or vice versa, to
check the input voltage level, then determine the gain of the
circuit by referring to the graphs given in the Typical
Performance Curves section.
The various error terms in the log amplifier, the ICL8048, are
Referred To the Output (RTO) of the device. The errors are
expressed in this way because in the majority of systems a
number of log amps interface with an antilog amp, as shown
in Figure 10.
It is very straightforward to estimate the system error at node
(A) by taking the square root of the sum-of-the-squares of
the errors of each contributing block.
If required, this error can be referred to the system output
through the voltage gain of the antilog circuit, using the
voltage gain versus input voltage plot.
The numerical values of x, y, and z in the above equation are
obtained from the maximum error voltage plots. For
example, with the ICL8048BC, the maximum error at the
output is 30mV at 25
o
C. This means that the measured
output will be within 30mV of the theoretical transfer
function, provided the unit has been adjusted per the
procedures described previously. Figure 11 illustrates this
point.
ICL7650
+
-
+
-
A
1
+
-
A
2
I
REF
I
IN
R
IN
V
IN
V
OUT
ICL8048
Q
1
Q
2
V
OFFSET
0.1
F
0.1
F
0.1
F
33k
33k
0V
1K
4
5
2
1
16
10
7
15
V
REF
(+15V)
R
REF
R
3
A
1
OUTPUT
R
5
2k
R
1
15.9k
R
2
680
(LOW T.C.) 1k
C
1
150pF
GAIN
V+
FIGURE 9. ICL8048 OFFSET NULLED BY ICL7650
12
13
A
INPUT
INPUT
ERROR DUE TO B (RTO)
= ymV
ERROR DUE TO C (RTI)
= zmV
ERROR DUE TO A (RTO)
= xmV
ANTI LOG
AMP
C
LOG AMP
A
LOG AMP
B
OUTPUT
FIGURE 10.
Total Error
x
2
y
2
z
2
+
+
at (A)
=
ICL8048
6
To determine the maximum error over the operating
temperature range, the 0
o
C to 70
o
C absolute error values
given in the table of electrical specifications should be used.
For intermediate temperatures, assume a linear increase in
the error between the 25
o
C value and the 70
o
C value.
It is important to note that the ICL8048 requires positive
values of I
REF
, and the input current must also be positive.
Application of negative I
IN
to the ICL8048 or negative I
REF
will cause malfunction, and if maintained for long periods,
would lead to device degradation. Some protection can be
provided by placing a diode between pin 7 and ground.
Setting Up the Reference Current
The input current reference pin (I
REF
) is not a true virtual
ground. For the ICL8048, a fraction of the output voltage is
seen on Pin 16 (Figure 7). This does not constitute an
appreciable error provided V
REF
is much greater than this
voltage. A 10V or 15V reference satisfies this condition.
Alternatively, I
REF
can be provided from a true current
source. One method of implementing such a current source
is shown in Figure 12.
Log of Ratio Circuit, Division
The ICL8048 may be used to generate the log of a ratio by
modulating the I
REF
input. The transfer function remains the
same, as defined by Equation 7:
Clearly it is possible to perform division using just one
ICL8048, followed by an antilog amplifier. For multiplication,
it is generally necessary to use two log amps, summing their
outputs into an antilog amp.
To avoid the problems caused by the I
REF
input not being a
true virtual ground (discussed in the previous section), the
circuit of Figure 12 is again recommended if the I
REF
input is
to be modulated.
Definition of Terms
In the definitions which follow, it will be noted that the various
error terms are referred to the output of the log amp, and to
the input of the antilog amp. The reason for this is explained
on the previous page.
Dynamic Range. The dynamic range of the ICL8048 refers
to the range of input voltages or currents over which the
device is guaranteed to operate.
Error, Absolute Value. The absolute error is a measure of
the deviation from the theoretical transfer function, after
performing the offset and scale factor adjustments as
outlined, (ICL8048). It is expressed in mV and referred to the
linear axis of the transfer function plot. Thus, in the case of
the ICL8048, it is a measure of the deviation from the
theoretical output voltage for a given input current or voltage.
The absolute error specification is guaranteed over the
dynamic range.
Error, % of Full Scale. The error as a percentage of full
scale can be obtained from the following relationship:
Temperature Coefficient of V
OUT
. For the ICL8048 the
temperature coefficient refers to the drift with temperature of
V
OUT
for a constant input current.
Power Supply Rejection Ratio. The ratio of the voltage
change in the linear axis of the transfer function (V
OUT
for
the ICL8048) to the change in the supply voltage, assuming
that the log axis is held constant.
Wideband Noise. For the ICL8048, this is the noise
occurring at the output under the specified conditions.
Scale Factor. For the log amp, the scale factor (K) is the
voltage change at the output for a decade (i.e., 10:1) change
at the input. See Equation 5.
Application Notes
For further applications assistance, see A007 "The
ICL8048/8049 Monolithic Log-Antilog Amplifiers".
INPUT CURRENT (A)
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
10
-3
-6
-8
-4
-2
0
2
4
6
8
OUTPUT V
O
L
T
A
GE (V)
I
REF
= 1nA
I
REF
= 1
A
I
REF
= 1mA
Actual output will lie
within shaded area for
ICL8048BC at 25
o
C
30mV
30mV
TRANSFER FN
THEORETICAL
FIGURE 11. TRANSFER FUNCTION FOR CURRENT INPUTS
+15V
+15V
+
-
741
2N2609
2N2219
10k
V
REF
I
REF
R
1
I
REF
= V
REF
/R
1
(TO PIN 16 ON ICL8048)
FIGURE 12.
V
OUT
Klog
10
I
IN
I
REF
--------------
=
(EQ. 7)
Error, % of Full Scale
100
Error, absolute value
Full Scale Output Voltage
-----------------------------------------------------------------------
=
ICL8048
7
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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P. O. Box 883, Mail Stop 53-204
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TEL: (321) 724-7000
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ICL8048
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer's identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
bbb
C A - B
S
c
Q
L
A
SEATING
BASE
D
PLANE
PLANE
-D-
-A-
-C-
-B-
D
E
S1
b2
b
A
e
M
c1
b1
(c)
(b)
SECTION A-A
BASE
LEAD FINISH
METAL
e
A/2
A
M
S
S
ccc
C A - B
M
D
S
S
aaa
C A - B
M
D
S
S
e
A
F16.3
MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
-
0.200
-
5.08
-
b
0.014
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.840
-
21.34
5
E
0.220
0.310
5.59
7.87
5
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
-
7
90
o
105
o
90
o
105
o
-
aaa
-
0.015
-
0.38
-
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
N
16
16
8
Rev. 0 4/94
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