1
November 16, 2004
ICM7211AM
4-Digit, LCD Display Driver
The ICM7211AM device is a non-multiplexed four-digit
seven-segment CMOS LCD display decoder-driver.
This device is configured to drive conventional LCD displays
by providing a complete RC oscillator, divider chain,
backplane driver, and 28 segment outputs.
It also has a microprocessor compatible input configuration,
which provides data input latches and Digit Address latches
under control of high-speed Chip Select inputs. These devices
simplify the task of implementing a cost-effective
alphanumeric seven-segment display for microprocessor
systems, without requiring extensive ROM or CPU time for
decoding and display updating.
The ICM7211AM provides the "Code B" output code, i.e.,
0-9, dash, E, H, L, P, blank, but will correctly decode true
BCD to seven-segment decimal outputs.
Features
Four Digit Non-Multiplexed 7 Segment LCD Display
Outputs with Backplane Driver
Complete Onboard RC Oscillator to Generate Backplane
Frequency
Backplane Input/Output Allows Simple Synchronization of
Slave-Devices to a Master
Provides Data and Digit Address Latches Controlled by
Chip Select Inputs to Provide a Direct High Speed
Processor Interface
Decodes Binary to Code B (0-9, Dash, E, H, L, P, Blank)
Ordering Information
PART NUMBER
DISPLAY
TYPE
DISPLAY
DECODING
INPUT
INTERFACING
DISPLAY DRIVE
TYPE
TEMP.
RANGE (C)
PACKAGE
PKG. DWG. #
ICM7211AMlPL
LCD
Code B
Microprocessor
Direct Drive
-40 to 85
40 Ld PDIP
E40.6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
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Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2001, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Data Sheet
FN3158.5
2
FN3158.5
November 16, 2004
Pinout
ICM7211AM (PDIP)
TOP VIEW
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
OSC
V
SS
CHIP SELECT 2
CHIP SELECT 1
DIGIT ADRESS BIT 2
DIGIT ADRESS BIT 1
B3
B2
B1
B0
DATA
INPUTS
V
DD
e
1
g
1
f
1
BP
a
2
b
2
c
2
d
2
e
2
g
2
f
2
a
3
b
3
c
3
d
3
e
3
g
3
f
3
a
4
d
1
c
1
b
1
a
1
f
4
g
4
e
4
d
4
c
4
b
4
Functional Block Diagram
ICM7211AM
7 WIDE DRIVER
7 WIDE LATCH EN
PROGRAMMABLE
4 TO 7 DECODER
7 WIDE DRIVER
7 WIDE LATCH EN
PROGRAMMABLE
4 TO 7 DECODER
7 WIDE DRIVER
7 WIDE LATCH EN
PROGRAMMABLE
4 TO 7 DECODER
7 WIDE DRIVER
7 WIDE LATCH EN
PROGRAMMABLE
4 TO 7 DECODER
D4
SEGMENT OUTPUTS
D3
SEGMENT OUTPUTS
D2
SEGMENT OUTPUTS
D1
SEGMENT OUTPUTS
2-BIT
DIGIT
ADRESS
INPUT
CHIP
CHIP
DATA
INPUTS
OSCILLATOR
INPUT
2 TO 4
DECODER
2-BIT
LATCH
ENABLE
4-BIT
LATCH
ENABLE
ONE
SHOT
SELECT 1
SELECT 2
BLACKPLANE
DRIVER
ENABLE
OSCILLATOR
19kHz
FREE-RUNNING
128
ENABLE
DIRECTOR
BP INPUT/OUTPUT
ICM7211AM
ICM7211AM
3
FN3158.5
November 16, 2004
Absolute Maximum Ratings
Thermal Information
Supply Voltage (V
DD
- V
SS
) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V
Input Voltage (Any Terminal) (Note 1) . . . V
SS
- 0.3V to V
DD
, + 0.3V
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to 85C
Thermal Resistance (Typical, Note 2)
JA
(C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150C
Maximum Storage Temperature Range . . . . . . . . .-65װC to 150C
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Due to the SCR structure inherent in the CMOS process, connecting any terminal to voltages greater than V
DD
or less than V
SS
may cause
destructive device latchup. For this reason, it is recommended that no inputs from external sources not operating on the same power supply be
applied to the device before its supply is established, and that in multiple supply systems, the supply to the ICM7211AM be turned on first.
2.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
CHARACTERISTICS V
DD
= 5V
10%, T
A
= 25C, V
SS
= 0V Unless Otherwise Specified
Operating Supply Voltage Range (V
DD
- V
SS
), V
SUPPLY
3
5
6
V
Operating Current, I
DD
Test circuit, Display blank
-
10
50
A
Oscillator Input Current, I
OSCI
Pin 36
-
2
10
A
Segment Rise/Fall Time, t
r
, t
f
C
L
= 200pF
-
0.5
-
s
Backplane Rise/Fall Time, t
r
, t
f
C
L
= 5000pF
-
1.5
-
s
Oscillator Frequency, f
OSC
Pin 36 Floating
-
19
-
kHz
Backplane Frequency, f
BP
Pin 36 Floating
-
150
-
Hz
INPUT CHARACTERISTICS
Logical "1" Input Voltage, V
IH
4
-
-
V
Logical "0" Input Voltage, V
IL
-
-
1
V
Input Leakage Current, I
ILK
Pins 27-34
-
0.01
1
A
Input Capacitance, C
lN
Pins 27-34
-
5
pF
BP/Brightness Input Leakage, I
BPLK
Measured at Pin 5 with Pin 36 at V
SS
-
0.01
1
A
BP/Brightness Input Capacitance, C
BPI
All Devices
-
200
-
pF
AC CHARACTERISTICS
Chip Select Active Pulse Width, t
WL
Other Chip Select Either Held Active, or
Both Driven Together
200
-
-
ns
Data Setup Time, t
DS
100
-
-
ns
Data Hold Time, t
DH
10
0
-
ns
Inter-Chip Select Time, t
ICS
2
-
-
s
Input Definitions
In this table, V
DD
and V
SS
are considered to be normal operating input logic levels. Actual input low and high levels are specified
under Operating Characteristics. For lowest power consumption, input signals should swing over the full supply.
INPUT
DIP TERMINAL
CONDITIONS
FUNCTION
B0
27
V
DD
= Logical One
V
SS
= Logical Zero
Ones (Least Significant)
Data Input Bits
B1
28
V
DD
= Logical One
V
SS
= Logical Zero
Twos
B2
29
V
DD
= Logical One
V
SS
= Logical Zero
Fours
B3
30
V
DD
= Logical One
V
SS
= Logical Zero
Eights (Most Significant)
ICM7211AM
ICM7211AM
4
FN3158.5
November 16, 2004
OSC
36
Floating or with External
Capacitor to V
DD
Oscillator Input
V
SS
Disables BP output devices, allowing segments to be synchronized to an
external signal input at the BP terminal (Pin 5).
Interface Input Configuration
INPUT
DESCRIPTION
DIP TERMINAL
CONDITIONS
FUNCTION
DA1
Digit Address
Bit 1 (LSB)
31
V
DD
= Logical One
V
SS
= Logical Zero
DA1 and DA2 serve as a 2-bit Digit Address Input
DA2, DA1 = 00 selects D4
DA2, DA1 = 01 selects D3
DA2, DA1 = 10 selects D2
DA2, DA1 = 11 selects D1
DA2
Digit Address
Bit 2 (MSB)
32
V
DD
= Logical One
V
SS
= Logical Zero
CS1
Chip Select 1
33
V
DD
= Inactive
V
SS
= Active
When both CS1 and CS2 are taken low, the data at the Data and Digit
Select code inputs are written into the input latches. On the rising edge
of either Chip Select, the data is decoded and written into the output
latches.
CS2
Chip Select 2
34
V
DD
= Inactive
V
SS
= Active
Input Definitions
In this table, V
DD
and V
SS
are considered to be normal operating input logic levels. Actual input low and high levels are specified
under Operating Characteristics. For lowest power consumption, input signals should swing over the full supply. (Continued)
INPUT
DIP TERMINAL
CONDITIONS
FUNCTION
Timing Diagram
FIGURE 1. MICROPROCESSOR INTERFACE INPUT
CS1
(CS2)
CS2
(CS1)
DATA AND
DIGIT
ADDRESS
= DON'T CARE
t
DH
t
DS
t
WI
t
ICS
Typical Performance Curves
FIGURE 2. OPERATING SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE
FIGURE 3. BACKPLANE FREQUENCY AS A FUNCTION OF
SUPPLY VOLTAGE
V
SUPP
(V)
4
1
2
3
6
7
5
30
25
20
15
10
5
I
OP
(
A)
DISPLAY BLANK, PIN 36 OPEN
T
A
= -20C
T
A
= 70C
T
A
= 25C
V
SUPP
(V)
4
1
2
3
6
5
180
150
120
90
60
30
BP
(H
z
)
T
A
= 25C
0
C
OSC
= 220pF
C
OSC
= 22pF
C
OSC
= 0pF
(PIN 36 OPEN)
ICM7211AM
ICM7211AM
5
FN3158.5
November 16, 2004
Description Of Operation
Device
The ICM7211AM provides outputs suitable for driving
conventional four-digit, seven-segment LCD displays. These
devices include 28 individual segment drivers, backplane
driver, and a self-contained oscillator and divider chain to
generate the backplane frequency.
The segment and backplane drivers each consist of a
CMOS inverter, with the N-Channel and P-Channel devices
ratioed to provide identical on resistances, and thus equal
rise and fall times. This eliminates any DC component, which
could arise from differing rise and fall times, and ensures
maximum display life.
The backplane output devices can be disabled by
connecting the OSCillator input (pin 36) to V
SS
. This allows
the 28 segment outputs to be synchronized directly to a
signal input at the BP terminal (pin 5). In this manner,
several slave devices may be cascaded to the backplane
output of one master device, or the backplane may be
derived from an external source. This allows the use of
displays with characters in multiples of four and a single
backplane. A slave device represents a load of
approximately 200pF (comparable to one additional
segment). Thus the limitation of the number of devices that
can be slaved to one master device backplane driver is the
additional load represented by the larger backplane of
displays of more than four digits. A good rule of thumb to
observe in order to minimize power consumption is to keep
the backplane rise and fall times less than about 5
s. The
backplane output driver should handle the backplane to a
display of 16 one-half inch characters. It is recommended, if
more than four devices are to be slaved together, the
backplane signal be derived externally and all the
ICM7211AM devices be slaved to it. This external signal
should be capable of driving very large capacitive loads with
short (1 - 2
s) rise and fall times. The maximum frequency
for a backplane signal should be about 150Hz although this
may be too fast for optimum display response at lower
display temperatures, depending on the display type.
The onboard oscillator is designed to free run at
approximately 19kHz at microampere current levels. The
oscillator frequency is divided by 128 to provide the
backplane frequency, which will be approximately 150Hz
with the oscillator free-running; the oscillator frequency may
be reduced by connecting an external capacitor between the
OSCillator terminal and V
DD
.
The oscillator may also be overdriven if desired, although care
must be taken to ensure that the backplane driver is not
disabled during the negative portion of the overdriving signal
(which could cause a DC component to the display). This can
be done by driving the OSCillator input between the positive
supply and a level out of the range where the backplane disable
is sensed (about one fifth of the supply voltage above V
SS
).
Another technique for overdriving the oscillator (with a signal
swinging the full supply) is to skew the duty cycle of the
overdriving signal such that the negative portion has a duration
shorter than about one microsecond. The backplane disable
sensing circuit will not respond to signals of this duration.
Input Configurations and Output Codes
The ICM7211AM accepts a four-bit true binary (i.e., positive
level = logical one) input at pins 27 thru 30, least significant
bit at pin 27 ascending to the most significant bit at pin 30. It
decodes the binary input into seven-segment alphanumeric
"Code B" output, i.e., 0-9, dash, E, H, L, P, blank. These
codes are shown explicitly in Table 1. It will correctly decode
true BCD to a seven-segment decimal output.
TABLE 1. OUTPUT CODES
BlNARY
CODE B
ICM7211AM
B3
B2
B1
BO
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
OSCILLATOR
FREQUENCY
BACKPLANE
INPUT/OUTPUT
OFF
ON
64 CYCLES
64 CYCLES
128 CYCLES
SEGMENTS
SEGMENTS
FIGURE 4. DISPLAY WAVEFORMS
ICM7211AM
ICM7211AM
6
FN3158.5
November 16, 2004
The ICM7211AM is intended to accept data from a data bus
under processor control.
In these devices, the four data input bits and the two-bit digit
address (DA1 pin 31, DA2 pin 32) are written into input
buffer latches when both chip select inputs (CS1 pin 33, CS2
pin 34) are taken low. On the rising edge of either chip select
input, the content of the data input latches is decoded and
stored in the output latches of the digit selected by the
contents of the digit address latches.
An address of 00 writes into D4, DA2 = 0, DA1 = 1 writes into
D3, DA2 = 1, DA1 = 0 writes into D2, and 11 writes into D1.
The timing relationships for inputting data are shown in
Figure 1, and the chip select pulse widths and data setup and
hold times are specified under Operating Characteristics.
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
BLANK
TABLE 1. OUTPUT CODES (Continued)
BlNARY
CODE B
ICM7211AM
B3
B2
B1
BO
a
b
c
d
f
g
e
FIGURE 5. SEGMENT ASSIGNMENT
Test Circuit
FIGURE 6.
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
DIGIT/CHIP
ICM7211AM
DATA
INPUTS
SELECT
INPUTS
V
SS
OSC
V
DD
BP
V
DD
V
DD
V
SS
MICROPROCESSOR
VERSION
MULTIPLEXED
VERSION
EACH SEGMENT
OUTPUT TO
BACKPLANE
WITH A 200pF
CAPACITOR
+
-
V
SS
V
DD
ICM7211AM
ICM7211AM
7
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN3158.5
November 16, 2004
Typical Application
FIGURE 7. 80C48 MICROPROCESSOR INTERFACE
28
40
39 T1
P27 38
37
36
35
P17 34
33
32
31
30
29
P10 27
26
PROG
22
24
23
P20 21
80C48
COMPUTER
2 XTAL1
13
3 XTAL2
4 RESET
5 SS
6 INT
7 EA
RD
DB0 12
14
15
16
17
18
19
20
1 TO
PSEN
ALE
V
CC
V
DD
V
SS
11
9
25
DB7
10
8
27 28 29 30
CS2
36 OSC
35 V
SS
1 V
DD
+5V
8 DIGIT
LCD DISPLAY
SEGMENTS
HIGH ORDER DIGITS
ICM7211AM
INPUT
NC
+5V
I/O
I/O
DS1 DS2
CS1
31
32
33
34
DATA
2, 3, 4
BP 5
37-40
6-26
B0-B3
29
28
27
30
CS2
36 OSC
35 V
SS
1 V
DD
+5V
SEGMENTS
LOW ORDER DIGITS
ICM7211AM
DS1 DS2
CS1
31
32
33
34
DATA
2, 3, 4
BP 5
37-40
6-26
B0-B3
WR
ICM7211AM
ICM7211AM
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