1
Features
CMOS Design for Very Low Power
Output
Drivers
Directly
Drive
Both
Digits
and
Segments of Large 8-Digit LED Displays
Measures Frequencies from DC to 10MHz; Periods
from 0.5
s to 10s
Stable High Frequency Oscillator uses either 1MHz or
10MHz Crystal
Both Common Anode and Common Cathode Available
Control
Signals
Available
for
External
Systems
Interfacing
Multiplexed BCD Outputs
Applications
Frequency Counter
Period Counter
Unit Counter
Frequency Ratio Counter
Time Interval Counter
Description
The ICM7226 is a fully integrated Universal Counter and
LED display driver. It combines a high frequency oscillator, a
decade timebase counter, an 8-decade data counter and
latches, a 7-segment decoder, digit multiplexer and segment
and digit drivers which can directly drive large LED displays.
The counter inputs accept a maximum frequency of 10MHz
in frequency and unit counter modes and 2MHz in the other
modes. Both inputs are digital inputs. In many applications,
amplification and level shifting will be required to obtain
proper digital signals for these inputs.
The ICM7226 can function as a frequency counter, period
counter, frequency ratio (f
A
/f
B
) counter, time interval counter
or as a totalizing counter. The devices require either a
10MHz or 1MHz quartz crystal timebase, or if desired an
external timebase can also be used. For period and time
interval, the 10MHz timebase gives a 0.1
s resolution. In
period average and time interval average, the resolution can
be in the nanosecond range. In the frequency mode, the
user can select accumulation times of 0.01s, 0.1s, 1s and
10s. With a 10s accumulation time, the frequency can be
displayed to a resolution of 0.1Hz. There is 0.2s between
measurements in all ranges. Control signals are provided to
enable gating and storing of prescaler data.
Leading zero blanking has been incorporated with frequency
display in kHz and time in
s. The display is multiplexed at a
500Hz rate with a 12.2% duty cycle for each digit. The
ICM7226A is designed for common anode displays with typi-
cal peak segment currents of 25mA, and the ICM7226B is
designed for common cathode displays with typical segment
currents of 12mA. In the display off mode, both digit drivers
and segment drivers are turned off, allowing the display to
be used for other functions.
Part Number Information
PART NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG.
NO.
ICM7226AlJL
-25 to 85
40 Ld CERDIP
F40.6
ICM7226BlPL
-25 to 85
40 Ld PDIP
E40.6
May 2001
ICM7226A,
ICM7226B
8-Digit, Multi-Function,
Frequency Counter/Timer
File Number
3169.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Americas Inc.
|
Copyright Intersil Americas Inc. 2001
itle
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ICM72
16
2
Pinouts
ICM7226A
COMMON ANODE (CERDIP)
TOP VIEW
ICM7226B
COMMON CATHODE (PDIP)
TOP VIEW
NOTE:
1. For maximum frequency stability, connect to V
DD
or V
SS
.
CONTROL INPUT
INPUT B
FUNCTION
SEG
e
SEG
g
SEG
a
V
SS
SEG
d
SEG
b
SEG
c
SEG
f
RST INPUT
EXT DP IN
INPUT A
BUF OSC OUT
OSC OUT
EXT RANGE
D1
D3
D5
V
DD
D6
D7
D8
HOLD
D2
D4
STORE
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
RANGE
OSC IN
NC (NOTE 1)
NC (NOTE 1)
EXT OSC IN
RST OUT
MEASUREMENT IN PROGRESS
BCD 2
BCD 1
BCD 4
BCD 8
DP
CONTROL INPUT
INPUT B
FUNCTION
D3
D2
D4
V
SS
D5
D6
D7
D8
RST INPUT
EXT DP IN
INPUT A
BUF OSC OUT
OSC OUT
EXT RANGE
DP OUT
SEG
e
SEG
d
V
DD
SEG
b
SEG
c
SEG
f
HOLD
SEG
g
SEG
a
STORE
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
RANGE
OSC IN
NC (NOTE 1)
NC (NOTE 1)
EXT OSC IN
RST OUT
MEASUREMENT IN PROGRESS
BCD 2
BCD 1
BCD 4
BCD 8
D1
ICM7226A, ICM7226B
3
Functional Block Diagram
STORE
AND RESET
REFERENCE
DIGIT
DECODER
OSC
10
4
OR
RANGE
CONTROL
DP
DECODER
SEGMENT
INPUT
INPUT
FN
MAIN
DRIVERS
COUNTER
+10
3
LOGIC
FF
CONTROL
LOGIC
CONTROL
LOGIC
CONTROL
LOGIC
DATA LATCHES
OUTPUT MUX
MAIN
10
3
SELECT
CONTROL
LOGIC
LOGIC
DRIVERS
AND LZB
FUNCTION
INPUT
D
CL
EN
CL
OVERFLOW
STORE
100Hz
Q
HOLD
INPUT
INPUT B
SEGMENT
OUTPUTS
EXT
DP
INPUT
CONTROL
INPUT
DIGIT
OUTPUTS
(8)
(8)
3
8
8
5
6
4
7
8
6
4
4
4
4
4
4
4
4
LOGIC
RANGE
SELECT
LOGIC
10
5
EXT RANGE
INPUT
LOGIC
4
4
MEAS IN
PROGRESS
OUTPUT
RANGE
INPUT
EXT OSC
INPUT
OSC
INPUT
BUF OSC
OUTPUT
RESET
INPUT
INPUT A
OSC
OUTPUT
COUNTER
RESET
BCD
OUTPUTS
(4)
RESET
OUTPUT
STORE
OUTPUT
8
R
ICM7226A, ICM7226B
4
Absolute Maximum Ratings
Thermal Information
Maximum Supply Voltage (V
DD
- V
SS
). . . . . . . . . . . . . . . . . . . . 6.5V
Maximum Digit Output Current . . . . . . . . . . . . . . . . . . . . . . . . 400mA
Maximum Segment Output Current . . . . . . . . . . . . . . . . . . . . . 60mA
Voltage On Any Input or
Output Terminal (Note 1) . . . . . . . . . . . . . . V
DD
+0.3V to V
SS
-0.3V
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -25
o
C to 85
o
C
Thermal Resistance (Typical, Note 2)
JA
(
o
C/W)
JC
(
o
C/W)
CERDIP Package . . . . . . . . . . . . . . . .
45
9
PDIP Package . . . . . . . . . . . . . . . . . . .
50
N/A
Maximum Junction Temperature
CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
o
C
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -55
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Destructive latchup may occur if input signals are applied before the power supply is established or if inputs or outputs are forced to
voltages exceeding V
DD
or V
SS
by 0.3V.
2.
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
V
DD
= 5.0V, T
A
= 25
o
C, Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Operating Supply Current, I
DD
Display Off, Unused Inputs to V
SS
-
2
5
mA
Supply Voltage Range (V
DD
-V
SS
), V
SUPPLY
-25
o
C to 85
o
C, INPUT A,
INPUT B Frequency at f
MAX
4.75
-
6.0
V
Maximum Frequency INPUT A, Pin 40, f
A(MAX)
-25
o
C to 85
o
C
4.75V < V
DD
< 6.0V, Figure 9
Function = Frequency, Ratio,
Unit Counter
10
14
-
MHz
Function = Period, Time Interval
2.5
-
-
MHz
Maximum Frequency INPUT B, Pin 2, f
B (MAX)
-25
o
C to 85
o
C
4.75V < V
DD
< 6.0V, Figure 10
2.5
-
-
MHz
Minimum Separation INPUT A to INPUT B,
Time Interval Function
-25
o
C to 85
o
C
4.75V < V
DD
< 6.0V, Figure 1
250
-
-
ns
Oscillator Frequency and External Oscillator Frequency,
f
OSC
-25
o
C to 85
o
C
4.75V < V
DD
< 6.0V
0.1
-
10
MHz
Oscillator Transconductance, g
M
V
DD
-4.75V, T
A
= 85
o
C
2000
-
-
S
Multiplex Frequency, f
MUX
f
OSC
= 10MHz
-
500
-
Hz
Time Between Measurements
f
OSC
= 10MHz
-
200
-
ms
Input Rate of Charge, dV
IN
/dt
Inputs A, B
-
15
-
mV/
s
Input Voltages: Pins 2, 19, 33, 39, 40, 35
Input Low Voltage, V
IL
-25
o
C to 85
o
C
-
-
1.0
V
Input High Voltage, V
lH
3.5
-
-
V
Pins 2, 39, 40, Input Leakage, A, B, I
ILK
-
-
20
A
Input Resistance to V
DD
Pins 19, 33, R
IN
V
IN
= V
DD
-1.0V
100
400
-
k
Input Resistance to V
SS
Pin 31, R
IN
V
IN
= +1.0V
50
100
-
k
Output Current
Low Output Current, Pins 3, 5-7, 17, 18, 32, 38, I
OL
V
OL
= +0.4V
400
-
-
A
High Output Current, Pins 5-7, 17, 18, 32, H
OL
V
OH
= +2.4V
100
-
-
A
High Output Current, Pins 3, 38, H
OL
V
OH
= V
DD
-0.8V
265
-
-
A
ICM7226A
Segment Driver: Pins 8-11, 13-16
Low Output Current, I
OL
V
O
= +1.5V
25
35
-
mA
High Output Current, I
OH
V
O
= V
DD
-1.0V
-
100
-
A
ICM7226A, ICM7226B
5
Timing Waveform
Multiplex Inputs: Pins 1, 4, 20, 21
Input Low Voltage, V
IL
-
-
0.8
V
Input High Voltage, V
IH
2.0
-
-
V
Input Resistance to V
SS
, R
IN
V
IN
= +1.0V
50
100
-
k
Digit Driver: Pins 22-24, 26-30
Low Output Current, I
OL
V
O
= +1.0V
-
-0.3
-
mA
High Output Current, I
OH
V
O
= V
DD
-2.0V
150
180
-
mA
ICM7226B
Segment Driver: Pins 22-24, 26-30
Leakage Current, I
L
V
O
= V
SS
-
-
10
A
High Output Current, I
OH
V
O
= V
DD
-2.0V
10
15
-
mA
Multiplex Inputs: Pins 1, 4, 20, 21
Input Low Voltage, V
IL
-
-
V
DD
-2.0
V
Input High Voltage, V
IH
V
DD
-0.8
-
-
V
Input Resistance to V
SS
, R
IN
V
IN
= V
DD
-1.0V
100
360
-
k
Digit Driver: Pins 8-11, 13-16
Low Output Current, I
OL
V
O
= +1.0V
50
75
-
mA
High Output Current, I
OH
V
O
= V
DD
-2.5V
-
100
-
A
NOTES:
1. Assumes all leads soldered or welded to PC board and free air flow.
2. Typical values are not tested.
Electrical Specifications
V
DD
= 5.0V, T
A
= 25
o
C, Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
MEASUREMENT
IN PROGRESS
30ms TO 40ms
STORE
RESET
INPUT A
INPUT B
PRIMING EDGES
PRIMING
FUNCTION:
TIME INTERVAL
UPDATE
190ms TO 200ms
40ms
60ms
40ms
MEASUREMENT INTERVAL
250ns MIN
MEASURED
INTERVAL
(FIRST)
MEASURED
INTERVAL
(LAST)
UPDATE
NOTE:
1. If range is set to 1 event, first and last measured interval will coincide.
FIGURE 1. WAVEFORMS FOR TIME INTERVAL MEASUREMENT (OTHERS ARE SIMILAR, BUT WITHOUT PRIMING PHASE)
ICM7226A, ICM7226B
6
Typical Performance Curves
FIGURE 2. ICM7226B TYPICAL I
DIGIT
vs V
OUT
FIGURE 3. ICM7226A TYPICAL I
DIG
vs V
DD
-V
OUT
FIGURE 4. ICM7226B TYPICAL I
SEG
vs V
DD
-V
OUT
FIGURE 5. ICM7226A TYPICAL I
SEG
vs V
OUT
FIGURE 6. ICM7226B TYPICAL I
DIGIT
vs V
OUT
FIGURE 7. ICM7226A TYPICAL I
SEG
vs V
OUT
V
DD
= 5.5V
200
50
100
0
0
1
2
3
V
OUT
(V)
I
D
IGI
T
(m
A
)
50
T
A
= 25
o
C
V
DD
= 4.5V
V
DD
= 5.0V
85
o
C
-20
o
C
4.5
V
DD
6.0V
300
200
100
0
0
1
2
3
V
DD
-V
OUT
(V)
I
DI
G
(mA
)
25
o
C
85
o
C
-20
o
C
4.5
V
DD
6.0V
30
20
10
0
0
1
2
3
V
DD
-V
OUT
(V)
I
SE
G
(mA
)
25
o
C
V
DD
= 5.5V
80
60
40
0
0
1
2
3
V
OUT
(V)
I
SE
G
(m
A
)
20
T
A
= 25
o
C
V
DD
= 4.5V
V
DD
= 5.0V
85
o
C
-20
o
C
V
DD
= 5.0V
200
150
100
0
0
1
2
3
V
OUT
(V)
I
DI
G
I
T
(mA
)
25
o
C
50
85
o
C
-20
o
C
V
DD
= 5.0V
80
60
40
0
0
1
2
3
V
OUT
(V)
I
SE
G
(mA
)
25
o
C
20
ICM7226A, ICM7226B
7
Description
INPUTS A and B
The signal to be measured is applied to INPUT A in
frequency period, unit counter, frequency ratio and time
interval modes. The other input signal to be measured is
applied to INPUT B in frequency ratio and time interval. f
A
should be higher than f
B
during frequency ratio.
Both inputs are digital inputs with a typical switching thresh-
old of 2.0V at V
DD
= 5.0V and input impedance of 250k
.
For optimum performance, the peak-to-peak input signal
should be at least 50% of the supply voltage and centered
about the switching voltage. When these inputs are being
driven from TTL logic, it is desirable to use a pullup resistor.
The circuit counts high to low transitions at both inputs
Note that the amplitude of the input should not exceed the
device supply (above the V
DD
and below the V
SS
) by more
than 0.3V, otherwise the device may be damaged.
Multiplexed Inputs
The FUNCTION, RANGE, CONTROL and EXTERNAL
DECIMAL POINT inputs are time multiplexed to select the
function desired. This is achieved by connecting the appro-
priate Digit driver output to the inputs. The function, range
and control inputs must be stable during the last half of each
digit output, (typically 125
s). The multiplexed inputs are
active high for the common anode lCM7226A and active low
for the common cathode lCM7226B.
Noise on the multiplex inputs can cause improper operation.
This is particularly true when the unit counter mode of
operation is selected, since changes in voltage on the digit
drivers can be capacitively coupled through the LED diodes
to the multiplex inputs. For maximum noise immunity, a 10k
resistor should be placed in series with the multiplexed
inputs as shown in the application circuits.
FIGURE 8. f
A
(MAX), f
B
(MAX) AS A FUNCTION OF SUPPLY
Typical Performance Curves
(Continued)
f
A
(MAX) FREQUENCY UNIT COUNTER,
FREQUENCY RATIO MODES
f
A
(MAX) f
B
(MAX) PERIOD
TIME INTERVAL MODES
T
A
= 25
o
C
V
DD
-V
SS
(V)
F
R
E
Q
UE
NCY
(
M
Hz
)
20
15
10
5
0
3
4
5
6
INPUT A
4.5V
0.5V
50ns MIN
t
r
= t
f
= 10ns
COUNTED
TRANSITIONS
50ns MIN
FIGURE 9. WAVEFORM FOR GUARANTEED MINIMUM f
A
(MAX)
FUNCTION = FREQUENCY, FREQUENCY RATIO,
UNIT COUNTER
INPUT A OR
INPUT B
4.5V
0.5V
MEASURED
INTERVAL
250ns
MIN
t
r
= t
f
= 10s
250ns
MIN
FIGURE 10. WAVEFORM FOR GUARANTEED MINIMUM f
B
(MAX)
AND f
A
(MAX) FOR FUNCTION = PERIOD AND
TIME INTERVAL
ICM7226A, ICM7226B
8
Table 1 shows the functions selected by each digit for these
inputs.
Function Input
The six functions that can be selected are: Frequency,
Period, Time Interval, Unit Counter, Frequency Ratio and
Oscillator Frequency.
The implementation of different functions is done by routing
the different signals to two counters, called "Main Counter"
and "Reference Counter". A simplified block diagram of the
device for functions realization is shown in Figure 11. Table 2
shows which signals will be routed to each counter in differ-
ent cases. The output of the Main Counter is the information
which goes to the display. The Reference Counter divides its
input to 1, 10, 100 and 1000. One of these outputs will be
selected through the range selector and drive the enable
input of the Main Counter. This means that the Reference
Counter, along with its' associated blocks, directs the Main
Counter to begin counting and determines the length of the
counting period. Note that Figure 11 does not show the com-
plete functional diagram (See the Functional Block Dia-
gram). After the end of each counting period, the output of
the Main Counter will be latched and displayed, then the
counter will be reset and a new measurement cycle will
begin. Any change in the FUNCTION INPUT will stop the
present measurement without updating the display and then
initiate a new measurement. This prevents an erroneous first
reading after the FUNCTION INPUT is changed. In all
cases, the 1-0 transitions are counted or timed.
TABLE 1. MULTIPLEXED INPUT FUNCTIONS
INPUT
FUNCTION
DIGIT
FUNCTION INPUT
Pin 4
Frequency
D1
Period
D8
Frequency Ratio
D2
Time Interval
D5
Unit Counter
D4
Oscillator Frequency
D3
RANGE INPUT
Pin 21
0.01s/1 Cycle
D1
0.1s/10 Cycles
D2
1s/100 Cycles
D3
10s/1K Cycles
D4
Enable External Range Input
D5
CONTROL INPUT
Pin 1
Display Off
D4 and
Hold
Display Test
D8
1MHz Select
D2
External Oscillator Enable
D1
External Decimal Point
Enable
D3
External DP INPUT
Pin 20
Decimal point is output for same digit
that is connected to this input.
TABLE 2. INPUT ROUTING
FUNCTION
MAIN
COUNTER
COUNTER
Frequency (f
A
)
Input A
100Hz (Oscillator
10
5
or 10
4
)
Period (t
A
)
Oscillator
Input A
Ratio (f
A
/f
B
)
Input A
Input B
Time Interval
(A
B)
Oscillator
Input A
Input B
Unit Counter
(Count A)
Input A
Not Applicable
Osc. Freq.
(f
OSC
)
Oscillator
100Hz (Oscillator
10
5
or 10
4
)
INTERNAL CONTROL
100Hz
INPUT A
INPUT B
INPUT
SELECTOR
INTERNAL OR
EXTERNAL
OSCILLATOR
INPUT A
ENABLE
CLOCK
MAIN COUNTER
RANGE SELECTOR
1
10
100
1000
INTERNAL CONTROL
INTERNAL CONTROL
CLOCK
INTERNAL CONTROL
INPUT
SELECTOR
REFERENCE COUNTER
FIGURE 11. SIMPLIFIED BLOCK DIAGRAM OF FUNCTIONS IMPLEMENTATION
ICM7226A, ICM7226B
9
Frequency - In this mode input A is counted by the Main
Counter for a precise period of time. This time is determined
by the time base oscillator and the selected range. For the
10MHz (or 1MHz) time base, the resolutions are 100Hz,
10Hz, 1Hz and 0.1Hz. The decimal point on the display is
set for kHz reading.
Period - In this mode, the timebase oscillator is counted by
the Main Counter for the duration of 1, 10, 100 or 1000
(range selected) periods of the signal at input A. A 10MHz
timebase gives resolutions of 0.1
s to 0.0001
s for 1000
periods averaging. Note that the maximum input frequency
for period measurement is 2.5MHz.
Frequency Ratio - In this mode, the input A is counted by
the Main Counter for the duration of 1, 10, 100 or 1000
(range selected) periods of the signal at input B. The fre-
quency at input A should be higher than input B for meaning-
ful result. The result in this case is unitless and its resolution
can go up to 3 digits after decimal point.
Time Interval - In this mode, the timebase oscillator is counted
by the Main Counter for the duration of a 1-0 transition of input
A until a 1-0 transition of input B. This means input A starts the
counting and input B stops it. If other ranges, except 0.01s/1
cycle are selected the sequence of input A and B transitions
must happen 10, 100 or 1000 times until the display becomes
updated; note this when measuring long time intervals to give
enough time for measurement completion. The resolution in
this mode is the same as for period measurement. See the
Time Interval Measurement section also.
Unit Counter - In this mode, the Main Counter is always
enabled. The input A is counted by the Main Counter and
displayed continuously.
Oscillator Frequency - In this mode, the device makes a
frequency measurement on its timebase. This is a self test
mode for device functionality check. For 10MHz timebase
the display will show 10000.0, 10000.00, 10000.000 and
Overflow in different ranges.
Range Input
The RANGE INPUT selects whether the measurement period is
made for 1,10,100 or 1000 counts of the Reference Counter or it
is controlled by EXT RANGE input. As it is shown in Table 1, this
gives different counting windows for frequency measurement
and various cycles for other modes of measurement.
In all functional modes except Unit Counter, any change in
the RANGE INPUT will stop the present measurement with-
out updating the display and then initiate a new measure-
ment. This prevents an erroneous first reading after the
RANGE INPUT is changed.
Control Input
Unlike the other multiplexed inputs, to which only one of the
digit outputs can be connected at a time, this input can be
tied to different digit lines to select combination of controls.
In this case, isolation diodes must be used in digit lines to
avoid crosstalk between them (see Figure 19). The direction
of diodes depends on the device version, common anode or
common cathode. For maximum noise immunity at this input,
in addition to the 10K resistor which was mentioned before,
a 39pF to 100pF capacitor should also be placed between
this input and the V
DD
or V
SS
(See Figure 19).
Display Off - To disable the display drivers, it is necessary to tie
the D4 line to the CONTROL INPUT and have the HOLD input
at V
DD
. While in Display Off mode, the segments and digit driv-
ers are all off, leaving the display lines floating, so the display
can be shared with other devices. In this mode, the oscillator
continues to run with a typical supply current of 1.5mA with a
10MHz crystal, but no measurements are made and multi-
plexed inputs are inactive. A new measurement cycle will be ini-
tiated when the HOLD input is switched to V
SS
.
Display Test - Display will turn on with all the digits showing
8s and all decimal points also on. The display will be blanked
if Display Off is selected at the same time.
1MHz Select - The 1MHz select mode allows use of a 1MHz
crystal with the same digit multiplex rate and time between
measurement as with a 10MHz crystal. This is done by divid-
ing the oscillator frequency by 10
4
rather than 10
5
. The dec-
imal point is also shifted one digit to the right in period and
time interval, since the least significant digit will be in
s
increment rather than 0.1
s increment.
External Oscillator Enable - In this mode, the signal at EXT
OSC INPUT is used as a timebase instead of the on-board
crystal oscillator (built around the OSC INPUT, OSC OUTPUT
inputs). This input can be used for an external stable tempera-
ture compensated crystal oscillator or for special measure-
ments with any external source. The on-board crystal oscillator
continues to work when the external oscillator is selected. This
is necessary to avoid hang-up problems, and has no effect on
the chip's functional operation. If the on-board oscillator fre-
quency is less than 1MHz or only the external oscillator is used,
THE OSC INPUT MUST BE CONNECTED TO THE EXT OSC
INPUT providing the timebase has enough voltage swing for
OSC INPUT (See Electrical Specifications). If the external time-
base is TTL level a pullup resistor must be used for OSC
INPUT. The other way is to put a 22M
resistor between OSC
INPUT and OSC OUTPUT and capacitively couple the EXT
OSC INPUT to OSC INPUT. This will bias the OSC INPUT at
its threshold and the drive voltage will need to be only 2V
P-P
.
The external timebase frequency must be greater than 100kHz
or the chip will reset itself to enable the on-board oscillator.
External Decimal Point Enable - In this mode, the EX DP
INPUT is enabled. A decimal point will be displayed for the
digit that its output line is connected to this input (EX DP
INPUT). Digit 8 should not be used since it will override the
overflow output. Leading zero blanking is effective for the
digits to the left of selected decimal point.
Hold Input
Except in the unit counter mode, when the HOLD input is
at V
DD
, any measurement in progress (before STORE goes
low) is stopped, the main counter is reset and the chip is
held ready to initiate a new measurement as soon as HOLD
goes low. The latches which hold the main counter data are
not updated, so the last complete measurement is displayed.
In unit counter mode when HOLD input is at V
DD
, the
counter is not stopped or reset, but the display is frozen at
that instantaneous value. When HOLD goes low the count
continues from the new value in the new counter.
ICM7226A, ICM7226B
10
RST IN Input
The RST IN is provided to reset the Main Counter, stop any
measurement in progress, and enable the display latches,
resulting in the all zero display. It is suggested to have a
capacitor at this input to V
SS
to prevent any hangup problem
on power up. See application circuits.
EXT RANGE Input
This input is provided to select ranges other than those
provided in the chip. In any mode of measurement the duration
of measurement is determined by the EXT RANGE if this input
is enabled. This input is sampled at 10ms intervals by the
100Hz reference derived from the timebase. Figure 12 shows
the relationship between this input, 100Hz reference signal and
MEAS IN PROGRESS. EXT RANGE can change state
anywhere during the period of 100Hz reference by will be
sampled at the trailing edge of the period to start or stop
measurement.
This input should not be used for short arbitrary ranges
(because of its sampling period), it is provided for very long
gating purposes. A way of using the ICM7226 for a short
arbitrary range is to feed the gating signal into the INPUT B
and run the device in the Frequency Ratio mode. Note that
the gating period will be from one positive edge until the next
positive edge of INPUT B (0.01s/1 cycle range).
MEAS IN PROGRESS, STORE, RST OUT Outputs
These outputs are provided for external system interfacing.
MEAS IN PROGRESS stays low during measurements and
goes high for intervals between measurements. Figure 13
shows the relationship between these outputs for intervals
between measurements. All these outputs can drive a low
power Schottky TTL. The MEAS IN PROGRESS can drive
one ECL load if the ECL device is powered from the same
power supply as the ICM7226.
BCD Outputs
The BCD representation of each display digit is available at
the BCD outputs in a multiplexed fashion. See Table 3 for dig-
its truth table. The BCD output of each digit is available when
its corresponding digit output is activated. Note that the digit
outputs are multiplexed from D8 (MSD) to D1 (LSD). The pos-
itive going (ICM7226A, common anode) or the negative going
(ICM7226B, common cathode) digit drive signals lag the BCD
data by 2
s to 6
s. This starting edge of each digit drive sig-
nal should be used to externally latch the BCD data. Each
BCD output drives one low power Schottky TTL load. Leading
zero blanking has no effect on the BCD outputs.
BUF OSC OUT Output
The BUFFered OSCillator OUTput is provided for use of the
on-board oscillator signal, without loading the oscillator itself.
This output can drive one low power Schottky TTL load. Care
should be taken to minimize capacitive loading on this pin.
Decimal Point Position
Table 4 shows the decimal point position for different modes
of lCM7226 operation. Note that the digit 1 is the least signif-
icant digit. Table is given for 10MHz timebase frequency.
REFERENCE
COUNTER
CLOCK
MEAS
IN PROGRESS
EXT RANGE
INPUT
t
r
FIGURE 12. EXTERNAL RANGE INPUT TO END OF
MEASUREMENT IN PROGRESS
TABLE 3. TRUTH TABLE BCD OUTPUTS
NUMBER
BCD 8
PIN 7
BCD 4
PIN 6
BCD 2
PIN 17
BCD 1
PIN 18
0
0
0
0
0
1
0
0
0
1
2
0
0
1
0
3
0
0
1
1
4
0
1
0
0
5
0
1
0
1
6
0
1
1
0
7
0
1
1
1
8
1
0
0
0
9
1
0
0
1
40ms
STORE
RESET OUT
60ms
30ms TO
40ms
40ms
190ms TO 200ms
MEAS
IN PROGRESS
FIGURE 13. RESET OUT, STORE AND MEASUREMENT IN
PROGRESS OUTPUTS BETWEEN MEASUREMENTS
TABLE 4. DECIMAL POINT POSITIONS
RANGE
FREQUENCY
PERIOD
FREQUENCY
RATIO
TIME
INTERVAL
UNIT
COUNTER
OSCILLATOR
FREQUENCY
0.01s/1 Cycle
D2
D2
D1
D2
D1
D2
0.1s/10 Cycle
D3
D3
D2
D3
D1
D3
1s/100 Cycle
D4
D4
D3
D4
D1
D4
10s/1K Cycle
D5
D5
D4
D5
D1
D5
External
N/A
N/A
N/A
N/A
N/A
N/A
ICM7226A, ICM7226B
11
Overflow Indication
When overflow happens in any measurement it will be indicated
on the decimal point of the digit 8. A separate LED indicator can
be used. Figure 14 shows how to connect this indicator.
Time Interval Measurement
When in the time interval mode and measuring a single
event, the lCM7226A and lCM7226B must first be "primed"
prior to measuring the event of interest. This is done by first
generating a negative going edge on Channel A followed by a
negative going edge on Channel B to start the "measurement
interval". The inputs are then primed ready for the measure-
ment. Positive going edges on A and B, before or after the
priming, will be needed to restore the original condition.
Priming can be easily accomplished using the circuit in
Figure 15.
Following the priming procedure (when in single event or 1
cycle range) the device is ready to measure one (only) event.
When timing repetitive signals, it is not necessary to "prime"
the lCM7226A and lCM7226B as the first alternating signal
states automatically prime the device. See Figure 1.
During any time interval measurement cycle, the ICM7226A
and lCM7226B requires 200ms following B going low to
update all internal logic. A new measurement cycle will not
take place until completion of this internal update time.
Oscillator Considerations
The oscillator is a high gain complementary FET inverter. An
external resistor of 10M
or 22M
should be connected
between the oscillator input and output to provide biasing.
The oscillator is designed to work with a parallel resonant
10MHz quartz crystal with a static capacitance of 22pF and
a series resistance of less than 35
. Among suitable
crystals is the 10MHz CTS KNIGHTS ISI-002.
For a specific crystal and load capacitance, the required g
M
can be calculated as follows:
C
O
= Crystal Static Capacitance
R
S
= Crystal Series Resistance
C
IN
= Input Capacitance
C
OUT
= Output Capacitance
= 2
f
The required g
M
should not exceed 50% of the g
M
specified
for the lCM7226 to insure reliable startup. The OSCillator
INPUT and OUTPUT pins each contribute about 4pF to C
IN
and C
OUT
. For maximum stability of frequency, C
IN
and
C
OUT
should be approximately twice the specified crystal
static capacitance.
In cases where non decade prescalers are used, it may be
desirable to use a crystal which is neither 10MHz or 1MHz.
In that case both the multiplex rate and time between
measurements will be different. The multiplex rate is:
for 10MHz mode and
for the
1MHz mode. The time between measurements is
in
the 10MHz mode and
in the 1MHz mode.
The buffered oscillator output should be used as an oscillator
test point or to drive additional logic; this output will drive one
low power Schottky TTL load. When the buffered oscillator
output is used to drive CMOS or the external oscillator input,
a 10k
resistor should be added from the buffered oscillator
output to V
DD
.
The crystal and oscillator components should be located as
close to the chip as practical to minimize pickup from other
signals. Coupling from the EXTERNAL OSClLLATOR INPUT
to the OSClLLATOR OUTPUT or INPUT can cause
undesirable shifts in oscillator frequency.
a
b
c
d
f
g
e
DP
LED
overflow
indicator
connections: Overflow
will
be
indicated on the decimal point output of digit 8.
FIGURE 14. SEGMENT IDENTIFICATION AND DISPLAY FONT
DEVICE
CATHODE
ANODE
ICM7226A
Decimal Point
D8
ICM7226B
D8
Decimal Point
SIGNAL A
SIGNAL B
INPUT A
INPUT B
V
DD
N.O.
100K
1N914
V
DD
150K
1
0.1
F
10K
10nF
1
1
1
2
2
V
SS
V
SS
V
SS
PRIME
FIGURE 15. PRIMING CIRCUIT, SIGNALS A AND B BOTH HIGH
OR LOW
DEVICE
TYPE
1
CD4049B Inverting Buffer
2
CD4070B Exclusive - OR
g
M
2
C
IN
C
OUT
R
S
1
C
O
C
L
--------
+
2
=
where C
L
C
IN
C
OU T
C
IN
C
OUT
+
---------------------------------
=
f
MUX
f
OSC
2
10
4
-------------------
=
f
MUX
f
OSC
2
10
3
-------------------
=
2
10
6
f
OSC
-------------------
2
10
5
f
OSC
-------------------
ICM7226A, ICM7226B
12
Display Considerations
The display is multiplexed at a 500Hz rate with a digit time of
244
s. An interdigit blanking time of 6
s is used to prevent
display ghosting (faint display of data from previous digit
superimposed on the next digit). Leading zero blanking is
provided, which blanks the left hand zeroes after decimal
point or any non zero digits. Digits to the right of the decimal
point are always displayed. The leading zero blanking will be
disabled when the Main Counter overflows.
The lCM7226A is designed to drive common anode LED dis-
plays at peak current of 25mA/segment, using displays with
V
F
= 1.8V at 25mA. The average DC current will be greater
than 3mA under these conditions. The lCM7226B is designed
to drive common cathode displays at peak current of
15mA/segment using displays with V
F
= 1.8V at 15mA. Resis-
tors can be added in series with the segment drivers to limit
the display current, if required. The Typical Performance
Curves show the digit and segment currents as a function of
output voltage for common anode and common cathode
drivers.
To increase the light output from the displays, V
DD
may be
increased to 6.0V. However, care should be taken to see that
maximum power and current ratings are not exceeded.
The SEGment and Digit outputs in both the ICM7226A and
ICM7226B are not directly compatible with either TTL or
CMOS logic. Therefore, level shifting with discrete transis-
tors may be required to use these outputs as logic signals.
External latching should be down on the leading edge of the
digit signal.
Accuracy
In a Universal Counter, crystal drift and quantization errors
cause errors. In frequency, period and time interval
modes, a signal derived from the oscillator is used in either
the Reference Counter or Main Counter, and in these
modes, an error in the oscillator frequency will cause an
identical error in the measurement. For instance, an oscilla-
tor temperature coefficient of 20ppm/
o
C will cause a mea-
surement error of 20ppm/
o
C.
In addition, there is a quantization error inherent in any digi-
tal measurement of
1 count. Clearly this error is reduced by
displaying more digits. In the frequency mode maximum
accuracy is obtained with high frequency inputs and in
period mode maximum accuracy is obtained with low fre-
quency inputs. As can be seen in Figure 16. In time interval
measurements there can be an error of 1 count per interval.
As a result there is the same inherent accuracy in all ranges
as shown in Figure 17. In frequency ratio measurement
can be more accurately obtained by averaging over more
cycles of INPUT B as shown in Figure 18.
FIGURE 16. MAXIMUM ACCURACY OF FREQUENCY AND
PERIOD MEASUREMENTS DUE TO LIMITATIONS
OF QUANTIZATION ERRORS
FIGURE 17. MAXIMUM ACCURACY OF TIME INTERVAL
MEASUREMENT DUE TO LIMITATIONS OF
QUANTIZATION ERRORS
FIGURE 18. MAXIMUM ACCURACY FOR FREQUENCY RATIO MEASUREMENT DUE TO LIMITATION OF QUANTIZATION ERRORS
FREQUENCY MEASURE
0
2
4
8
1
10
10
3
10
7
FREQUENCY (Hz)
M
A
X
I
M
U
M
NUM
BE
R
O
F
6
0.01s
S
I
G
N
IF
ICANT
DIG
I
T
S
10
5
0.1s
10s
1s
PERIOD MEASURE
f
OSC
= 10MHz
1 CYCLE
10 CYCLES
10
3
CYCLES
10
2
CYCLES
MAXIMUM TIME INTERVAL
FOR 10
3
INTERVALS
MAXIMUM TIME
INTERVAL FOR
10
2
INTERVALS
MAXIMUM TIME INTERVAL
FOR 10 INTERVALS
10
3
10
4
10
5
10
6
10
7
10
8
10
2
10
1
0
1
2
3
4
5
6
7
8
TIME INTERVAL (
s)
M
A
X
I
M
U
M
NUM
BE
R
O
F
S
I
G
N
IF
ICANT
DIG
I
T
S
1 CYCLE
10 CYCLES
10
3
CYCLES
10
2
CYCLES
RANGE
10
3
10
4
10
5
10
6
10
7
10
8
10
2
10
1
0
1
2
3
4
5
6
7
8
M
A
X
I
M
U
M
NUM
BE
R
O
F
S
I
G
N
IF
ICANT
DIG
I
T
S
f
A
/f
B
ICM7226A, ICM7226B
13
Test Circuit
CONTROL INPUT
BUF OSC OUT
EXT RANGE
HOLD
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
EXT OSC IN
RST OUT
MEAS IN PROGRESS
39pF
INPUT B
FUNCTION
GENERATOR
FUNCTION
INPUT A
GENERATOR
10K
DP
D1
D2
D3
D4
D8
D5
e
g
a
d
b
c
f
FUNCTION
STORE
BCD C
BCD D
BCD B
BCD A
RESET
a
b
c
d
e
f
g
DP
OVERFLOW
D8
D8
D7
D6
D5
D4
D3
D2
D1
8
8
6
6
DENOTES BUS
WITH 6
V
DD
= 5.0V
FUNCTION
GENERATOR
V
SS
10k
V
DD
V
DD
V
DD
22M
10MHz
CRYSTAL
V
DD
30pF
39pF
V
DD
D1
D2
D3
D4
D5
D6
D7
D8
V
DD
8
D1
D2
D3
D5
8
100k
D4
5
D8
D7
D6
D4
D1
D2
D3
D5
100k
DISPLAY
TEST
1MHz
EXT
TEST
DP
D8
D2
D1
D3
1N914s
DISPLAY
OFF
D4
EXT
OSC
D5
CONDUCTORS
CRYSTAL SPECS. =
F
O
C
O
R
S
10.00MHz
22pF
35
ICM7226A
6
FIGURE 19.
DEVICE
CATHODE
ANODE
ICM7226A
DP
D8
ICM7226B
D8
DP
NOTE: Overflow will be indicated on the decimal point output of digit 8.
ICM7226A, ICM7226B
14
Typical Applications
The ICM7226 has been designed as a complete stand alone
Universal Counter, or used with prescalers and other circuitry
in a variety of applications. Since INPUT A and INPUT B are
digital inputs, additional circuitry will be required in many
applications, for input buffering, amplification, hysteresis, and
level shifting to obtain the required digital voltages. For many
applications a FET source follower can be used for input buff-
ering, and an ECL 10116 line receiver can be used for amplifi-
cation and hysteresis to obtain high impedance input,
sensitivity and bandwidth. However, cost and complexity of
this circuitry can vary widely, depending upon the sensitivity
and bandwidth required. When TTL prescalers or input buffers
are used, a pull up resistors to V
DD
should be used to obtain
optimal voltage swing at INPUTS A and B. If prescalers aren't
required, the ICM7226 can be used to implement a minimum
component Universal Counter as shown in Figure 20.
For input frequencies up to 40MHz, the circuit shown in
Figure 21 can be used to implement a frequency and
period counter. To obtain the correct value when measuring
frequency and period, it is necessary to divide the 10MHz
oscillator frequency down to 2.5MHz. In doing this the time
between measurements is lengthened to 800ms and the dis-
play multiplex rate is decreased to 125Hz.
If the input frequency is prescaled by ten, the oscillator
frequency can remain at either 10MHz or 1MHz, but the
decimal point must be moved. Figure 22 shows use of a
10
prescaler in frequency counter mode. Additional logic has
been added to enable the ICM7226 to count the input
directly in period mode for maximum accuracy.
D8
HOLD
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
EXT OSC IN
39pF
10k
D3
D1
D2
D3
D4
D8
D5
g
e
a
d
b
c
f
RESET
D8
D7
D6
D5
D4
D3
D2
D1
8
6
V
DD
100k
V+
V+
22M
10MHz
CRYSTAL
V+
39pF
39pF (TYP)
V+
DP
D2
D5
D6
D7
D8
V
DD
D1
D2
D3
100k
D4
4
DISPLAY
TEST
D8
D1
1N914s
DISPLAY
BLANK
D4
TYPICAL
C
L
R
S
22pF
35
a
b
c
d
e
f
g
DP
0.1
F
ICM7226B
D4
B IN
A IN
V
DD
10k
8
CRYSTAL
PARAMETERS
EXT OSC
ENABLE
3
FIGURE 20. 10MHz UNIVERSAL COUNTER
OVERFLOW
ICM7226A, ICM7226B
15
D8
HOLD
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
39pF
10k
D3
g
e
a
d
b
c
f
RESET
D8
D7
D6
D5
D4
D3
D2
D1
8
V
DD
3k
V
DD
V
DD
22M
10MHz
CRYSTAL
V
DD
39pF
39pF (TYP)
V
DD
DP
D2
D5
D6
D7
D8
V
DD
D1
D2
D3
100k
D4
4
DI
S
P
L
A
Y
OF
F
D4
D8
1N914
DI
S
P
L
A
Y
T
EST
D1
a
b
c
d
e
f
g
DP
0.1
ICM7226B
D4
V
DD
8
EX
T
O
SC
E
NAB
L
E
3
10k
D1
F
8
3
D
Q
Q
C
P
V+
V+
B IN
D
Q
Q
C
P
V+
V+
V+
3k
D1
D8
D2
F
R
P
74LS74
D
Q
Q
C
P
V
DD
V
DD
A IN
74LS74
CK
D
Q
Q
C
P
V
DD
V
DD
CK1
IC
2
V
DD
100k
D
Q
Q
C
P
V
DD
V
DD
CK
D
Q
Q
C
P
V
DD
V
DD
CK2
IC
2
OVERFLOW
V
DD
3k
2
2
FIGURE 21. 40MHz FREQUENCY, PERIOD COUNTER
ICM7226A, ICM7226B
16
D8
HOLD
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
EXT OSC IN
39pF
D3
d
b
c
f
D8
D7
D6
D5
D4
D3
D2
D1
8
V
DD
10
V
DD
V
DD
22M
10MHz
CRYSTAL
V
DD
39pF
39pF
V
DD
D2
D5
D6
D7
D8
V
DD
D1
D2
D3
D5
5
DISPLAY
TEST
D8
D2
1N914s
DISPLAY
OFF
D4
a
b
c
d
e
f
g
DP
0.1
F
ICM7226A
D4
10k
EXT
8
8
100k
D4
RANGE
D1
8
OSC
EN
1MHz
D1
D3
OVERFLOW
100k
S6
(TYP)
k
10k
8
4
QTTL
F
V+ 10k
V+ 10k
MS
CE
CP
M1
V
DD
INPUT
ECL11C90
QTTL
MS
CE
CP
M1
V
DD
INPUT
ECL11C90
2
DP
a
g
e
P
R
UC
D1
D8
D2
D4
V+ 10k
74LS00
74LS00
FIGURE 22. 100MHz MULTI-FUNCTION COUNTER
ICM7226A, ICM7226B
17
D8
HOLD
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
39pF
10k
D4
D1
D3
D8
D7
D6
D5
D4
D3
D2
D1
8
V
DD
10k
V
DD
V
DD
22M
10MHz
CRYSTAL
V
DD
39pF
39pF
V
DD
V
DD
DISPLAY
TEST
D8
1N914s
DISPLAY
OFF
D4
a
b
c
d
e
f
g
0.1
F
ICM7226B
10k
3
10k
8
D1
OVERFLOW
100k
RESET
(TYP)
2N2222
10k
2
D3
g
e
a
d
b
c
f
DP
D2
D5
D6
D7
D8
D4
D1
D2
4
V
DD
V
DD
3k
10k
CONT 2
QTTL
MS
CE
CP
M1
V
DD
INPUT
ECL11C90
V
DD
V
DD
FUNCTION
SWITCH
OPEN FREQ
CLOSED
PERIOD
F
OUT
D1 IN
CD4016
CONT 2
OUT
D8 IN
V
DD
INPUT
N.O.
FIGURE 23. 100MHz FREQUENCY, PERIOD COUNTER
DP
ICM7226A, ICM7226B
18
Figure 23 shows the use of a CD4016 analog multiplexer to
multiplex the digital outputs back to the FUNCTION Input.
Since the CD4016 is a digitally controlled analog transmission
gate, no level shifting of the digit output is required. CD4051s
or CD4052s could also be used to select the proper inputs for
the multiplexed input on the ICM7226 from 2-bit or 3-bit digital
inputs. These analog multiplexers may also be used in sys-
tems in which the mode of operation is controlled by a micro-
processor rather than directly from front panel switches. TTL
multiplexers such as the 74LS153 or 74LS251 may also be
used, but some additional circuitry will be required to convert
the digit output to TTL compatible logic levels.
The circuit shown in Figure 24 can be used in any of the
circuit applications shown to implement a single measure-
ment mode of operation. This circuit uses the STORE output
to put the ICM7226 into a hold mode. The HOLD input can
also be used to reduce the time between measurements.
The circuit shown in Figure 25 puts a short pulse into the
HOLD input a short time after STORE goes low. A new mea-
surement will be initiated at the end of the pulse on the
HOLD input. This circuit reduces the time between measure-
ments to about 40ms from 200ms; use of the circuit shown in
Figure 25 on the circuit shown in Figure 21 will reduce the
time between measurements from 800ms to about 160ms.
Using LCD Display
Figure 26 shows the ICM7226 being interfaced to LCD dis-
plays, by using its BCD outputs and 8 digit lines to drive two
ICM7211 display drivers.
FIGURE 24. SINGLE MEASUREMENT CIRCUIT FOR USE WITH
ICM7226
FIGURE 25. CIRCUIT FOR REDUCING TIME BETWEEN
MEASUREMENTS
FIGURE 26. 10MHz UNIVERSAL COUNTER SYSTEM WITH LCD DISPLAY
V
DD
100k
STORE
OUTPUT
S1
V
DD
100k
S2
V
DD
100k
S3
HOLD
INPUT
SWITCH
FUNCTION
S1
Open-Single Meas Mode Enabled
S2
Closed-Initiate New Measurement
S3
Closed-Hold Input
V
DD
STORE
OUTPUT
HOLD
INPUT
100k
100pF
100pF
HOLD SWITCH
100k
N.O.
ICM7226A
a
b
c
d
f
g
e
a
b
c
d
f
g
e
a
b
c
d
f
g
e
a
b
c
d
f
g
e
a
b
c
d
f
g
e
a
b
c
d
f
g
e
a
b
c
d
f
g
e
a
b
c
d
f
g
e
ICM7211
ICM7211
5
28 SEGMENT LINES
28 SEGMENT LINES
5
1
+5V
35
31 32 33
34
22 23 24
26
30
29 28 27
30
29
28
27
18
17
6
7
31 32 33
34
27 28 29
30
1
+5V
35
36
D8
D1
D8
D5
ICM7226A, ICM7226B
19
All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation's quality certifications can be viewed at website www.intersil.com/design/quality/iso.asp.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli-
able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
2401 Palm Bay Rd.
Palm Bay, FL 32905
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
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Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
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8F-2, 96, Sec. 1, Chien-kuo North,
Taipei, Taiwan 104
Republic of China
TEL: 886-2-2515-8508
FAX: 886-2-2515-8369
ICM7226A, ICM7226B
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