CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

8-Digit, Microprocessor-Compatible, LED

Display Decoder Driver

The Intersil ICM7228 display driver interfaces
microprocessors to an 8-digit, 7-segment, numeric LED
display. Included on chip are two types of 7-segment
decoder, multiplex scan circuitry, LED display segment
drivers, LED display digit drivers and an 8-byte static
memory as display RAM.

Data can be written to the ICM7228A and ICM7228B's display
RAM in sequential 8-digit update or in single-digit update
format. Data is written to the ICM7228C and ICM7228D display
RAM in parallel random access format. The ICM7228A and
ICM7228C drive common anode displays. The ICM7228B and
ICM7228D drive common cathode displays. All versions can
display the RAM data as either Hexadecimal or Code B format.
The ICM7228A and ICM7228B incorporate a No Decode mode
allowing each bit of each digit's RAM word to drive individual
display segments resulting in independent control of all display
segments. As a result, bargraph and other irregular display
segments and formats can be driven directly by this chip.

The Intersil ICM7228 is an alternative to both the Maxim
ICM7218 and the Intersil ICM7218 display drivers. Notice that
the ICM7228A/B has an additional single digit access mode.
This could make the Intersil ICM7218A/B software incompatible
with ICM7228A/B operation.

Features

· Improved 2nd Source to Maxim ICM7218

· Fast Write Access Time of 200ns

· Multiple Microprocessor Compatible Versions

· Hexadecimal, Code B and No Decode Modes

· Individual Segment Control with "No Decode" Feature

· Digit and Segment Drivers On-Chip

· Non-Overlapping Digits Drive

· Common Anode and Common Cathode LED Versions

· Low Power CMOS Architecture

· Single 5V Supply

Applications

· Instrumentation

· Test Equipment

· Hand Held Instruments

· Bargraph Displays

· Numeric and Non-Numeric Panel Displays

· High and Low Temperature Environments where LCD

Display Integrity is Compromised

Ordering Information

PART NUMBER

DATA ENTRY PROTOCOL

DISPLAY TYPE

TEMP. RANGE (

PACKAGE

PKG. NO.

ICM7228AIPI

Sequential

Common Anode

-40 to 85

28 Ld PDIP

E28.6

ICM7228BIPI

Sequential

Common Cathode

-40 to 85

28 Ld PDIP

E28.6

ICM7228CIPI

Random

Common Anode

-40 to 85

28 Ld PDIP

E28.6

ICM7228DIPI

Random

Common Cathode

-40 to 85

28 Ld PDIP

E28.6

ICM7228AIJI

Sequential

Common Anode

-40 to 85

28 Ld CERDIP

F28.6

ICM7228AIBI

Sequential

Common Anode

-40 to 85

28 Ld SOIC

M28.3

ICM7228BIBI

Sequential

Common Cathode

-40 to 85

28 Ld SOlC

M28.3

ICM7228CIBI

Random

Common Anode

-40 to 85

28 Ld SOlC

M28.3

FN3160.4

Data Sheet

July 2003

ICM7228

ICM7228

Pinouts

ICM7228A

(CERDIP, PDIP, SOIC)

COMMON ANODE

TOP VIEW

ICM7228B

(CERDIP, PDIP, SOIC)

COMMON CATHODE

TOP VIEW

ICM7228C

(CERDIP, PDIP, SOIC)

COMMON ANODE

TOP VIEW

ICM7228D

(CERDIP, PDIP, SOIC)

COMMON CATHODE

TOP VIEW

SEG c

SEG e

SEG b

ID6 (HEXA/CODE B)

ID5 (DECODE)

ID7 (DATA COMING)

WRITE

MODE

ID4 (SHUTDOWN)

ID1

ID0

ID2

ID3

SEG g

SEG d

SEG f

DIGIT 3

DIGIT 7

DIGIT 8

DIGIT 5

DIGIT 2

DIGIT 1

SEG a

DIGIT 6

DIGIT 4

DIGIT 6

DIGIT 3

DIGIT 1

ID6 (HEXA/CODE B)

ID5 (DECODE)

ID7 (DATA COMING)

WRITE

MODE

ID4 (SHUTDOWN)

ID1

ID0

ID2

ID3

DIGIT 5

DIGIT 2

DIGIT 8

SEG g

SEG e

SEG d

SEG b

SEG a

DIGIT 7

SEG f

SEG c

SEG e

SEG b

DA0 (DIGIT ADDRESS 0)

DA1 (DIGIT ADDRESS 1)

ID7 (INPUT DP)

WRITE

HEXA/CODE B/SHUTDOWN

DA2 (DIGIT ADDRESS 2)

ID1

ID0

ID2

ID3

SEG g

SEG d

SEG f

DIGIT 3

DIGIT 7

DIGIT 8

DIGIT 5

DIGIT 2

DIGIT 1

SEG a

DIGIT 6

DIGIT 4

DIGIT 6

DIGIT 3

DIGIT 1

DA0 (DIGIT ADDRESS 0)

DA1 (DIGIT ADDRESS 1)

ID7 (INPUT DP)

WRITE

HEXA/CODE B/SHUTDOWN

DA2 (DIGIT ADDRESS 2)

ID1

ID0

ID2

ID3

DIGIT 5

DIGIT 2

DIGIT 8

SEG g

SEG e

SEG d

SEG b

SEG a

DIGIT 7

SEG f

SEG c

ICM7228

Functional Block Diagram

8 SEGMENT

DRIVERS

8 DIGIT

DRIVERS

DECODE

NO-DECODE

8-BYTE
STATIC

RAM

HEXADECIMAL/

CODE B

DECODER

MULTIPLEX

OSCILLATOR

WRITE ADDRESS

COUNTER

CONTROL

LOGIC

READ

ADDRESS, DIGIT

MULTIPLEXER

ICM7228A, ICM7228B

ID0 - ID7

INPUT

DATA

ID4 - ID7

CONTROL

INPUTS

MODE

WRITE

SHUTDOWN

HEXA/CODE B

DECODE

INTERDIGIT
BLANKING

DECIMAL
POINT

8 SEGMENT

DRIVERS

8 DIGIT

DRIVERS

8-BYTE
STATIC

RAM

HEXADECIMAL/

CODE B

DECODER

MULTIPLEX

OSCILLATOR

WRITE ADDRESS

COUNTER

THREE LEVEL

INPUT LOGIC

READ

ADDRESS

MULTIPLEXER

ICM7228C, ICM7228D

WRITE

SHUTDOWN

INTERDIGIT
BLANKING

DECIMAL
POINT

DA0 - DA2

DIGIT

ADDRESS

ID0 - ID3

ID7

DATA INPUT

HEXADECIMAL/

CODE B/

SHUTDOWN

ICM7228

Absolute Maximum Ratings

Thermal Information

Supply Voltage (V

- V

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V

Digit Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA
Segment Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Input Voltage (Note 1) (Any Terminal) . . (V

-0.3V)<V

<(V

+0.3V)

Operating Conditions

Operating Temperature Range

IPI, IJI, IBI Suffix. . . . . . . . . . . . . . . . . . . . . . . . . . . -40

C to 85

Thermal Resistance (Typical, Note 2)

(

C/W)

(

C/W)

CERDIP Package. . . . . . . . . . . . . . . . .

PDIP Package . . . . . . . . . . . . . . . . . . .

N/A

SOIC Package . . . . . . . . . . . . . . . . . . .

N/A

Maximum Junction Temperature

IPI, IBI Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

IJI Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

Maximum Storage Temperature Range . . . . . . . . . -65

C to 150

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to a voltage greater than V

or less then V

may cause destructive device latchup. For this reason, it is recommended that no inputs row sources operating on a different

power supply be applied to the device before its own supply is established, and when using multiple supply systems the supply to the ICM7228
should be turned on first.

is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief 379 for details.

Electrical Specifications

= +5.0V ±10%, V

= 0V, Unless Otherwise Specified INDUSTRIAL TEMPERATURE RANGE, IPI, IJI,

IBI DEVICES

PARAMETER

TEST CONDITIONS

= 25

-40

C TO 85

UNITS

MIN

TYP

MAX

MIN

TYP

MAX

Supply Voltage Range, V

SUPPLY

Operating

Power Down Mode

Quiescent Supply Current, I

Shutdown, ICM7228A, IMC7228B

100

Shutdown, 7228C, 7228D

2.5

100

2.5

100

Operating Supply Current, I

Common Anode, ICM7228A/C
Segments = ON; Outputs = OPEN

200

450

200

450

Common Anode, ICM7228A/C
Segments = OFF; Outputs = OPEN

100

450

100

450

Common Cathode, ICM7228B/D
Segments = ON; Outputs = OPEN

250

450

250

450

Common Cathode, ICM7228B/D
Segments = OFF; Outputs = OPEN

175

450

175

450

Digit Drive Current, I

DIG

Common Anode, ICM7228A/C
V

OUT

= V

- 2.0V

200

175

Common Cathode, ICM7228B/D
V

OUT

= V

+ 1.0V

Digit Leakage Current, I

DLK

Shutdown Mode, V

OUT

= 2.0V

Common Anode, ICM7228A/C

100

Shutdown Mode, V

OUT

= 5.0V

Common Cathode, 7228B/D

100

Peak Segment Drive Current, I

SEG

Common Anode, ICM7228A/C
V

OUT

= V

+ 1.0V

Common Cathode, 7228B/D
V

OUT

= V

- 2.0V

Segment Leakage Current, I

SLK

Shutdown Mode, V

OUT

= V

Common Anode, ICM7228A/C

Shutdown Mode, V

OUT

= V

Common Cathode, ICM7228B/D

ICM7228

Input Leakage Current, I

All Inputs Except Pin 9
ICM7228C, ICM7228D V

= V

All Inputs Except Pin 9
ICM7228C, ICM7228D V

= 5.0V

-1

Display Scan Rate, f

MUX

Per Digit

390

Inter-Digit Blanking Time, t

IDB

Logical "1" Input Voltage, V

INH

Three Level Input: Pin 9
ICM7228C, ICM7228D Hexadecimal
V

= 5V

4.2

Floating Input, V

INF

Three Level Input: Pin 9
ICM7228C, ICM7228D Code B
V

= 5V

2.0

3.0

2.0

3.0

Logical "0" Input Voltage, V

INL

Three Level Input: Pin 9
ICM7228C, ICM7228D Shutdown
V

= 5V

0.8

Three Level Input Impedance, Z

= 5V

Pin 9 of ICM7228C and ICM7228D

Logical "1" Input Voltage, V

All Inputs Except
Pin 9 of ICM7228C, ICM7228D
V

= 5V

2.0

Logical "0" Input Voltage, V

All Inputs Except
Pin 9 of ICM7228C, ICM7228D
V

= 5V

0.8

SWITCHING SPECIFICATIONS V

= +5.0V

10%, V

= 0V, V

= +0.4V, V

= +2.4V

Write Pulsewidth (Low), t

200

100

250

Write Pulsewidth (High), t

850

540

1200

Mode Hold Time, t

ICM7228A, ICM7228B

-65

Mode Setup Time, t

ICM7228A, ICM7228B

250

150

250

Data Setup Time, t

250

160

250

Data Hold Time, t

-60

Digit Address Setup Time, t

ICM7228C, ICM7228D

250

110

250

Digit Address Hold Time, t

ICM7228C, ICM7228D

-60

Electrical Specifications

= +5.0V ±10%, V

= 0V, Unless Otherwise Specified INDUSTRIAL TEMPERATURE RANGE, IPI, IJI,

IBI DEVICES (Continued)

PARAMETER

TEST CONDITIONS

= 25

-40

C TO 85

UNITS

MIN

TYP

MAX

MIN

TYP

MAX

ICM7228

Typical Performance Curves

FIGURE 5. COMMON ANODE DIGIT DRIVER I

DIG

vs (V

- V

DIG

)

FIGURE 6. COMMON ANODE SEGMENT DRIVER I

SEG

vs V

SEG

FIGURE 7. COMMON CATHODE DIGIT DRIVER I

DIG

vs V

DIG

FIGURE 8. COMMON CATHODE SEGMENT DRIVER I

SEG

- V

SEG

)

TABLE 1. ICM7228A PIN ASSIGNMENTS AND DESCRIPTIONS

PIN NO.

NAME

FUNCTION

DESCRIPTION

SEG c

Output

LED Display Segments c, e, b and Decimal Point Drive Lines.

SEG e

SEG b

ID6,
(HEXA/CODE B)

Input

When "MODE" Low: Display Data Input, Bit 7.
When "MODE" High: Control Bit, Decoding Scheme Selection: High, Hexadecimal Decoding;
Low, Code B Decoding.

ID5, (DECODE)

Input

When "MODE" Low: Display Data Input, Bit 6.
When "MODE" High: Control Bit, Decode/No Decode Selection: High, No Decode; Low, Decode.

ID7,
(DATA COMING)

Input

When "MODE" Low: Display Data Input, Bit 8, Decimal Point Data.
When "MODE" High: Control Bit, Sequential Data Update Select: High, Data Coming; Low, No
Data Coming.

WRITE

Input

Data Input Will Be Written to Control Register or Display RAM on Rising Edge of WRITE.

-V

DIG

(V)

(mA)

100

200

300

400

500

1.0

2.0

3.0

4.0

5.0

-55

125

-55

125

SEG

(V)

(mA)

1.0

2.0

3.0

4.0

5.0

-55

125

DIG

(V)

DIG

)

300

200

100

1.0

2.0

3.0

4.0

5.0

-55

125

-V

SEG

(V)

1.0

2.0

3.0

4.0

5.0

SEG

(mA)

-55

125

ICM7228

MODE

Input

Selects Data to Be Loaded to Control Register or Display RAM: High, Loads Control Register;
Low, Loads Display RAM.

ID4,
(SHUTDOWN)

Input

When "MODE" Low: Display Data Input, Bit 5.
When "MODE" High: Control Bit, Low Power Mode Select: High, Normal Operation; Low,
Oscillator and Display Disabled.

ID1

Input

When "MODE" Low: Display Data Input, Bit 2.
When "MODE" High and "ID7 (DATA COMING)" Low: Digit Address, Bit 2, Single Digit Update
Mode.

ID0

Input

When "MODE" Low: Display Data Input, Bit 1.
When "MODE" High and "ID7 (DATA COMING)" Low: Digit Address, LSB, Single Digit Update
Mode.

ID2

Input

When "MODE" Low: Display Data Input, Bit 3.
When "MODE" High and "ID7 (DATA COMING)" Low: Digit Address, MSB, Single Digit Update
Mode.

ID3

Input

When "MODE" Low: Display Data Input, Bit 4.
When "MODE" High: RAM Bank Select (Decode Modes Only): High, RAM Bank A; Low, RAM
Bank B

DIGIT 1

Output

LED Display Digits 1, 2, 5 and 8 Drive Lines.

DlGlT 2

DIGIT 5

DlGlT 8

Supply

Device Positive Power Supply Rail.

DIGIT 4

Output

LED Display Digits 4, 7, 6 and 3 Drive Lines.

DlGlT 7

DlGlT 6

DIGlT 3

SEG f

Output

LED Display Segments f, d, g and a Drive Lines.

SEG d

SEG g

SEG a

Supply

Device Ground or Negative Power Supply Rail.

TABLE 2. ICM7228B PIN ASSIGNMENTS AND DESCRIPTIONS

PIN NO.

NAME

FUNCTION

DESCRIPTION

DIGIT 4

Output

LED Display Digits 4, 6, 3 and 1 Drive Lines.

DlGlT 6

DIGIT 3

DlGlT 1

ID6,
(HEXA/CODE B)

Input

When "MODE" Low: Display Data Input, Bit 7.
When "MODE" High: Control Bit, Decoding Scheme Selection: High, Hexadecimal
Decoding; Low, Code B Decoding.

ID5, (DECODE)

Input

When "MODE" Low: Display Data Input, Bit 6.
When "MODE" High: Control Bit, Decode/No Decode Selection: High, No Decode; Low, Decode.

ID7,
(DATA COMING)

Input

When "MODE" Low: Display Data Input, Bit 8, Decimal Point Data.
When "MODE" High: Control Bit, Sequential Data Update Select: High, Data Coming; Low, No
Data Coming.

TABLE 1. ICM7228A PIN ASSIGNMENTS AND DESCRIPTIONS (Continued)

PIN NO.

NAME

FUNCTION

DESCRIPTION

ICM7228

WRITE

Input

Data Input Will Be Written to Control Register or Display RAM on Rising Edge of WRITE.

MODE

Input

Selects Data to Be Loaded to Control Register or Display RAM: High, Loads Control Register;
Low, Loads Display RAM.

ID4,
(SHUTDOWN)

Input

When "MODE" Low: Display Data Input, Bit 5.
When "MODE" High: Control Bit, Low Power Mode Select: High, Normal Operation; Low,
Oscillator and Display Disabled.

ID1

Input

When "MODE" Low: Display Data Input, Bit 2.
When "MODE" High and "ID7 (DATA COMING)" Low: Digit Address, Bit 2, Single Digit Update
Mode.

ID0

Input

When "MODE" Low: Display Data Input, Bit 1.
When "MODE" High and "ID7 (DATA COMING)" Low: Digit Address, LSB, Single Digit Update
Mode.

ID2

Input

When "MODE" Low: Display Data Input, Bit 3.
When "MODE" High and "ID7 (DATA COMING)" Low: Digit Address, MSB, Single Digit Update
Mode.

ID3

Input

When "MODE" Low: Display Data Input, Bit 4.
When "MODE" High: RAM Bank Select (Decode Modes Only): High, RAM Bank A; Low, RAM
Bank B.

Output

LED Display Decimal Point and Segments a, b, and d Drive Lines

SEG a

SEG b

SEG d

Supply

Device Positive Power Supply Rail.

SEG c

Output

LED Display Segments c, e, f and g Drive Lines.

SEG e

SEG f

SEG g

DIGIT 8

Output

LED Display Digits 8, 2, 5 and 7 Drive Lines.

DIGIT 2

DIGIT 5

DIGIT 7

Supply

Device Ground or Negative Power Supply Rail.

TABLE 3. ICM7228C PIN ASSIGNMENTS AND DESCRIPTIONS

PIN NO.

NAME

FUNCTION

DESCRIPTION

SEG c

Output

LED Display Segments c, e, band Decimal Point Drive Lines.

SEG e

SEG b

DA0

Input

Digit Address Input, Bit 1 LSB.

DA1

Input

Digit Address Input, Bit 2.

ID7,
(INPUT DP)

Input

Display Decimal Point Data Input, Negative True.

WRITE

Input

Data Input Will Be Written to Display RAM on Rising Edge of WRITE.

TABLE 2. ICM7228B PIN ASSIGNMENTS AND DESCRIPTIONS (Continued)

PIN NO.

NAME

FUNCTION

DESCRIPTION

ICM7228

HEXA/CODE
B/SHUTDOWN

Input

Three Level Input. Display Function Control: High, Hexadecimal Decoding; Float, Code B
Decoding; Low, Oscillator, and Display Disabled.

DA2

Input

Digit Address Input, Bit 3, MSB.

ID1

Input

Display Data Inputs.

ID0

ID2

ID3

DIGIT 1

Output

LED Display Digits 1, 2, 5 and 8 Drive Lines.

DlGlT 2

DIGIT 5

DlGlT 8

Supply

Device Positive Power Supply Rail.

DIGIT 4

Output

LED Display Digits 4, 7, 6 and 3 Drive Lines.

DlGlT 7

DlGlT 6

DIGlT 3

SEG f

Output

LED Display Segments f, d, g and a Drive Lines.

SEG d

SEG g

SEG a

Supply

Device Ground or Negative Power Supply Rail.

TABLE 4. ICM7228D PIN ASSIGNMENTS AND DESCRIPTIONS

PIN NO.

NAME

FUNCTION

DESCRIPTION

DIGIT 4

Output

LED Display Digits 4, 6, 3 and 1 Drive Lines.

DlGlT 6

DIGIT 3

DlGlT 1

DA0

Input

Digit Address Input, Bit 1 LSB.

DA1

Input

Digit Address Input, Bit 2.

ID7, (INPUT DP)

Input

Display Decimal Point Data Input, Negative True.

WRITE

Input

Data Input Will Be Written to Display RAM on Rising Edge of WRITE.

HEXA/CODE
B/SHUTDOWN

Input

Three Level Input. Display Function Control: High, Hexadecimal Decoding; Float, Code B
Decoding; Low, Oscillator and Display Disabled.

DA2

Input

Digit Address Input, Bit 3, MSB.

ID1

Input

Display Data Inputs.

ID0

ID2

ID3

Output

LED Display Decimal Point and Segments a, b, and d Drive Lines.

SEG a

SEG b

SEG d

Supply

Device Positive Power Supply Rail.

TABLE 3. ICM7228C PIN ASSIGNMENTS AND DESCRIPTIONS (Continued)

PIN NO.

NAME

FUNCTION

DESCRIPTION

ICM7228

Detailed Description

System Interfacing and Data Entry Modes,
ICM7228A and ICM7228B

The ICM7228A/B devices are compatible with the
architectures of most microprocessor systems. Their fast
switching characteristics makes it possible to access them as
a memory mapped I/O device with no wait state necessary in
most microcontroller systems. All the ICM7228A/B inputs,
including MODE, feature a 250ns minimum setup and 0ns
hold time with a 200ns minimum WRITE pulse. Input logic
levels are TTL and CMOS compatible. Figure 9 shows a
generic method of driving the ICM7228A/B from a
microprocessor bus. To the microprocessor, each device
appears to be 2 separate I/O locations; the Control Register
and the Display RAM. Selection between the two is
accomplished by the MODE input driven by address line A0.
Input data is placed on the lD0 - lD7 lines. The WRITE input
acts as both a device select and write cycle timing pulse. See
Figure 1 and Switching Specifications Table for write cycle
timing parameters.
The ICM7228A/B have three data entry modes: Control
Register update without RAM update, sequential 8-digit
update and single digit update. In all three modes a control
word is first written by pulsing the WRITE input while the
MODE input is high, thereby latching data into the Control
Register. The logic level of individual bits in the Control
Register select Shutdown, Decode/No Decode, Hex/Code B,
RAM bank A/B and Display RAM digit address as shown in
Tables 1 and 2.
The ICM7228A/B Display RAM is divided into 2 banks, called
bank A and B. When using the Hexadecimal or code B display
modes, these RAM banks can be selected separately. This
allows two separate sets of display data to be stored and
displayed alternately. Notice that the RAM bank selection is not
possible in No-Decode mode, this is because the display data
in the No-Decode mode has 8 bits, but in Decoded schemes
(Hex/Code B) is only 4 bits (lD0 - lD3 data). It should also be
mentioned that the decimal point is independent of selected
bank, a turned on decimal point will remain on for either bank.
Selection of the RAM banks is controlled by lD3 input. The lD3

logic level (during Control Register update) selects which bank
of the internal RAM to be written to and/or displayed.

Control Register Update without RAM Update

The Control Register can be updated without changing the
display data by a single pulse on the WRITE input, with MODE
high and DATA COMING low. If the display is being decoded
(Hex/Code B), then the value of lD3 determines which RAM
bank will be selected and displayed for all eight digits.

Sequential 8-Digit Update

The logic state of DATA COMING (lD7) is also latched
during a Control Register update. If the latched value of
DATA COMING (lD7) is high, the display becomes blanked
and a sequential 8-digit update is initiated. Display data can
now be written into RAM with 8 successive WRITE pulses,
starting with digit 1 and ending with digit 8 (See Figure 2).
After all 8 RAM locations have been written to, the display
turns on again and the new data is displayed. Additional
write pulses are ignored until a new Control Register update
is performed. All 8 digits are displayed in the format
(Hex/Code B or No Decode) specified by the control word
that preceded the 8 digit update. If a decoding scheme
(Hex/Code B) is to be used, the value of lD3 during the
control word update determines which RAM bank will be
written to.

Single Digit Update

In this mode each digit data in the display RAM can be updated
individually without changing the other display data. First, with
MODE input high, a control word is written to the Control
Register carrying the following information; DATA COMING
(lD7) low, the desired display format data on lD4 - lD6, the RAM
bank selected by lD3 (if decoding is selected) and the address
of the digit to be updated on data lines lD0 - lD2 (See Table 5).
A second write to the ICM7228A/B, this time with MODE input
low, transfers the data at the lD0 - lD7 inputs into the selected
digit's RAM location. In single digit update mode, each
individual digit's data can be specified independently for being
displayed in Decoded or No-Decode mode. For those digits
which decoding scheme (Hex/Code B) is selected, only one
can be effective at a time. Whenever a control word is written,
the specified decoding scheme will be applied to all those digits
which selected to be displayed in Decoded mode.

SEG c

Output

LED Display Segments c, e, f and g Drive Lines.

SEG e

SEG f

SEG g

DIGIT 8

Output

LED Display Digits 8, 2, 5 and 7 Drive Lines.

DIGIT 2

DIGIT 5

DIGIT 7

Supply

Device Ground or Negative Power Supply Rail.

TABLE 4. ICM7228D PIN ASSIGNMENTS AND DESCRIPTIONS (Continued)

PIN NO.

NAME

FUNCTION

DESCRIPTION

ICM7228

System Interfacing, ICM7228C and ICM7228D

The ICM7228C/D devices are directly compatible with the
architecture of most microprocessor systems. Their fast
switching characteristics make it possible to access them as a
memory mapped I/O device with no wait state necessary in
most microcontroller systems. All the ICM7228C/D inputs,
excluding HEXA/CODE B/SHUTDOWN, feature a 250ns
minimum setup and 0ns hold time with a 200ns minimum
WRITE pulse. Input logic levels are TTL and CMOS
compatible. Figure 10 shows a generic method of driving the
ICM7228C/D from a microprocessor bus. To the
microprocessor, the 8 bytes of the Display RAM appear to be
8 separate I/O locations. Loading the ICM7228C/D is quite
similar to a standard memory write cycle. The address of the
digit to be updated is placed on lines DA0 - DA2, the data to
be written is placed on lines ID0 - lD3 and ID7, then a low
pulse on WRITE input will transfer the data in. See Figure 3
and Switching Characteristics Table for write cycle timing
parameters.

The ICM7228C/D devices do not have any control register, and
also they do not provide the No Decode display format.
Hexadecimal or Code B character selection and shutdown
mode are directly controlled through the three level input at

Pin 9, which is accordingly called HEXA/CODE
B/SHUTDOWN. See Tables 3 and 4 for input and output
definitions of the ICM7228C/D devices.

Display Formats

The ICM7228A and ICM7228B have three possible display
formats; Hexadecimal, Code B and No Decode. Table 6
shows the character sets for the decode modes and their
corresponding input code.

The display formats of the ICM7228A/B are selected by
writing data to bits ID4, ID5 and ID6 of the Control Register
(See Table 1 and 2 for input Definitions). Hexadecimal and
Code B data is entered via ID0-lD3 and ID7 controls the
decimal point.

I/O OR
MEMORY
WRITE PULSE

DECODER
ENABLE

ADDRESS

DECODER

ID0

ID7 INTERSIL

ICM7228A/B

SEGMENTS

DRIVE

WRITE

MODE

DIGITS

DRIVE

DEVICE SELECT

AND

WRITE PULSE

LED DISPLAY

ADDRESS BUS A0 - A15

A1-A15

DATA BUS D0-D7

D0 - D7

MIC

OPROCESS

OR SYS

TEM

FIGURE 9. ICM7228A/B MICROPROCESSOR SYSTEM INTERFACING

TABLE 5. DIGITS ADDRESS, ICM7228A/B

INPUT DATA LINES

SELECTED DIGIT

1D2

lD2

lD0

DlGlT 1

DlGlT 2

DIGlT 3

DlGlT 4

DIGIT 5

DlGlT 6

DlGlT 7

DlGlT 8

TABLE 6. DISPLAY CHARACTER SETS

INPUT DATA CODE

DISPLAY CHARACTERS

ID3

ID2

ID1

ID0

HEXADECIMAL

CODE B

(Blank)

ICM7228

The No Decode mode of the ICM7228A and ICM7228B
allows the direct segment-by-segment control of all 64
segments driven by the device. In the No Decode mode, the
input data directly control the outputs as shown in Table 7.

An input high level turns on the respective segment, except
for the decimal point, which is turned on by an input low level
on ID7.

The No Decode mode can be used in different applications
such as bar graph or status panel driving where each
segment controls an individual LED.

The ICM7228C and ICM7228D have only the Hexadecimal
and Code B character sets. The HEXA/CODE
B/SHUTDOWN input, pin 9, requires a three level input. Pin
9 selects the Hexadecimal format when pulled high, the
Code B format when floating or driven to mid-supply, and the
shutdown mode when pulled low (See Tables 3 and 4).
Table 6 also applies to the ICM7228C/D devices.

Shutdown and Display Banking

When shutdown, the ICM7228 enters a low power standby
mode typically consuming only 1

A of supply current for the

ICM7228A/B and 2.5

A for the ICM7228C/D. In this mode

the ICM7228 turns off the multiplex scan oscillator as well as
the digit and segment drivers. However, input data can still
be entered when in the shutdown mode. Data is retained in
memory even with the supply voltage as low as 2V.

The ICM7228A/B is shutdown by writing a control word with
Shutdown (lD4) low. The ICM7228C/D is put into shutdown
mode by driving pin 9, HEXA/CODE B/SHUTDOWN, low.

The ICM7228 operating current with the display blanked is
within 100

A - 200

A for all versions. All versions of the

ICM7228 can be blanked by writing Hex FF to all digits and
selecting Code B format. The ICM7228A and ICM7228B can
also be blanked by selecting No Decode mode and writing
Hex 80 to all digits (See Tables 6 and 7).

Common Anode Display Drivers, ICM7228A and
ICM7228C

The common anode digit and segment driver output
schematics are shown in Figure 12. The common anode digit
driver output impedance is approximately 4

. This provides a

nearly constant voltage to the display digits. Each digit has a
minimum of 200mA drive capability. The N-Channel segment
driver's output impedance of 50

limits the segment current to

approximately 25mA peak current per segment. Both the
segment and digit outputs can directly drive the display,
current limiting resistors are not required.

Individual segment current is not significantly affected by
whether other segments are on or off. This is because the
segment driver output impedance is much higher than that of
the digit driver. This feature is important in bar graph
applications where each bar graph element should have the
same brightness, independent of the number of elements being
turned on.

I/O OR
MEMORY
WRITE PULSE

DECODER
ENABLE

ADDRESS

DECODER

ID0 - ID3

INTERSIL

ICM7228C/D

SEGMENTS

DRIVE

WRITE

DA0 - DA2

DIGITS

DRIVE

A0 - A2

DEVICE SELECT

AND

WRITE PULSE

LED DISPLAY

ADDRESS BUS A0 - A15

A3 - A15

DATA BUS D0 - D7

MICRO

PROCES

SOR SYS

TEM

AND ID7

FIGURE 10. ICM7228C/D MICROPROCESSOR SYSTEM INTERFACING

TABLE 7. NO DECODE SEGMENT LOCATIONS

DATA

INPUT

ID7

ID6 ID5 ID4 ID3 ID2 ID1 ID0

Controlled

Segment

Decimal

Point

FIGURE 11. DIGITS SEGMENT ASSIGNMENTS

ICM7228

Common Cathode Display Drivers, ICM7228B and
ICM7228D

The common cathode digit and segment driver output
schematics are shown in Figure 13. The N-channel digit
drivers have an output impedance of approximately 15

Each digit has a minimum of 50mA drive capability. The
segment drivers have an output impedance of approximately
100

with typically 10mA peak current drive for each

segment. The common cathode display driver output
currents are only

of the common anode display driver

currents. Therefore, the ICM7228A and ICM7228C common
anode display drivers are recommended for those
applications where high display brightness is desired. The
ICM7228B and ICM7228D common cathode display drivers
are suitable for driving bubble-lensed monolithic 7 segment
displays. They can also drive individual LED displays up to
0.3 inches in height when high brightness is not required.

Display Multiplexing

Each digit of the ICM7228 is on for approximately 320

with a multiplexing frequency of approximately 390Hz. The
ICM7228 display drivers provide interdigit blanking. This
ensures that the segment information of the previous digit is
gone and the information of the next digit is stable before the
next digit is driven on. This is necessary to eliminate display
ghosting (a faint display of data from previous digit
superimposed on the next digit). The interdigit blanking time
is 10

s typical with a guaranteed 2

s minimum. The

ICM7228 turns off both the digit drivers and the segment
drivers during the interdigit blanking period. The digit
multiplexing sequence is: D2, D5, D1, D7, D8, D6, D4 and
D3. A typical digit's drive pulses are shown on Figure 4.

Due to the display multiplexing, the driving duty cycle for
each digit is 12% (100 x

) This means the average current

for each segment is

of its peak current. This must be

considered while designing and selecting the displays.

Driving Larger Displays

If very high display brightness is desired, the ICM7228
display driver outputs can be externally buffered. Figures 14
thru 16 show how to drive either common anode or common
cathode displays using the ICM7228 and external driver
circuit for higher current displays.

Another method of increasing display currents is to connect
two digit outputs together and load the same data into both
digits. This drives the display with the same peak current,
but the average current doubles because each digit of the
display is on for twice as long, i.e.,

duty cycle versus

DIGIT

STROBE

INTERDIGIT

BLANKING

SHUTDOWN

200mA

COMMON
ANODE
DIGIT
OUTPUT

NOTE: When SHUTDOWN goes low INTERDIGIT BLANKING also
stays low.

FIGURE 12A. DIGIT DRIVER

SEGMENT

DATA

INTERDIGIT

BLANKING

SHUTDOWN

COMMON
ANODE
SEGMENT
OUTPUT

FIGURE 12B. SEGMENT DRIVER

FIGURE 12. COMMON ANODE DISPLAY DRIVERS

DIGIT

STROBE

INTERDIGIT

BLANKING

SHUTDOWN

COMMON
CATHODE
DIGIT
OUTPUT

FIGURE 13A. DIGIT DRIVER

ICM7228

Three Level Input, ICM7228C and ICM7228D

As mentioned before, pin 9 is a three level input and controls
three functions: Hexadecimal display decoding, Code B
display decoding and shutdown mode. In many applications,
pin 9 will be left open or permanently wired to one state. When
pin 9 can not be permanently left in one state, the circuits
illustrated in Figure 17 can be used to drive this three level
input.

SEGMENT

DATA

INTERDIGIT

BLANKING

SHUTDOWN

200mA

COMMON
CATHODE
SEGMENT
OUTPUT

100

NOTE: When SHUTDOWN goes low INTERDIGIT BLANKING also
stays low.

FIGURE 13B. SEGMENT DRIVER

FIGURE 13. COMMON CATHODE DISPLAY DRIVERS

ICM7228A/B

SEGMENT

OUTPUT

DIGIT

OUTPUT

UP TO

10K

FIGURE 14. DRIVING HIGH CURRENT DISPLAY, COMMON

ANODE ICM7228A/C TO COMMON ANODE

ICM7228C/D

100

SEGMENT

OUTPUT

DIGIT

OUTPUT

2N6034

(100mA

PEAK

)

2N2219

1.4A

PEAK

14mA

FIGURE 15. DRIVING HIGH CURRENT DISPLAY, COMMON

CATHODE ICM7228B/D TO COMMON CATHODE
DISPLAY

ICM7228C/D

100

SEGMENT

OUTPUT

300

DIGIT

OUTPUT

2N2219

(100mA

PEAK

)

2N6034

1.4A

PEAK

FIGURE 16. DRIVING HIGH CURRENT DISPLAY, COMMON

CATHODE ICM7228B/D TO COMMON CATHODE
DISPLAY

ICM7228

Power Supply Bypassing

Connect a minimum of 47

F in parallel with 0.1

F capacitors

between V

and V

of ICM7228. These capacitors

should be placed in close proximity to the device to reduce
the power supply ripple caused by the multiplexed LED
display drive current pulses.

HIGH = HEX
LOW = SHUTDOWN

HIGH = HEX OR SHUTDOWN
LOW = CODE B

HIGH = HEX
LOW = SHUTDOWN

HIGH = HEX OR SHUTDOWN
LOW = CODE B

HIGH = CODE B
LOW = HEX

HIGH = SHUTDOWN
LOW = CODE B

HIGH = SHUTDOWN
LOW = HEX

HIGH = SHUTDOWN
LOW = CODE B

PIN 9

CD4016
CD4066

CONTROL

CD4069

1N4148

OPEN DRAIN OR OPEN
COLLECTOR OUTPUT

74C126 THREE-STATE BUFFER

FIGURE 17. ICM7228C/D PIN 9 DRIVE CIRCUITS

Test Circuits

FIGURE 18. FUNCTIONAL TEST CIRCUIT #1

ID6 (HEXA/CODE B)

ID5 (DECODE)

ID7 (DATA COMING)

WRITE

MODE

ID4 (SHUTDOWN)

ID1

ID0

ID2

ID3

d
g

a
c
e

COMMON ANODE DISPLAY

+0.1

ICM7228A

ICM7228

Dual-In-Line Plastic Packages (PDIP)

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English and

Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of

Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated in

JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions.

Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and

are measured with the leads constrained to be perpendic-

ular to datum

7. e

and e

are measured at the lead tips with the leads unconstrained.

must be zero or greater.

8. B1 maximum dimensions do not include dambar protrusions. Dambar

protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,

E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

-C-

-B-

INDEX

1 2 3

N/2

AREA

SEATING

BASE

PLANE

-C-

-A-

0.010 (0.25)

C A

B S

E28.6

(JEDEC MS-011-AB ISSUE B)

28 LEAD DUAL-IN-LINE PLASTIC PACKAGE

SYMBOL

INCHES

MILLIMETERS

NOTES

MIN

MAX

MIN

MAX

0.250

6.35

0.015

0.39

0.125

0.195

3.18

4.95

0.014

0.022

0.356

0.558

0.030

0.070

0.77

1.77

0.008

0.015

0.204

0.381

1.380

1.565

35.1

39.7

0.005

0.13

0.600

0.625

15.24

15.87

0.485

0.580

12.32

14.73

0.100 BSC

2.54 BSC

0.600 BSC

15.24 BSC

0.700

17.78

0.115

0.200

2.93

5.08

Rev. 1 12/00

ICM7228

Ceramic Dual-In-Line Frit Seal Packages (CERDIP)

NOTES:

1. Index area: A notch or a pin one identification mark shall be locat-

ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer's identification shall not be used
as a pin one identification mark.

2. The maximum limits of lead dimensions b and c or M shall be

measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.

3. Dimensions b1 and c1 apply to lead base metal only. Dimension

M applies to lead plating and finish thickness.

4. Corner leads (1, N, N/2, and N/2+1) may be configured with a

partial lead paddle. For this configuration dimension b3 replaces
dimension b2.

5. This dimension allows for off-center lid, meniscus, and glass

overrun.

6. Dimension Q shall be measured from the seating plane to the

base plane.

7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

10. Controlling dimension: INCH.

bbb

C A - B

SEATING

BASE

PLANE

-D-

-A-

-C-

-B-

(c)

(b)

SECTION A-A

BASE

LEAD FINISH

METAL

A/2

ccc

C A - B

aaa

C A - B

F28.6

MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURATION A)

28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

SYMBOL

INCHES

MILLIMETERS

NOTES

MIN

MAX

MIN

MAX

0.232

5.92

0.014

0.026

0.36

0.66

0.014

0.023

0.36

0.58

0.045

0.065

1.14

1.65

0.023

0.045

0.58

1.14

0.008

0.018

0.20

0.46

0.008

0.015

0.20

0.38

1.490

37.85

0.500

0.610

12.70

15.49

0.100 BSC

2.54 BSC

0.600 BSC

15.24 BSC

eA/2

0.300 BSC

7.62 BSC

0.125

0.200

3.18

5.08

0.015

0.060

0.38

1.52

0.005

0.13

105

aaa

0.015

0.38

bbb

0.030

0.76

ccc

0.010

0.25

0.0015

0.038

2, 3

Rev. 0 4/94

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

ICM7228

Small Outline Plastic Packages (SOIC)

NOTES:

1. Symbols are defined in the "MO Series Symbol List" in Section 2.2

of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension "D" does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.

4. Dimension "E" does not include interlead flash or protrusions. In-

terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

6. "L" is the length of terminal for soldering to a substrate.
7. "N" is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width "B", as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are not necessarily exact.

INDEX

AREA

-B-

0.25(0.010)

C A

B S

-A-

-C-

SEATING PLANE

0.10(0.004)

h x 45

0.25(0.010)

M28.3

(JEDEC MS-013-AE ISSUE C)

28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

SYMBOL

INCHES

MILLIMETERS

NOTES

MIN

MAX

MIN

MAX

0.0926

0.1043

2.35

2.65

0.0040

0.0118

0.10

0.30

0.013

0.0200

0.33

0.51

0.0091

0.0125

0.23

0.32

0.6969

0.7125

17.70

18.10

0.2914

0.2992

7.40

7.60

0.05 BSC

1.27 BSC

0.394

0.419

10.00

10.65

0.01

0.029

0.25

0.75

0.016

0.050

0.40

1.27

Rev. 0 12/93

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