9-21

August 1997

ICM7243

8-Character, Microprocessor-

Compatible, LED Display Decoder Driver

Features

· 14-Segment and 16-Segment Fonts with Decimal Point

· Mask Programmable for Other Font-Sets Up to 64

Characters

· Microprocessor Compatible

· Directly Drives LED Common Cathode Displays

· Cascadable Without Additional Hardware

· Standby Feature Turns Display Off; Puts Chip in Low

Power Mode

· Sequential Entry or Random Entry of Data Into

Display

· Single +5V Operation

· Character and Segment Drivers, All MUX Scan

Circuitry, 8 x 6 Static Memory and 64-Character ASCll
Font Generator Included On-Chip

Description

The ICM7243 is an 8-character, alphanumeric display driver
and controller which provides all the circuitry required to
interface a microprocessor or digital system to a 14-segment
or 16-segment display. It is primarily intended for use in
microprocessor systems, where it minimizes hardware and
software overhead. Incorporated on-chip are a 64-character
ASClI decoder, 8 x 6 memory, high power character and
segment drivers, and the multiplex scan circuitry.

6-bit ASCll data to be displayed is written into the memory
directly from the microprocessor data bus. Data location
depends upon the selection of either

Sequential

(MODE = 1) or Random access mode (MODE = 0). In the
Sequential Access mode the first entry is stored in the
lowest location and displayed in the "left-most" character
position. Each subsequent entry is automatically stored in
the next higher location and displayed to the immediate
"right" of the previous entry. A DISPlay FULL signal is pro-
vided after 8 entries; this signal can be used for cascading
devices together. A CLeaR pin is provided to clear the mem-
ory and reset the location counter. The Random Access
mode allows the processor to select the memory address
and display digit for each input word.

The character multiplex scan runs whenever data is not
being entered. It scans the memory and CHARacter drivers,
and ensures that the decoding from memory to display is
done in the proper sequence. Intercharacter blanking is
provided to avoid display ghosting.

Ordering Information

PART NUMBER

TEMP.

RANGE (

PACKAGE

PKG.

NO.

ICM7243AIJL

-25

C to 85

40 Ld CERPDIP

F40.6

ICM7243AIPL

-25

C to 85

40 Ld PDIP

E40.6

ICM7243BIJL

-25

C to 85

40 Ld CERPDIP

F40.6

ICM7243BlPL

-25 to 85

40 Ld PDIP

E40.6

File Number

3162.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207

Intersil Corporation 1999

9-22

Pinouts

ICM7243A (16-SEGMENT CHARACTER)

(PDIP, CERDIP)

TOP VIEW

ICM7243B (14-SEGMENT CHARACTER)

(PDIP, CERDIP)

TOP VIEW

SEG

CHAR 8

CHAR 7

CHAR 6

SEG

MODE

A0/SEN

A1/CLR

A2/DISP FULL

OSC/OFF

CHAR 1

CHAR 2

CHAR 3

CHAR 4

CHAR 5

SEG

CHAR 8

CHAR 7

CHAR 6

SEG

MODE

A0/SEN

A1/CLR

A2/DISP FULL

OSC/OFF

CHAR 1

CHAR 2

CHAR 3

CHAR 4

CHAR 5

ICM7243

9-24

Absolute Maximum Ratings

Thermal Information

Supply Voltage V

- V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V

Input Voltage (Any Terminal) . . . . . . . . . . . V

+0.3V to V

-0.3V

CHARacter Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . 300mA
SEGment Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -25

C to 85

Thermal Resistance (Typical, Note 1)

(

C/W)

(

C/W)

PDIP Package . . . . . . . . . . . . . . . . . . .

N/A

CERDIP Package . . . . . . . . . . . . . . . .

Maximum Junction Temperature

CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Maximum Storage Temperature Range . . . . . . . . . .-65

C to 150

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

= 5V, V

= 0V, T

= 25

C, Unless Otherwise Specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

DC CHARACTERISTICS

Supply Voltage (V

- V

), V

SUPP

4.75

5.0

5.25

Operating Supply Current, I

SUPP

= 5.25V, 10 Segments ON, All 8 Characters

180

Quiescent Supply Current, I

STBY

SUPP

= 5.25V, OSC/OFF Pin < 0.5V, CS = V

250

Input High Voltage, V

Input Low Voltage, V

0.8

Input Current, I

-10

+10

CHARacter Drive Current, I

CHAR

SUPP

= 5V, V

OUT

= 1V

140

190

CHARacter Leakage Current, I

CHLK

100

SEGment Drive Current, I

SEG

SUPP

= 5V, V

OUT

= 2.5V

SEGment Leakage Current, I

SLK

0.01

DISPlay FULL Output Low, V

= 1.6mA

0.4

DISPlay FULL Output High, V

= 100

2.4

Display Scan Rate, f

400

Electrical Specifications

Drive levels 0.4V and 2.4V, timing measured at 0.8V and 2.0V. V

= 5V, T

= 25

C, Unless Otherwise

Specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

AC CHARACTERISTICS

WR, CLeaR Pulse Width Low, t

WPI

300

250

WR, CLeaR Pulse Width High (Note 1), t

WPH

250

Data Hold Time, t

-100

Data Setup Time, t

250

150

Address Hold Time, t

125

Address Setup Time, t

CS, CS Setup Time, t

Pulse Transition Time, t

100

SEN Setup Time, t

SEN

-25

Display Full Delay, t

WDF

700

480

Capacitance

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Input Capacitance, C

(Note 2)

Output Capacitance, C

(Note 2)

NOTES:

1. In Sequential mode WR high must be

SEN

WDF

2. For design reference only, not tested.

ICM7243

9-26

Performance Curves

FIGURE 4. SEGMENT CURRENT vs OUTPUT VOLTAGE

FIGURE 5. CHARACTER CURRENT VS OUPUT VOLTAGE

SEG

(mA)

SEGMENT VOLTAGE (V)

= 5.5V

4.5V

5.0V

CHAR

(mA)

= 5.5V

4.5V

5.0V

SEGMENT VOLTAGE (V)

100

200

300

400

500

Pin Descriptions

SIGNAL

PIN

FUNCTION

ICM7243A(B)

D0 - D5

10 - 15

(8 - 13)

Six-Bit ASCll Data input pins (active high).

CS, CS

(14 - 16)

Chip Select from

P address decoder, etc.

WRite pulse input pin (active low). For an active high write pulse, CS can be used, and WR can be
used as CS.

MODE

Selects data entry MODE. High selects Sequential Access (SA) mode where first entry is
displayed in "leftmost" character and subsequent entries appear to the "right". Low selects the
Random Access (RA) mode where data is displayed on the character addressed via A0 - A2
Address pins.

A0/SEN

In RA mode it is the LSB of the character Address. In SA mode it is used for cascading devices for
displays of more than 8 characters (active high enables device controller).

A1/CLeaR

In RA mode this is the second bit of the address. In

mode, a low input will CLeaR the Serial

Address Counter, the Data Memory and the display.

A2/DISPlay

FULL

mode this is the MSB of the Address. In

mode, the output goes high after eight entries,

indicating DISPlay FULL.

OSC/OFF

OSCillator input pin. Adding capacitance to V

will lower the internal oscillator frequency. An

external oscillator can be applied to this pin. A low at this input sets the device into a (shutdown)
mode, shutting OFF the display and oscillator but retaining data stored in memory.

SEG a - SEG m,

2 - 9, 32 - 40

(2 - 7), (32 - 40)

SEGment driver outputs.

CHARacter 1 - 8

18 - 21,

23 - 26

CHARacter driver outputs.

ICM7243

9-29

NOTE: 17 for ICM7243A, 15 for ICM7243B.

FIGURE 8. MULTICHARACTER DISPLAY USING SEQUENTIAL ACCESS MODE

FIGURE 9A. COMMON CATHODE DISPLAY

FIGURE 9B. COMMON ANODE DISPLAY

FIGURE 9. DRIVING LARGE DISPLAYS

Typical Applications

(Continued)

8-CHARACTER LED DISPLAY

CLR

+5V

SEN

MODE

D0 - D5

CHAR

SEG

DISP FULL

DATA

WR,

CS,

FIRST 8 CHARACTERS

SECOND 8 CHARACTERS

NTH 8 CHARACTERS

8-CHARACTER LED DISPLAY

+5V

CLR

SEN

MODE

D0 - D5

CHAR

SEG

DISP FULL

CLR

SEN

MODE

D0 - D5

CHAR

SEG

DISP FULL

+5V

NOTE

(CS)

BUS

(WR)

+5V

100

1mA

2N2219

(100mA

PEAK

)

CHAR

14mA

2N6034

1.4A

PEAK

GND

= 4

ICM7243

+5V

GND

SEG

+5V

100

2N2219

(100mA

PEAK

)

1.4A

PEAK

GND

= 4

ICM7243

+5V

GND

SEG

300

GND

+5V

CHAR

2N6034

ICM7243

9-32

Detailed Description

WR, CS, CS - These pins are immediately functionally
ANDed, so all actions described as occurring on an edge of
WR, with CS and CS enabled, will occur on the equivalent
(last) enabling or (first) disabling edge of any of these
inputs. The delays from CS pins are slightly (about 5ns)
greater than from WR or CS due to the additional inverter
required on the former.

MODE - The MODE pin input is latched on the falling edge
of WR (or its equivalent, see above). The location (in Data
Memory) where incoming data will be placed is determined
either from the Address pins or the Sequential Address
Counter. This is controlled by MODE input. MODE also
controls the function of A0/SEN, A1/CLR, and A2/DlSPlay
FULL lines.

Random Access Mode - When the internal mode latch is
set for Random Access (RA) (MODE latched low), the
Address input on A0, A1 and A2 will be latched by the fall-
ing edge of WR (or its equivalent). Subsequent changes on
the Address lines will not affect device operation. This
allows use of a multiplexed 6-bit bus controlling both
address and data, with timing controlled by WR.

Sequential Access Mode - If the internal latch is set for
Sequential Access (SA), (MODE latched high), the Serial
ENable input or SEN will be latched on the falling edge of
WR (or its equivalent). The CLR input is asynchronous, and
will force-clear the Sequential Address Counter to address
000 (CHARacter 1), and set all Data Memory contents to
100000 (blank) at any time. The DISPlay FULL output will
be active in SA mode to indicate the overflow status of the
Sequential Address Counter. If this output is low, and SEN
is (latched) high, the contents of the Counter will be used to
establish the Data Memory location for the Data input. The
Counter is then incremented on the rising edge of WR. If
SEN is low, or DISPlay FULL is high, no action will occur.
This allows easy "daisy-chaining" of display drivers for mul-
tiple character displays in a Sequential Access mode.

Changing Modes - Care must be exercised in any
application involving changing from one mode to another.
The change will occur only on a falling edge of WR (or its
equivalent). When changing mode from

Sequential

Access to Random Access, note that A2/DlSPlay FULL
will be an output until WR has fallen low, and an Address
drive here could cause a conflict. When changing from
Random Access to Sequential Access, A1/CLR should
be high to avoid inadvertent clearing of the Data Memory
and Sequential Address Counter. DISPlay FULL will
become active immediately after the rising edge of WR.

Data Entry - The input Data is latched on the rising edge of
WR (or its equivalent) and then stored in the Data Memory
location determined as described above. The six Data bits
can be multiplexed with the Address information on the
same lines in Random Access mode. Timing is controlled
by the WR input.

OSC/OFF - The device includes a relaxation oscillator with
an internal capacitor and a nominal frequency of 200kHz.
By adding external capacitance to V

at the OSC/OFF

pin, this frequency can be reduced as far as desired. Alter-
natively, an external signal can be injected on this pin. The
oscillator (or external) frequency is pre-divided by 64, and
then further divided by 8 in the Multiplex Counter, to drive
the CHARacter drive lines (see Figure 3). An inter-charac-
ter blanking signal is derived from the pre-divider. An addi-
tional comparator on the OSC/OFF input detects a level
lower than the relaxation oscillator's range, and blanks the
display, disables the DISPlay FULL output (if active), and
clears the pre-divider and Multiplex Counter. This puts the
circuit in a low-power-dissipation mode in which all outputs
are effectively open circuits, except for parasitic diodes to
the supply lines. Thus a display connected to the output
may be driven by another circuit (including another
ICM7243) without driver conflicts.

Display Output - The output of the Multiplex Counter is
decoded and multiplexed into the address input of the Data
Memory, except during WR operations (in Sequential
Access mode, with SEN high and DISPlay FULL low),
when it scans through the display data. The address
decoder also drives the CHARacter outputs, except during
the inter-character blanking interval (nominally about 5

s).

Each CHARacter output lasts nominally about 300

s, and

is repeated nominally every 2.5ms, i.e., at a 400Hz rate
(times are based on internal oscillator without external
capacitor).

The 6 bits read from the Data Memory are decoded in the
ROM to the 17 (15 for ICM7243B) segment signals, which
drive the SEGment outputs. Both CHARacter and SEG-
ment outputs are disabled during WR operations (with SEN
high and DISPlay FULL Low for Sequential Access
mode). The outputs may also be disabled by pulling
OSC/OFF low.

The decode pattern from 6 bits to 17 (15) segments is done
by a ROM pattern according to the ASCll font shown. Cus-
tom decode patterns can be arranged, within these limita-
tions, by consultation with the factory.

ICM7243

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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

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