4-281
March 1997
82C83H
CMOS Octal Latching Inverting Bus Driver
Features
Full 8-Bit Parallel Latching Buffer
Bipolar 8283 Compatible
Three-State Inverting Outputs
Propagation Delay . . . . . . . . . . . . . . . . . . . . . . 25ns Max
Gated Inputs
- Reduce Operating Power
- Eliminate the Need for Pull-Up Resistors
Single 5V Power Supply
Low Power Operation
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Operating Temperature Ranges
- C82C83H . . . . . . . . . . . . . . . . . . . . . . . . .0
o
C to +70
o
C
- I82C83H . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
- M82C83H . . . . . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Description
The Intersil 82C83H is a high performance CMOS Octal
Latching Buffer manufactured using a self-aligned silicon gate
CMOS process (Scaled SAJI IV). The 82C83H provides an 8-
bit parallel latch/buffer in a 20 lead pin package. The active
high strobe (STB) input allows transparent transfer of data
and latches data on the negative transition of this signal. The
active low output enable (OE) permits simple interface to
microprocessor systems. The 82C83H provides inverted data
at the outputs.
Pinouts
82C83H (PDIP, CERDIP)
TOP VIEW
82C83H (PLCC, CLCC)
TOP VIEW
Ordering Information
PART NO.
PACKAGE
TEMP RANGE
PKG. NO
CP82C83H
20 Ld PDIP
0
o
C to +70
o
C
E20.3
IP82C83H
-40
o
C to +85
o
C
E20.3
CS82C83H
20 Ld PLCC
0
o
C to +70
o
C
N20.35
IS82C83H
-40
o
C to +85
o
C
N20.35
CD82C83H
20 Ld CERDIP
0
o
C to +70
o
C
F20.3
ID82C83H
-40
o
C to +85
o
C
F20.3
MD82C83H/B
0
o
C to +70
o
C
F20.3
8406702RA
SMD#
-55
o
C to +125
o
C
F20.3
MR82C83H/B
20 Pad CLCC
-55
o
C to +125
o
C
J20.A
84067022A
SMD#
-55
o
C to +125
o
C
J20.A
TRUTH TABLE
STB
OE
DI
DO
X
H
X
HI-Z
H
L
L
H
H
L
H
L
L
X
H = Logic One
L = Logic Zero
X = Don`t Care
HI-Z = High Impedance
= Negative Transition
= Latched to Value of Last
Data
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
DI
0
DI
1
DI
2
DI
3
DI
4
DI
5
DI
7
DI
6
OE
GND
V
CC
DO
1
DO
2
DO
3
DO
0
DO
4
DO
5
DO
6
DO
7
STB
PIN NAMES
PIN
DESCRIPTION
DI
0
- DI
7
Data Input Pins
DO
0
- DO
7
Data Output Pins
STB
Active High Strobe
OE
Active Low Output Enable
19
3
2
20
1
15
16
17
18
14
9
10
11
12
13
4
5
6
7
8
DI
4
DI
5
DI
6
DI
7
DI
3
OE
GND
STB
DO
7
DO
6
DO
2
DO
3
DO
4
DO
5
DO
1
DI
2
DI
1
DI
0
V
CC
DO
0
File Number
2971.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
4-282
Functional Diagram
Gated Inputs
During normal system operation of a latch, signals on the
bus at the device inputs will become high impedance or
make transitions unrelated to the operation of the latch.
These unrelated input transitions switch the input circuitry
and typically cause an increase in power dissipation in
CMOS devices by creating a low resistance path between
V
CC
and GND when the signal is at or near the input switch-
ing threshold. Additionally, if the driving signal becomes high
impedance (``float'' condition), it could create an indetermi-
nate logic state at the inputs and cause a disruption in
device operation.
The Intersil 82C8X series of bus drivers eliminates these
conditions by turning off data inputs when data is latched
(STB = logic zero for the 82C82/83H) and when the device is
disabled (OE = logic one for the 82C86H/87H). These gated
inputs disconnect the input circuitry from the V
CC
and
ground power supply pins by turning off the upper P-channel
and lower N-channel (See Figures 1 and 2). No current flow
from V
CC
to GND occurs during input transitions and invalid
logic states from floating inputs are not transmitted. The next
stage is held to a valid logic level internal to the device.
D.C. input voltage levels can also cause an increase in ICC if
these input levels approach the minimum V
IH
or maximum
V
IL
conditions. This is due to the operation of the input cir-
cuitry in its linear operating region (partially conducting
state). The 82C8X series gated inputs mean that this condi-
tion will occur only during the time the device is in the trans-
parent mode (STB = logic one). ICC remains below the
maximum ICC standby specification of 10
A during the time
inputs are disabled, thereby greatly reducing the average
power dissipation of the 82C8X series devices.
Decoupling Capacitors
The transient current required to charge and discharge the
300pF load capacitance specified in the 82C83H data sheet
is determined by
I = C
L
(dv/dt)
Assuming that all outputs change state at the same time and
that dv/dt is constant;
where t
R
= 20ns, V
CC
= 5.0V, C
L
= 300pF on each eight out-
puts.
I = (8 x 300 x 10
-12
) x (5.0V x 0.8)/(20 x 10
-9
) = 480mA
This current spike may cause a large negative voltage spike on
V
CC
which could cause improper operation of the device. To fil-
ter out this noise, it is recommended that a 0.1
F ceramic disc
capacitor be placed between V
CC
and GND at each device,
with placement being as near to the device as possible.
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
STB
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
OE
D Q
CLK
P
P
N
N
N
P
V
CC
V
CC
INTERNAL
DATA
STB
DATA IN
FIGURE 1. 82C82/83H
N
N
P
P
P
N
V
CC
V
CC
DATA
INTERNAL
OE
DATA IN
FIGURE 2. 82C86H/87H GATED INPUTS
I
C
L
V
CC
80 percent
(
)
t
R
t
F
/
--------------------------------------------------------
=
(EQ. 1)
P
P
N
N
N
P
V
CC
V
CC
INTERNAL
DATA
STB
DATA IN
ADDRESS
ADDRESS
ALE
MULTI-
ICC
PLEXED
BUS
FIGURE 3. SYSTEM EFFECTS OF GATED INPUTS
82C83H
4-283
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND 0.5V to V
CC
+0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
C82C83H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to +70
o
C
I82C83H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
M82C83H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Thermal Resistance (Typical)
JA
o
C/W
JC
o
C/W
CERDIP Package . . . . . . . . . . . . . . . .
70
16
CLCC Package . . . . . . . . . . . . . . . . . .
80
20
PDIP Package . . . . . . . . . . . . . . . . . . .
75
N/A
PLCC Package . . . . . . . . . . . . . . . . . .
75
N/A
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65
o
C to +150
o
C
Max Junction Temperature Ceramic Package . . . . . . . . . . . . . . +175
o
C
Max Junction Temperature Plastic Package. . . . . . . . . . . . . . . . +150
o
C
Lead Temperature (Soldering 10s) (PLCC - Lead Tips Only) . . +300
o
C
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
V
CC
= 5.0V
10%; T
A
= 0
o
C to +70
o
C (C82C83H);
T
A
= -40
o
C to +85
o
C (I82C83H);
T
A
= -55
o
C to +125
o
C (M82C83H)
SYMBOL
PARAMETER
MIN
MAX
UNITS
TEST CONDITIONS
V
IH
Logical One Input Voltage
2.0
2.2
-
V
C82C83H, I82C83H,
M82C83H, (Note 1)
V
IL
Logical Zero Input Voltage
0.8
V
V
OH
Logical One Output Voltage
3.0
V
CC
-0.4V
-
V
I
OH
= -8mA,
I
OH
= -100mA, OE = GND
V
OL
Logical Zero Output Voltage
0.45
V
I
OL
= 20mA, OE = GND
I
I
Input Leakage Current
-10
10
A
V
IN
= GND or V
CC
,
DIP Pins 1-9,11
I
O
Output Leakage Current
-10
10
A
V
O
= GND or OE
V
CC
-0.5V
DIP Pins 12-19
lCCSB
Standby Power Supply Current
-
10
A
V
IN
= V
CC
or GND
V
CC
= 5.5V Outputs Open
IC COP
Operating Power Supply Current
-
1
mA/
MHz
T
A
= +25
o
C, V
CC
= 5V, Typical
(See Note 2)
NOTES:
1. V
IH
is measured by applying a pulse of magnitude = V
lHMIN
to one data Input at a time and checking the corresponding device output for
a valid logical 1 - during valid input high time. Control pins (STB, CE) are tested separately with all device data input pins at V
CC
-0.4V.
2. Typical ICCOP = 1 mA/MHz of STB cycle time. (Example: 5MHz
P, ALE = 1.25MHz, ICCOP = 1.25mA).
Capacitance
T
A
= +25
o
C
SYMBOL
PARAMETER
TYPICAL
UNITS
TEST CONDITIONS
C
IN
Input Capacitance
13
pF
FREQ = 1MHz, all measure-
ments are referenced to device
GND
C
OUT
Output Capacitance
20
pF
82C83H
4-284
AC Electrical Specifications
V
CC
= 5.0V
10%; C
L
= 300pF (Note 1), FREQ = 1MHz
T
A
= 0
o
C to +70
o
C (C82C83H);
T
A
= -40
o
C to +85
o
C (l82C83H);
T
A
= -55
o
C to +125
o
C (M82C83H)
SYMBOL
PARAMETER
LIMITS
UNITS
TEST CONDITIONS
MIN
MAX
(1) TlVOV
Propagation Delay Input to Output
5
25
ns
See Notes 2, 3
(2) TSHOV
Propagation Delay STB to Output
10
50
ns
See Notes 2, 3
(3) TEHOZ
Output Disable Time
5
22
ns
See Notes 2, 3
(4) TELOV
Output Enable Time
10
45
ns
See Notes 2, 3
(5) TlVSL
Input to STB Set Up Time
0
-
ns
See Notes 2, 3
(6) TSLIX
Input to STB Hold Time
30
-
ns
See Notes 2, 3
(7) TSHSL
STB High Time
15
-
ns
See Notes 2, 3
(8) TR, TF
Input Rise/Fall Times
-
20
ns
See Notes 2, 3
NOTES:
1. Output load capacitance is rated 300pF for both ceramic and plastic packages.
2. All AC Parameters tested as per test load circuits. Input rise and tall times are driven at 1ns/V.
3. Input test signals must switch between V
IL
-0.4V and V
lH
+0.4V.
Timing Waveforms
All Timing measurements are made at 1.5V unless otherwise noted.
FIGURE 4. TIMING WAVEFORMS
Test Load Circuits
FIGURE 5. TIVOV, TSHOV
FIGURE 6. TELOV OUTPUT HIGH ENABLE
TR, TF (8)
TIVSL (5)
TSHSL (7)
TSLIX
(6)
2.0V
0.8V
TIVOV
(1)
TEHOZ (3)
TSHOV (2)
VOH -0.1V
VOL +0.1V
TELOV (4)
3.0V
0.45V
OUTPUTS
OE
STB
INPUTS
2.27V
91
300pF
TEST
POINT
OUTPUT
(SEE NOTE)
1.5V
180
300pF
TEST
POINT
OUTPUT
(SEE NOTE)
82C83H
4-285
NOTE: Includes jig and stray capacitance.
FIGURE 7. TELOV OUTPUT LOW ENABLE
FIGURE 8. TEHOZ OUTPUT LOW/HIGH DISABLE
Burn-In Circuits
FIGURE 9. MD82C83H CERDIP
FIGURE 10. MR82C83H CLCC
NOTES:
1. V
CC
= 5.5V
0.5V GND = 0V
2. V
IH
= 4.5V
10%
3. V
IL
= -0.2 to 0.4V
4. R1 = 47kW
5%
5. R2 = 2.0kW
5%
6. R3 = 1.0kW
5%
7. R4 = 5.0kW
5%
8. C1 = 0.01
F Minimum
9. F0 = 100kHz
10%
10. F1 = F0/2, F2 = F1/2, F3 = F2/2
Test Load Circuits
(Continued)
1.5V
51
300pF
TEST
POINT
OUTPUT
(SEE NOTE)
2.27V
91
50pF
TEST
POINT
OUTPUT
(SEE NOTE)
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
F2
F2
F2
F2
F2
F2
F2
F2
F0
R1
R1
R1
R1
R1
R1
R1
R1
R1
C1
V
CC
R1
V
CC
R2
R2
A
A
A
A
A
A
A
A
A
F1
4
5
6
7
8
9
10
11 12
13
3
2
1
20 19
15
14
18
17
16
V
CC
C1
R4
R4
R4
R4
R4
R4
R4
F2
F2
F2
F2
F2
R3
R3
R4
R4
F0
F1
V
CC
R4
V
CC
R4
R4
R4
F2
F2
F2
R4
R4
R4
2
2
V
CC
2
82C83H
4-286
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Die Characteristics
DIE DIMENSIONS:
138.6 x 155.5 x 19
1 mils
METALLIZATION:
Type: Silicon - Aluminum
Thickness: 11k
2k
GLASSIVATION:
Type: SiO
2
Thickness: 8k
1k
WORST CASE CURRENT DENSITY:
2.0 x 10
5
A/cm
2
Metallization Mask Layout
82C83H
DI2
DI1
DI2
VCC
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
STB
GND
OE
DI7
DI6
DI5
DI4
DI3
82C83H
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