4-287
March 1997
82C84A
CMOS Clock Generator Driver
Features
Generates the System Clock For CMOS or NMOS
Microprocessors
Up to 25MHz Operation
Uses a Parallel Mode Crystal Circuit or External
Frequency Source
Provides Ready Synchronization
Generates System Reset Output From Schmitt Trigger
Input
TTL Compatible Inputs/Outputs
Very Low Power Consumption
Single 5V Power Supply
Operating Temperature Ranges
- C82C84A . . . . . . . . . . . . . . . . . . . . . . . . .0
o
C to +70
o
C
- I82C84A . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
- M82C84A . . . . . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Description
The Intersil 82C84A is a high performance CMOS Clock Generator-
driver which is designed to service the requirements of both CMOS
and NMOS microprocessors such as the 80C86, 80C88, 8086 and
the 8088. The chip contains a crystal controlled oscillator, a divide-by-
three counter and complete "Ready" synchronization and reset logic.
Static CMOS circuit design permits operation with an external fre-
quency source from DC to 25MHz. Crystal controlled operation to
25MHz is guaranteed with the use of a parallel, fundamental mode
crystal and two small load capacitors.
All inputs (except X1 and RES) are TTL compatible over tempera-
ture and voltage ranges.
Power consumption is a fraction of that of the equivalent bipolar cir-
cuits. This speed-power characteristic of CMOS permits the
designer to custom tailor his system design with respect to power
and/or speed requirements.
Ordering Information
PART
NUMBER
TEMP. RANGE
PACKAGE
PKG.
NO.
CP82C84A
0
o
C to +70
o
C
18 Ld PDIP
E18.3
IP82C84A
-40
o
C to +85
o
C
E18.3
CS82C84A
0
o
C to +70
o
C
20 Ld PLCC
N20.35
IS82C84A
-40
o
C to +85
o
C
N20.35
CD82C84A
0
o
C to +70
o
C
18 Ld CERDIP
F18.3
ID82C84A
-40
o
C to +85
o
C
F18.3
MD82C84A/B
-55
o
C to +125
o
C
F18.3
8406801VA
SMD#
F18.3
MR82C84A/B
-55
o
C to +125
o
C
20 Pad CLCC
J20.A
84068012A
SMD#
J20.A
Pinouts
82C84A (PDIP, CERDIP)
TOP VIEW
82C84A (PLCC, CLCC)
TOP VIEW
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1
V
CC
X2
EFI
F/C
OSC
RES
X1
GND
ASYNC
RESET
CSYNC
PCLK
RDY1
READY
RDY2
CLK
AEN1
AEN2
4
5
6
7
8
9
10
11
12
13
3
2
1
20
19
15
14
18
17
16
RDY1
AEN2
NC
READY
RDY2
NC
F/C
EFI
X2
CLK
RESET
GND
OSC
RES
V
CC
CSYNC
PCLK
X1
AEN1
ASYNC
File Number
2974.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
4-288
Functional Diagram
CONTROL PIN
LOGICAL 1
LOGICAL 0
F/C
External Clock
Crystal Drive
RES
Normal
Reset
RDY1, RDY2
Bus Ready
Bus Not Ready
AEN1, AEN2
Address Disabled
Address Enable
ASYNC
1 Stage Ready
Synchronization
2 Stage Ready
Synchronization
X1
X2
EF1
CSYNC
RDY1
RDY2
11
17
16
13
14
1
4
3
6
7
15
RESET
OSC
PCLK
CLK
READY
XTAL
OSCILLATOR
CK
D
Q
FF1
CK
D
CK
D
Q
FF2
Q
12
2
8
5
10
RES
F/C
AEN1
AEN2
ASYNC
SYNC
2
SYNC
3
82C84A
4-289
Pin Description
SYMBOL
NUMBER
TYPE
DESCRIPTION
AEN1,
AEN2
3, 7
I
ADDRESS ENABLE: AEN is an active LOW signal. AEN serves to qualify its respective Bus
Ready Signal (RDY1 or RDY2). AEN1 validates RDY1 while AEN2 validates RDY2. Two AEN
signal inputs are useful in system configurations which permit the processor to access two Multi-
Master System Busses. In non-Multi-Master configurations, the AEN signal inputs are tied true
(LOW).
RDY1,
RDY2
4, 6
I
BUS READY (Transfer Complete). RDY is an active HIGH signal which is an indication from a
device located on the system data bus that data has been received, or is available RDY1 is qual-
ified by AEN1 while RDY2 is qualified by AEN2.
ASYNC
15
I
READY SYNCHRONIZATION SELECT: ASYNC is an input which defines the synchronization
mode of the READY logic. When ASYNC is low, two stages of READY synchronization are pro-
vided. When ASYNC is left open or HIGH, a single stage of READY synchronization is provided.
READY
5
O
READY: READY is an active HIGH signal which is the synchronized RDY signal input. READY
is cleared after the guaranteed hold time to the processor has been met.
X1, X2
17, 16
I O
CRYSTAL IN: X1 and X2 are the pins to which a crystal is attached. The crystal frequency is 3
times the desired processor clock frequency, (Note 1).
F/C
13
I
FREQUENCY/CRYSTAL SELECT: F/C is a strapping option. When strapped LOW. F/C permits
the processor's clock to be generated by the crystal. When F/C is strapped HIGH, CLK is gen-
erated for the EFI input, (Note 1).
EFI
14
I
EXTERNAL FREQUENCY IN: When F/C is strapped HIGH, CLK is generated from the input fre-
quency appearing on this pin. The input signal is a square wave 3 times the frequency of the de-
sired CLK output.
CLK
8
O
PROCESSOR CLOCK: CLK is the clock output used by the processor and all devices which di-
rectly connect to the processor's local bus. CLK has an output frequency which is 1/3 of the crys-
tal or EFI input frequency and a 1/3 duty cycle.
PCLK
2
O
PERIPHERAL CLOCK: PCLK is a peripheral clock signal whose output frequency is 1/2 that of
CLK and has a 50% duty cycle.
OSC
12
O
OSCILLATOR OUTPUT: OSC is the output of the internal oscillator circuitry. Its frequency is
equal to that of the crystal.
RES
11
I
RESET IN: RES is an active LOW signal which is used to generate RESET. The 82C84A pro-
vides a Schmitt trigger input so that an RC connection can be used to establish the power-up
reset of proper duration.
RESET
10
O
RESET: RESET is an active HIGH signal which is used to reset the 80C86 family processors. Its
timing characteristics are determined by RES.
CSYNC
1
I
CLOCK SYNCHRONIZATION: CSYNC is an active HIGH signal which allows multiple 82C84As
to be synchronized to provide clocks that are in phase. When CSYNC is HIGH the internal
counters are reset. When CSYNC goes LOW the internal counters are allowed to resume count-
ing. CSYNC needs to be externally synchronized to EFI. When using the internal oscillator
CSYNC should be hardwired to ground.
GND
9
Ground
V
CC
18
V
CC
: The +5V power supply pin. A 0.1
F capacitor between V
CC
and GND is recommended for
decoupling.
NOTE:
1. If the crystal inputs are not used X1 must be tied to V
CC
or GND and X2 should be left open.
82C84A
4-290
Functional Description
Oscillator
The oscillator circuit of the 82C84A is designed primarily for
use with an external parallel resonant, fundamental mode
crystal from which the basic operating frequency is derived.
The crystal frequency should be selected at three times the
required CPU clock. X1 and X2 are the two crystal input
crystal connections. For the most stable operation of the
oscillator (OSC) output circuit, two capacitors (C1 = C2) as
shown in the waveform figures are recommended. The out-
put of the oscillator is buffered and brought out on OSC so
that other system timing signals can be derived from this sta-
ble, crystal-controlled source.
Capacitors C1, C2 are chosen such that their combined
capacitance
matches the load capacitance as specified by the crystal
manufacturer. This ensures operation within the frequency
tolerance specified by the crystal manufacturer.
Clock Generator
The clock generator consists of a synchronous divide-by-
three counter with a special clear input that inhibits the
counting. This clear input (CSYNC) allows the output clock
to be synchronized with an external event (such as another
82C84A clock). It is necessary to synchronize the CSYNC
input to the EFI clock external to the 82C84A. This is accom-
plished with two flip-flops. (See Figure 1). The counter out-
put is a 33% duty cycle clock at one-third the input
frequency.
NOTE: The F/C input is a strapping pin that selects either the crystal
oscillator or the EFI input as the clock for the
3 counter. If
the EFI input is selected as the clock source, the oscillator
section can be used independently for another clock source.
Output is taken from OSC.
Clock Outputs
The CLK output is a 33% duty cycle clock driver designed to
drive the 80C86, 80C88 processors directly. PCLK is a periph-
eral clock signal whose output frequency is 1/2 that of CLK.
PCLK has a 50% duty cycle.
Reset Logic
The reset logic provides a Schmitt trigger input (RES) and a
synchronizing flip-flop to generate the reset timing. The reset
signal is synchronized to the falling edge of CLK. A simple RC
network can be used to provide power-on reset by utilizing this
function of the 82C84A.
READY Synchronization
Two READY input (RDY1, RDY2) are provided to accommo-
date two system busses. Each input has a qualifier (AEN1 and
AEN2, respectively). The AEN signals validate their respective
RDY signals. If a Multi-Master system is not being used the
AEN pin should be tied LOW.
Synchronization is required for all asynchronous active-going
edges of either RDY input to guarantee that the RDY setup
and hold times are met. Inactive-going edges of RDY in nor-
mally ready systems do not require synchronization but must
satisfy RDY setup and hold as a matter of proper system
design.
The ASYNC input defines two modes of READY synchroniza-
tion operation.
When ASYNC is LOW, two stages of synchronization are pro-
vided for active READY input signals. Positive-going asynchro-
nous READY inputs will first be synchronized to flip-flop one of
the rising edge of CLK (requiring a setup time tR1VCH) and
the synchronized to flip-flop two at the next falling edge of
CLK, after which time the READY output will go active (HIGH).
Negative-going asynchronous READY inputs will be synchro-
nized directly to flip-flop two at the falling edge of CLK, after
which the READY output will go inactive. This mode of opera-
tion is intended for use by asynchronous (normally not ready)
devices in the system which cannot be guaranteed by design
to meet the required RDY setup timing, TR1VCL, on each bus
cycle.
When ASYNC is high or left open, the first READY flip-flop is
bypassed in the READY synchronization logic. READY inputs
are synchronized by flip-flop two on the falling edge of CLK
before they are presented to the processor. This mode is avail-
able for synchronous devices that can be guaranteed to meet
the required RDY setup time.
ASYNC can be changed on every bus cycle to select the
appropriate mode of synchronization for each device in the
system.
TABLE 1. CRYSTAL SPECIFICATIONS
PARAMETER
TYPICAL CRYSTAL SPEC
Frequency
2.4 - 25MHz, Fundamental, "AT" cut
Type of Operation
Parallel
Unwanted Modes
6dB (Minimum)
Load Capacitance
18 - 32pF
CT =
C1 x C2
C1 + C2
----------------------
(Including stray capacitance)
EFI
EFI
82C84A
CSYNC
(TO OTHER 82C84As)
CLOCK
SYNCHRONIZE
D
Q
>
D
Q
>
FIGURE 1. CSYNC SYNCHRONIZATION
NOTE: If EFI input is used, then crystal input X1 must be tied to V
CC
or GND and X2 should be left open. If the crystal inputs are used,
then EFI should be tied to V
CC
or GND.
82C84A
4-291
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.5V to V
CC
+0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
C82C84A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to +70
o
C
I82C84A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
M82C84A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Thermal Resistance . . . . . . . . . . . . . . . .
JA
(
o
C/W)
JC
(
o
C/W)
CERDIP Package . . . . . . . . . . . . . . . .
80
20
CLCC Package . . . . . . . . . . . . . . . . . .
95
28
PDIP Package . . . . . . . . . . . . . . . . . . .
85
N/A
PLCC Package . . . . . . . . . . . . . . . . . .
85
N/A
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65
o
C to +150
o
C
Max Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300
o
C
(PLCC - Lead Tips Only)
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
V
CC
= +5.0V
10%,
T
A
= 0
o
C to +70
o
C (C82C84A),
T
A
= -40
o
C to +85
o
C (I82C84A),
T
A
= -55
o
C to +125
o
C (M82C84A)
SYMBOL
PARAMETER
MIN
MAX
UNITS
TEST CONDITIONS
V
IH
Logical One Input Voltage
2.0
2.2
-
V
V
C82C84A, I82C84
M82C84A, Notes 1, 2
V
IL
Logical Zero Input Voltage
-
0.8
V
Notes 1, 2, 3
V
IHR
Reset Input High Voltage
V
CC
-0.8
-
V
V
ILR
Reset Input Low Voltage
-
0.5
V
VT+ - VT-
Reset Input Hysteresis
0.2 V
CC
-
-
V
OH
Logical One Output Current
V
CC
-0.4
-
V
I
OH
= -4.0mA for CLK Output
I
OH
= -2.5mA for All Others
V
OL
Logical Zero Output Voltage
-
0.4
V
I
OL
= +4.0mA for CLK Output
I
OL
= +2.5mA for All Others
II
Input Leakage Current
-1.0
1.0
A
V
IN
= V
CC
or GND except ASYNC,
X1: (Note 4)
I
CCOP
Operating Power Supply Current
-
40
mA
Crystal Frequency = 25MHz
Outputs Open, Note 5
NOTES:
1. F/C is a strap option and should be held either
0.8V or
2.2V. Does not apply to X1 or X2 pins.
2. Due to test equipment limitations related to noise, the actual tested value may differ from that specified, but the specified limit is
guaranteed.
3. CSYNC pin is tested with V
IL
0.8V.
4. ASYNC pin includes an internal 17.5k
nominal pull-up resistor. For ASYNC input at GND, ASYNC input leakage current = 300
A
nominal, X1 - crystal feedback input.
5. f = 25MHz may be tested using the extrapolated value based on measurements taken at f = 2MHz and f = 10MHz.
Capacitance
T
A
= +25
o
C
SYMBOL
PARAMETER
TYPICAL
UNITS
TEST CONDITIONS
C
IN
Input Capacitance
10
pF
FREQ = 1MHz, all measurements are
referenced to device GND
C
OUT
Output Capacitance
15
pF
82C84A
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