6-248
File Number
2872.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
RFP2N08L, RFP2N10L
2A, 80V and 100V, 1.050 Ohm, Logic Level,
N-Channel Power MOSFETs
The RFP2N08L and RFP2N10L are N-Channel enhancement
mode silicon gate power field effect transistors specifically
designed for use with logic level (5V) driving sources in
applications such as programmable controllers, automotive
switching, and solenoid drivers. This performance is
accomplished through a special gate oxide design which
provides full rated conductance at gate biases in the 3V to 5V
range, thereby facilitating true on-off power control directly
from logic circuit supply voltages.
Formerly developmental type TA0924.
Features
2A, 80V and 100V
r
DS(ON)
= 1.050
Design Optimized for 5V Gate Drives
Can be Driven Directly from QMOS, NMOS, TTL Circuits
Compatible with Automotive Drive Requirements
SOA is Power Dissipation Limited
Nanosecond Switching Speeds
Linear Transfer Characteristics
High Input Impedance
Majority Carrier Device
Related Literature
- TB334 "Guidelines for Soldering Surface Mount
Components to PC Boards"
Symbol
Packaging
JEDEC TO-220AB
Ordering Information
PART NUMBER
PACKAGE
BRAND
RFP2N08L
TO-220AB
RFP2N08L
RFP2N10L
TO-220AB
RFP2N10L
NOTE: When ordering, include the entire part number.
G
D
S
GATE
DRAIN (FLANGE)
SOURCE
DRAIN
Data Sheet
July 1999
6-249
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
RFP2N08L
RFP2N10L
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DS
80
100
V
Drain to Gate Voltage (R
GS
= 1M
)
(Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
80
100
V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
2
2
A
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
5
5
A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
10
10
V
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P
D
25
25
W
Derate above 25
o
C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0.2
0.2
W/
o
C
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
-55 to 150
-55 to 150
o
C
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
300
260
300
260
o
C
o
C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 125
o
C.
Electrical Specifications
T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
BV
DSS
V
GS
= 0V, I
D
= 250
A
RFP2N08L
80
-
-
V
RFP2N10L
100
-
-
V
Gate to Threshold Voltage
V
GS(TH)
V
GS
= V
DS
, I
D
= 250
A
1.0
-
2.0
V
Gate to Source Leakage
I
GSS
V
GS
=
10V, V
DS
= 0V
-
-
100
nA
Zero to Gate Voltage Drain Current
I
DSS
V
DS
= Rated BV
DSS
, V
GS
= 0V
-
-
1.0
A
V
DS
= 0.8 x Rated BV
DSS
, V
GS
= 0V, T
C
= 125
o
C
-
-
25
A
Drain to Source On Voltage (Note 2)
V
DS(ON)
I
D
= 2A, V
GS
= 5V
-
-
2.1
V
Drain to Source On Resistance (Note 2)
r
DS(ON)
I
D
= 2A, V
GS
= 5V, (Figures 6, 7)
-
-
1.050
Turn-On Delay Time
t
d(ON)
I
D
= 2A, V
DD
= 50V, R
G
= 6.25
,
R
L
= 25
, V
GS
= 5V
(Figures 10, 11, 12)
-
10
25
ns
Rise Time
t
r
-
15
45
ns
Turn-Off Delay Time
t
d(OFF)
-
25
45
ns
Fall Time
t
f
-
20
25
ns
Input Capacitance
C
ISS
V
GS
= 0V, V
DS
= 25V, f = 1.0MHz
(Figure 9)
-
-
200
pF
Output Capacitance
C
OSS
-
-
80
pF
Reverse Transfer Capacitance
C
RSS
-
-
35
pF
Thermal Resistance Junction to Case
R
JC
-
-
5
o
C/W
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Source to Drain Diode Voltage (Note 2)
V
SD
I
SD
= 2A
-
-
1.4
V
Reverse Recovery Time
t
rr
I
SD
= 2A, dI
SD
/dt = 50A/
s
-
100
-
ns
NOTES:
2. Pulse test: pulse width
300
s, duty cycle
2%.
3. Repetitive rating: pulse width limited by maximum junction temperature.
RFP2N08L, RFP2N10L
6-250
Typical Performance Curves
Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. FORWARD BIAS SAFE OPERATING AREA
FIGURE 4. SATURATION CHARACTERISTICS
FIGURE 5. TRANSFER CHARACTERISTICS
FIGURE 6. DRAIN TO SOURCE ON RESISTANCE vs DRAIN
CURRENT
T
C
, CASE TEMPERATURE (
o
C)
PO
WER DISSIP
A
TION MUL
TIPLIER
0
0
25
50
75
100
150
0.2
0.4
0.6
0.8
1.0
1.2
125
0
25
50
75
100
125
150
T
C
, CASE TEMPERATURE (
o
C)
I
D
, DRAIN CURRENT (A)
2.5
1.5
1.0
0.5
2.0
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
10
0.01
10
1
I
D
, DRAIN CURRENT (A)
10
2
1
RFP2N10L
0.1
OPERATION IN THIS AREA
LIMITED BY r
DS(ON)
T
J
= MAX RATED, T
C
= 25
o
C
RFP2N08L
10
3
V
DS,
DRAIN TO SOURCE VOLTAGE (V)
I
D
, DRAIN CURRENT (A)
0
4
6
10
2
5
7
3
8
6
4
2
8
1
0
1
3
5
7
9
PULSE DURATION = 80
s
T
C
= 25
o
C
V
GS
= 4.0V
V
GS
= 10V
V
GS
= 5.0V
V
GS
= 2.0V
V
GS
= 3.0V
DUTY CYCLE = 0.5% MAX
1
3
4
6
2
4
I
DS(ON)
, DRAIN T
O
SOURCE CURRENT (A)
V
GS
, GATE TO SOURCE VOLTAGE (V)
6
2
8
5
3
1
5
V
DS
= 15V
PULSE DURATION = 80
s
0
7
T
C
= -40V
T
C
= 25V
T
C
= 125V
T
C
= -40V
T
C
= 125V
DUTY CYCLE = 0.5% MAX
2
I
D,
DRAIN CURRENT (A)
1
0
2
0
1.5
r
DS(ON)
, DRAIN T
O
SOURCE
1
0.5
3
4
T
C
= -40V
10
V
GS
= 5V
PULSE DURATION = 80
s
5
6
7
8
9
T
C
= 25V
T
C
= 125V
ON RESIST
ANCE (
)
DUTY CYCLE = 0.5% MAX
RFP2N08L, RFP2N10L
6-251
FIGURE 7. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 8. NORMALIZED GATE TO THRESHOLD vs
JUNCTION TEMPERATURE
FIGURE 9. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 10. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Test Circuit and Waveforms
FIGURE 11. SWITCHING TIME TEST CIRCUIT
FIGURE 12. RESISTIVE SWITCHING WAVEFORMS
Typical Performance Curves
Unless Otherwise Specified (Continued)
-50
T
J
, JUNCTION TEMPERATURE (
o
C)
2.0
100
0
50
150
200
1.0
1.5
0.5
I
D
= 2A, V
GS
= 5V
PULSE DURATION = 80ms
NORMALIZED DRAIN T
O
SOURCE
ON RESIST
ANCE
DUTY CYCLE = 0.5% MAX
-50
T
J
, JUNCTION TEMPERATURE (
o
C)
NORMALIZED GA
TE T
O
1.0
0.5
0
0
200
THRESHOLD V
O
L
T
A
G
E
50
100
150
1.5
2.0
I
D
= 250
A
V
DS
= V
GS
0
20
30
40
70
C, CAP
A
CIT
ANCE (pF)
V
DS,
DRAIN TO SOURCE VOLTAGE (V)
240
200
160
0
10
120
80
C
ISS
C
RSS
C
OSS
40
50
60
V
GS
= 0V, f = 0.1MHz
C
ISS
= C
GS
+ C
GD
C
RSS
= C
GD
C
OSS
C
DS
+ C
GD
100
75
25
0
20
I
G REF
(
)
I
G ACT
(
)
-------------------------
t, TIME (ms)
80
I
G REF
(
)
I
G ACT
(
)
-------------------------
10
8
6
2
0
V
DS
, DRAIN T
O
SOURCE V
O
L
T
A
GE (V)
V
GS
, GA
TE T
O
SOURCE V
O
L
T
A
GE (V)
V
DD
= BV
DSS
V
DD
= 0.75 BV
DSS
V
DD
= 0.50 BV
DSS
V
DD
= 0.25 BV
DSS
DESCENDING ORDER:
R
L
= 50
, V
GS
= 5V
I
G(REF)
= 0.094mA
50
4
DRAIN SOURCE VOLTAGE
PLATEAU VOLTAGES IN
SOURCE
VOLTAGE
GATE
V
GS
R
L
R
G
DUT
+
-
V
DD
t
ON
t
d(ON)
t
r
90%
10%
V
DS
90%
10%
t
f
t
d(OFF)
t
OFF
90%
50%
50%
10%
PULSE WIDTH
V
GS
0
0
RFP2N08L, RFP2N10L
6-252
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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Intersil Corporation
P. O. Box 883, Mail Stop 53-204
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TEL: (407) 724-7000
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Taipei, Taiwan
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TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
RFP2N08L, RFP2N10L
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