8-143
File Number
4537.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
RFT3055LE
2.0A, 60V, 0.150 Ohm, N-Channel, Logic
Level, ESD Rated, Power MOSFET
This product is an N-Channel power MOSFET manufactured
using the MegaFET process. This process, which uses
feature sizes approaching those of LSI circuits, gives
optimum utilization of silicon, resulting in outstanding
performance. It was designed for use in applications such as
switching regulators, switching converters, motor drivers,
and relay drivers. These transistors can be operated directly
from integrated circuits.
Formerly developmental type TA49158.
Features
2.0A, 60V
r
DS(ON)
= 0.150
2kV ESD Protected
Temperature Compensating PSPICE
Model
Thermal Impedance SPICE Model
Peak Current vs Pulse Width Curve
UIS Rating Curve
Related Literature
- TB334, "Guidelines for Soldering Surface Mount
Components to PC Boards"
Symbol
Packaging
SOT-223
Ordering Information
PART NUMBER
PACKAGE
BRAND
RFT3055LE
SOT-223
3055L
NOTE: RFT3055LE is available only in tape and reel.
D
G
S
DRAIN
SOURCE
GATE
DRAIN
(FLANGE)
Data Sheet
August 1999
8-144
Absolute Maximum Ratings
T
A
= 25
o
C, Unless Otherwise Specified
RFT3055LE
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
60
V
Drain to Gate Voltage (R
GS
= 20k
) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
DGR
60
V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
10
V
Drain Current
Continuous (Figure 2) (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
2.0
Figure 5
A
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
Figures 6, 16, 17
Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Derate Above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
9.09
W
mW/
o
C
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
-55 to 150
o
C
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
300
260
o
C
o
C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 125
o
C.
Electrical Specifications
T
A
= 25
o
C, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
BV
DSS
I
D
= 250
A, V
GS
= 0V (Figure 11)
60
-
-
V
Gate to Source Threshold Voltage
V
GS(TH)
V
GS
= V
DS
, I
D
= 250
A (Figure 10)
1
-
2
V
Zero Gate Voltage Drain Current
I
DSS
V
DS
= 60V, V
GS
= 0V
-
-
1
A
V
DS
= 60V, V
GS
= 0V, T
A
= 150
o
C
-
-
50
A
Gate to Source Leakage Current
I
GSS
V
GS
=
10V
-
-
10
A
Drain to Source On Resistance
r
DS(ON)
I
D
= 2.0A, V
GS
= 5V (Figure 9)
-
0.110
0.150
Turn-On Time
t
ON
V
DD
= 30V, I
D
2.0A,
R
L
= 15
, V
GS
=
5V,
R
GS
= 5
(Figure 12)
-
-
120
ns
Turn-On Delay Time
t
d(ON)
-
10
-
ns
Rise Time
t
r
-
70
-
ns
Turn-Off Delay Time
t
d(OFF)
-
30
-
ns
Fall Time
t
f
-
25
-
ns
Turn-Off Time
t
OFF
-
-
85
ns
Total Gate Charge
Q
g(TOT)
V
GS
= 0V to 10V
V
DD
= 30V,
I
D
2.0A,
R
L
= 15
I
g(REF)
= 1.0mA
(Figure 15)
-
28
35
nC
Gate Charge at 10V
Q
g(5)
V
GS
= 0V to 5V
-
15
18
nC
Threshold Gate Charge
Q
g(TH)
V
GS
= 0V to 1V
-
1.0
1.2
nC
Input Capacitance
C
ISS
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
(Figure 12)
-
850
-
pF
Output Capacitance
C
OSS
-
170
-
pF
Reverse Transfer Capacitance
C
RSS
-
100
-
pF
Thermal Resistance Junction to Ambient
R
JA
Pad Area = 0.171 in
2
(see note 2)
-
-
110
o
C/W
Pad Area = 0.068 in
2
-
-
128
o
C/W
Pad Area = 0.026 in
2
-
-
147
o
C/W
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Source to Drain Diode Voltage
V
SD
I
SD
= 2.0A
-
-
1.5
V
Reverse Recovery Time
t
rr
I
SD
= 2.0A, dI
SD
/dt = 100A/
s
-
-
100
ns
NOTE:
2. 110
o
C/W measured using FR-4 board with 0.171in
2
footprint for 1000 seconds.
RFT3055LE
8-145
Typical Performance Curves
Unless otherwise specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
T
A
, AMBIENT TEMPERATURE (
o
C)
PO
WER DISSIP
A
TION MUL
TIPLIER
0
0
25
50
75
100
150
0.2
0.4
0.6
0.8
1.0
1.2
125
0
0.5
1.0
1.5
2.0
2.5
25
50
75
100
125
150
I
D
, DRAIN CURRENT (A)
T
A
, AMBIENT TEMPERATURE (
o
C)
R
JA
= 110
o
C/W
0.01
0.1
1
10
-3
10
-2
10
-1
10
0
10
1
10
2
10
3
2
Z
JA
, NORMALIZED
THERMAL IMPED
ANCE
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
JA
x R
JA
+ T
A
P
DM
t
1
t
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.01
0.02
t, RECTANGULAR PULSE DURATION (s)
R
JA
= 110
o
C/W
0.1
1
10
100
0.1
1
10
100
0.01
200
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
I
D
, DRAIN CURRENT (A)
T
J
= MAX RATED
T
A
= 25
o
C
100
s
10ms
1ms
100ms
DC
LIMITED BY r
DS(ON)
AREA MAY BE
OPERATION IN THIS
R
JA
= 110
o
C/W
1
10
30
10
-3
10
-2
10
-1
10
0
10
1
10
2
10
3
t, PULSE WIDTH (s)
I
DM
, PEAK CURRENT (A)
I = I
25
150 - T
A
125
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
T
A
= 25
o
C
V
GS
= 5V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
R
JA
= 110
o
C/W
RFT3055LE
8-146
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
Typical Performance Curves
Unless otherwise specified (Continued)
0.1
1
10
20
0.01
0.1
1
10
100
I
AS
, A
V
ALANCHE CURRENT (A)
t
AV
, TIME IN AVALANCHE (ms)
t
AV
= (L)(I
AS
)/(1.3*RATED BV
DSS
- V
DD
)
If R = 0
If R
0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3*RATED BV
DSS
- V
DD
) +1]
STARTING T
J
= 25
o
C
STARTING T
J
= 150
o
C
0
4
8
12
16
20
0
1
2
3
4
5
I
D
, DRAIN CURRENT (A)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
= 3V
V
GS
= 4V
PULSE DURATION = 80
s
T
A
= 25
o
C
DUTY CYCLE = 0.5% MAX
V
GS
= 10V
V
GS
= 5V
V
GS
= 4.5V
0
4
8
12
16
20
0
1.5
3.0
4.5
6.0
I
D,
DRAIN CURRENT (A)
V
GS
, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
V
DD
= 15V
25
o
C
-55
o
C
150
o
C
0.5
0.75
1.0
1.25
1.5
1.75
2.0
-80
-40
0
40
80
120
160
NORMALIZED DRAIN T
O
SOURCE
T
J
, JUNCTION TEMPERATURE (
o
C)
ON RESIST
ANCE
PULSE DURATION = 80
s
V
GS
= 5V, I
D
= 2A
DUTY CYCLE = 0.5% MAX
0.7
0.8
0.9
1.0
1.1
1.2
-80
-40
0
40
80
120
160
NORMALIZED GA
TE
T
J
, JUNCTION TEMPERATURE (
o
C)
THRESHOLD V
O
L
T
A
GE
V
GS
= V
DS
, I
D
= 250
A
0.9
0.95
1.0
1.05
1.1
1.15
-80
-40
0
40
80
120
160
BREAKDO
WN V
O
L
T
A
GE
T
J
, JUNCTION TEMPERATURE (
o
C)
NORMALIZED DRAIN T
O
SOURCE
I
D
= 250
A
RFT3055LE
8-147
FIGURE 12. SWITCHING TIME vs GATE RESISTANCE
FIGURE 13. SOURCE TO DRAIN ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 15. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
Typical Performance Curves
Unless otherwise specified (Continued)
0
150
200
0
10
20
30
40
SWITCHING TIME (ns)
R
GS
, GATE TO SOURCE RESISTANCE (
)
50
50
t
R
t
F
t
D(OFF)
t
D(ON)
100
V
DD
= 30V, I
D
= 2A, R
L
= 15
50
100
150
200
250
2
4
6
8
10
V
GS
, GATE TO SOURCE VOLTAGE (V)
r
DS(ON)
, ON-ST
A
TE RESIST
ANCE (m
)
PULSE DURATION = 80
s
I
D
= 2A
I
D
= 0.5A
DUTY CYCLE = 0.5% MAX
0
300
600
900
1200
0
5
10
15
20
25
30
C, CAP
A
CIT
ANCE (pF)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
C
ISS
C
OSS
C
RSS
V
GS
= 0V, f = 1MHz
C
ISS
= C
GS
+ C
GD
C
RSS
= C
GD
C
OSS
= C
DS
+ C
GD
0
2
4
6
8
10
0
6
12
18
24
30
V
GS
, GA
TE T
O
SOURCE V
O
L
T
A
GE (V)
V
DD
= 15V
Q
g
, GATE CHARGE (nC)
I
D
= 2A
I
D
= 0.5A
WAVEFORMS IN
DESCENDING ORDER:
RFT3055LE
8-148
Test Circuits and Waveforms
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
FIGURE 18. GATE CHARGE TEST CIRCUIT
FIGURE 19. GATE CHARGE WAVEFORM
FIGURE 20. SWITCHING TIME TEST CIRCUIT
FIGURE 21. RESISTIVE SWITCHING WAVEFORMS
t
P
V
GS
0.01
L
I
AS
+
-
V
DS
V
DD
R
G
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
0V
DUT
V
DD
V
DS
BV
DSS
t
P
I
AS
t
AV
0
R
L
V
GS
+
-
V
DS
V
DD
DUT
I
g(REF)
V
DD
Q
g(TH)
V
GS
= 1V
Q
g(5)
V
GS
= 5V
Q
g(TOT)
V
GS
= 10V
V
DS
V
GS
I
g(REF)
0
0
V
GS
0V
R
GS
R
L
DUT
+
-
V
GS
V
DS
t
ON
t
d(ON)
t
r
90%
10%
V
DS
90%
10%
t
f
t
d(OFF)
t
OFF
90%
50%
50%
10%
PULSE WIDTH
V
GS
0
0
RFT3055LE
8-149
Thermal Resistance vs. Mounting Pad
Area
The maximum rated junction temperature, T
J(MAX)
, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P
D(MAX)
,
in an application. Therefore the application's ambient
temperature, T
A
(
o
C), and thermal impedance R
JA
(
o
C/W)
must be reviewed to ensure that T
J(MAX)
is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
In using surface mount devices such as the SOT-223
package, the environment in which it is applied will have a
significant influence on the part's current and maximum
power dissipation ratings. Precise determination of the
P
D(MAX)
is complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Intersil provides thermal information to assist the designer's
preliminary application evaluation. Figure 22 defines the
R
JA
for the device as a function of the top copper
(component side) area. This is for a horizontally positioned
FR-4 board with 1oz copper after 1000 seconds of steady
state power with no air flow.This graph provides the
necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Intersil device Spice
thermal model or manually utilizing the normalized maximum
transient thermal impedance curve.
Displayed on the curve are the three R
JA
values listed in
the Electrical Specifications table. The three points were
chosen to depict the compromise between the copper board
area, the thermal resistance and ultimately the power
dissipation, P
D(MAX)
. Thermal resistances corresponding to
other component side copper areas can be obtained from
Figure 22 or by calculation using Equation 2. The area, in
square inches is the top copper area including the gate and
source pads.
(EQ. 1)
P
D MAX
(
)
T
J MAX
(
)
T
A
(
)
R
JA
--------------------------------------------
=
50
100
150
200
0.01
0.1
1.0
147
o
C/W - 0.026in
2
AREA, TOP COPPER AREA (in
2
)
R
JA
(
o
C/W)
128
o
C/W - 0.068in
2
110
o
C/W - 0.171in
2
R
JA
= 75.9 - 19.3 * ln(AREA)
FIGURE 22. THERMAL RESISTANCE vs MOUNTING PAD
AREA
(EQ. 2)
R
JA
75.9
19.3
Area
(
)
ln
=
RFT3055LE
8-150
PSPICE Electrical Model
.SUBCKT RFT3055LE 2 1 3 ;
REV May 98
CA 12 8 1.68e-9
CB 15 14 1.78e-9
CIN 6 8 7.69e-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DESD1 91 9 DESD1MOD
DESD2 91 7 DESD2MOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 64.28
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1e-9
LGATE 1 9 4.6e-9
LSOURCE 3 7 4.6e-9
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 24e-3
RGATE 9 20 9.84
RLDRAIN 2 5 10
RLGATE 1 9 46
RLSOURCE 3 7 46
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 49e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*45),4))}
.MODEL DBODYMOD D (IS = 3.61e-13 RS = 1.78e-2 TRS1 = 1.7e-2 TRS2 = -4.69e-6 CJO = 3.88e-10 TT = 3.6e-8)
.MODEL DBREAKMOD D (RS = 4.73e-1 TRS1 = -2.19e-3 TRS2 = 4.7e-5)
.MODEL DESD1MOD D (BV = 12.5 NBV = 17.5 IBV = 2.5e-4 RS = 22)
.MODEL DESD2MOD D (BV = 12.86 NBV = 22 IBV = 2.5e-4 RS = 0)
.MODEL DPLCAPMOD D (CJO = 4.803e-10 IS = 1e-30 N = 10)
.MODEL MMEDMOD NMOS (VTO = 1.78 KP = 1.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 9.84)
.MODEL MSTROMOD NMOS (VTO = 2.08 KP = 10.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.55 KP = 0.1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 98.4 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.06e-3 TC2 = -6.22e-7)
.MODEL RDRAINMOD RES (TC1 = 4.5e-3 TC2 = 6e-5)
.MODEL RSLCMOD RES (TC1 = 0 TC2 = 0)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC = 0 TC2 = -4e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.9e-3 TC2 = 1.3e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.4 VOFF= -2.4)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.4 VOFF= -4.4)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.0 VOFF= 1.15)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.15 VOFF= -2.0)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
1
GATE
RGATE
EVTEMP
18
22
9
+
12
13
8
14
13
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
CIN
MWEAK
RDRAIN
DBREAK
EBREAK
DBODY
DRAIN
RSOURCE
SOURCE
RBREAK
RVTEMP
VBAT
IT
EVTHRES
ESG
DPLCAP
ESLC
RSLC1
RSLC2
6
6
8
10
5
51
50
5
51
16
21
11
17
18
8
14
5
8
6
8
7
3
17
18
19
2
+
+
+
+
+
+
+
19
8
22
MMED
MSTRO
RVTHRES
LSOURCE
RLSOURCE
LDRAIN
RLDRAIN
LGATE
RLGATE
91
DESD1
DESD2
20
8
RFT3055LE
8-151
SPICE Thermal Model
REV May 98
RFT3055LE
Copper Area = 0.077in
2
CTHERM1 9 8 7.5e-5
CTHERM2 8 7 3.5e-4
CTHERM3 7 6 1.2e-3
CTHERM4 6 5 1.5e-2
CTHERM5 5 4 6.0e-2
CTHERM6 4 3 3.0e-1
CTHERM7 3 2 1.6
CTHERM8 2 1 6
RTHERM1 9 8 8.2e-2
RTHERM2 8 7 2.7e-1
RTHERM3 7 6 1.9
RTHERM4 6 5 3.1
RTHERM5 5 4 12
RTHERM6 4 3 38
RTHERM7 3 2 32
RTHERM8 2 1 22
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
1
4
5
6
7
8
9
JUNCTION
AMBIENT
2
3
RTHERM7
RTHERM8
CTHERM7
CTHERM8
RFT3055LE
8-152
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RFT3055LE
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