6-418
File Number
3948.5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
RLD03N06CLE, RLD03N06CLESM,
RLP03N06CLE
0.3A, 60V, 6 Ohm, ESD Rated, Current
Limited, Voltage Clamped, Logic Level
N-Channel Power MOSFETs
These are intelligent monolithic power circuits which
incorporate a lateral bipolar transistor, resistors, zener
diodes and a power MOS transistor. The current limiting of
these devices allow it to be used safely in circuits where a
shorted load condition may be encountered. The drain to
source voltage clamping offers precision control of the circuit
voltage when switching inductive loads. The "Logic Level"
gate allows this device to be fully biased on with only 5V
from gate to source, thereby facilitating true on-off power
control directly from logic level (5V) integrated circuits.
These devices incorporate ESD protection and are designed
to withstand 2kV (Human Body Model) of ESD.
Formerly developmental type TA49028.
Features
0.30A, 60V
r
DS(ON)
= 6.0
Built in Current Limit I
LIMIT
0.140 to 0.210A at 150
o
C
Built in Voltage Clamp
Temperature Compensating PSPICE
Model
2kV ESD Protected
Controlled Switching Limits EMI and RFI
Related Literature
- TB334 "Guidelines for Soldering Surface Mount
Components to PC Boards"
Symbol
Packaging
Ordering Information
PART NUMBER
PACKAGE
BRAND
RLD03N06CLE
TO-251AA
03N06C
RLD03N06CLESM
TO-252AA
03N06C
RLP03N06CLE
TO-220AB
03N06CLE
NOTE: When ordering, use the entire part number. Add the suffix 9A to
obtain the TO-252AA variant in tape and reel, i.e. RLD03N06CLESM9A.
G
S
D
JEDEC TO-251AA
JEDEC TO-252AA
JEDEC TO-220AB
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
GATE
SOURCE
DRAIN
(FLANGE)
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
Data Sheet
July 1999
6-419
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
RLD03N06CLE, RLD03N06CLESM,
RLP03N06CLE
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
60
V
Drain to Gate Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
60
V
Gate to Source Voltage (Reverse Voltage Gate Bias Not Allowed) . . . . . . . . . . . . V
GS
+5.5
V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
D
Self Limited
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Derate Above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
0.2
W
W/
o
C
Electrostatic Discharge Rating MIL-STD-883, Category B(2) . . . . . . . . . . . . . . . .ESD
2
KV
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
-55 to 175
o
C
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
pkg
300
260
o
C
o
C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 150
o
C.
Electrical Specifications
T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
BV
DSS
I
D
= 250
A, V
GS
= 0V
60
-
85
V
Gate Threshold Voltage
V
GS(TH)
V
GS
= V
DS
, I
D
= 250
A
1
-
2.5
V
Zero Gate Voltage Drain Current
I
DSS
V
DS
= 45V,
V
GS
= 0V
T
J
= 25
o
C
-
-
25
A
T
J
= 150
o
C
-
-
250
A
Gate to Source Leakage Current
I
GSS
V
GS
= 5V
T
J
= 25
o
C
-
-
5
A
T
J
= 150
o
C
-
-
20
A
Drain to Source On Resistance (Note 2)
r
DS(ON)
I
D
= 0.100A,
V
GS
= 5V
T
J
= 25
o
C
-
-
6.0
T
J
= 150
o
C
-
-
12.0
Limiting Current
I
DS(LIMIT)
V
DS
= 15V,
V
GS
= 5V
T
J
= 25
o
C
280
-
420
mA
T
J
= 150
o
C
140
-
210
mA
Turn-On Time
t
ON
V
DD
= 30V, I
D
= 0.10A,
R
L
= 3
00
, V
GS
= 5V,
R
GS
= 25
-
-
7.5
s
Turn-On Delay Time
t
d(ON)
-
-
2.5
s
Rise Time
t
r
-
-
5.0
s
Turn-Off Delay Time
t
d(OFF)
-
-
7.5
s
Fall Time
t
f
-
-
5.0
s
Turn-Off Time
t
OFF
-
-
12.5
s
Input Capacitance
C
ISS
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
-
100
-
pF
Output Capacitance
C
OSS
-
65
-
pF
Reverse Transfer Capacitance
C
RSS
-
3.0
-
pF
Thermal Resistance Junction to Case
R
JC
-
-
5.0
o
C/W
Thermal Resistance Junction to Ambient
R
JA
TO-220 Package
-
-
80
o
C/W
TO-251 and TO-252 Packages
-
-
100
o
C/W
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Source to Drain Diode Voltage
V
SD
I
SD
= 0.1A
-
-
1.5
V
Diode Reverse Recovery Time
t
rr
I
SD
= 0.1A, dI
SD
/dt = 100A/
s
-
-
1.0
ms
NOTES:
2. Pulsed: pulse duration =
300
s maximum, duty cycle =
2%.
3. Repititive rating: pulse width limited by maximum junction temperature.
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE
6-420
Typical Performance Curves
Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. FORWARD BIAS SAFE OPERATING AREA
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. SELF-CLAMPED INDUCTIVE SWITCHING
FIGURE 5. SATURATION CHARACTERISTICS
T
C
, CASE TEMPERATURE (
o
C)
25
50
75
100
125
150
175
0
PO
WER DISSIP
A
TION MUL
TIPLIER
0
0
0.2
0.4
0.6
0.8
1.0
1.2
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
1
10
100
I
D
,
DRAIN CURRENT
(A)
0.1
1
175
o
C
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
25
o
C
DC
T
C
= 25
o
C, T
J
= MAX RATED
OPERATION IN THIS
AREA IS LIMITED BY
JUNCTION TEMPERATURE
t, RECTANGULAR PULSE DURATION (s)
Z
JC
, NORMALIZED
THERMAL IMPED
ANCE
2
1
0.1
0.01
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
JC
x R
JC
+ T
C
P
DM
t
1
t
2
0.01
0.02
0.05
0.1
0.2
0.5
SINGLE PULSE
t
AV
, TIME IN CLAMP (s)
0.01
0.1
1
10
I
(CLAMP)
,
CLAMPED DRAIN CURRENT (A)
0.1
1
25
o
C
0.001
50
o
C
100
o
C
125
o
C
150
o
C
TEMPERATURES LISTED ARE STARTING
JUNCTION TEMPERATURES
75
o
C
T
C
= 25
o
C
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
I
D
, DRAIN CURRENT (A)
0
0.10
0.20
0.30
0
1
2
3
4
5
V
GS
= 3V
V
GS
= 4V
V
GS
= 7.5V
V
GS
= 5V
0.40
PULSE DURATION = 80
s
T
C
= 25
o
C
DUTY CYCLE = 0.5% MAX
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE
6-421
FIGURE 6. TRANSFER CHARACTERISTICS
FIGURE 7. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 8. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 9. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs TEMPERATURE
FIGURE 10. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 11. NORMALIZED DRAIN LIMITING CURRENT vs
JUNCTION TEMPERATURE
Typical Performance Curves
Unless Otherwise Specified (Continued)
25
o
C
175
o
C
V
GS
, GATE TO SOURCE VOLTAGE (V)
0
2
3
4
5
1
0
0.30
0.40
I
D(ON)
, ON ST
A
TE DRAIN CURRENT (A)
-55
o
C
0.50
0.60
0.20
0.10
PULSE TEST
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX
V
DD
= 15V
T
J
, JUNCTION TEMPERATURE (
o
C)
0
0.5
1.0
1.5
2.0
2.5
-80
-40
0
40
80
120
160
200
NORMALIZED DRAIN T
O
SOURCE
I
D
= 0.10A
V
GS
= 5V,
PULSE DURATION = 80
s
ON RESIST
ANCE
DUTY CYCLE = 0.5% MAX
T
J
, JUNCTION TEMPERATURE (
o
C)
-80
-40
0
40
80
120
200
160
0
0.5
1.0
1.5
2.0
NORMALIZED GA
TE
THRESHOLD V
O
L
T
A
GE
V
GS
= V
DS
, I
D
= 250
A
2.0
1.5
1.0
0.5
0
-80
-40
0
40
80
120
160
200
NORMALIZED DRAIN T
O
SOURCE BREAKDO
WN V
O
L
T
A
G
E
T
J
, JUNCTION TEMPERATURE (
o
C)
I
D
= 10mA
300
100
0
0
5
10
15
20
25
C
,
CAP
A
CIT
ANCE (pF)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
C
RSS
200
C
OSS
C
ISS
V
GS
= 0V, f = 1MHz
C
ISS
= C
GS
+ C
GD
C
RSS
= C
GD
C
OSS
C
DS
+ C
GD
NORMALIZED DRAIN LIMITING CURRENT
2.0
1.0
0.5
0
1.5
T
J
, JUNCTION TEMPERATURE (
o
C)
-80
-40
0
40
80
120
160
200
V
GS
= 5V
PULSE DURATION = 80
s
DUTY CYCLE = 0.5% MAX.
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE
6-422
Detailed Description
Temperature Dependence of Current Limiting and
Switching Speed Performance
The RLD03N06CLE, CLESM and RLP03N06CLE are
monolithic power devices which incorporate a Logic Level power
MOSFET transistor with a current sensing scheme and control
circuitry to enable the device to self limit the drain source current
flow. The current sensing scheme supplies current to a resistor
that is connected across the base to emitter of a bipolar transistor
in the control section. The collector of this bipolar transistor is
connected to the gate of the power MOSFET transistor. When
the ratiometric current from the current sensing reaches the
value required to forward bias the base emitter junction of this
bipolar transistor, the bipolar "turns on". A resistor is incorporated
in series with the gate of the power MOSFET transistor allowing
the bipolar transistor to adjust the drive on the gate of the power
MOSFET transistor to a voltage which then maintains a constant
current in the power MOSFET transistor. Since both the
ratiometric current sensing scheme and the base emitter unction
voltage of the bipolar transistor vary with temperature, the current
at which the device limits is a function of temperature. This
dependence is shown in Figure 3.
The resistor in series with the gate of the power MOSFET
transistor also results in much slower switching performance
than in standard power MOSFET transistors. This is an
advantage where fast switching can cause EMI or RFI. The
switching speed is very predictable.
DC Operation
The limit on the drain to source voltage for operation in
current limiting on a steady state (DC) basis is shown in the
equation below. The dissipation in the device is simply the
applied drain to source voltage multiplied by the limiting
current. This device, like most power MOSFET devices
today, is limited to 175
o
C. The maximum voltage allowable
can, therefore, be expressed as shown in Equation 1:
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT.
Test Circuits and Waveforms
FIGURE 13. RESISTIVE SWITCHING TEST CIRCUIT
FIGURE 14. RESISTIVE SWITCHING WAVEFORMS
Typical Performance Curves
Unless Otherwise Specified (Continued)
60
45
30
15
0
I
G REF
(
)
I
G ACT
(
)
----------------------
t, TIME (
s)
I
G REF
(
)
I
G ACT
(
)
----------------------
5.00
3.75
2.50
1.25
0.00
V
DS
, DRAIN SOURCE V
O
L
T
A
GE (V)
V
GS
, GA
TE SOURCE V
O
L
T
A
GE (V)
V
DD
= BV
DSS
R
L
= 600
I
G(REF)
= 0.1mA
V
GS
= 5V
0.75 BV
DSS
0.50 BV
DSS
0.25 BV
DSS
10
40
V
DD
V
DS
V
GS
0V
R
GS
DUT
R
L
t
ON
t
d(ON)
t
r
90%
10%
V
DS
90%
10%
t
f
t
d(OFF)
t
OFF
90%
50%
50%
10%
PULSE WIDTH
V
GS
DS
150
C T
AMBIENT
(
)
I
LM
R
JC
R
JA
+
(
)
-------------------------------------------------------
=
(EQ. 1)
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE
6-423
The results of this equation are plotted in Figure 15 for various
heatsinks.
Duty Cycle Operation
In many applications either the drain to source voltage or the
gate drive is not available 100% of the time. The copper header
on which the RLD03N06CLE, CLESM and RLP03N06CLE is
mounted has a very large thermal storage capability, so for
pulse widths of less then 1ms, the temperature of the header
can be considered a constant, thereby the junction temperature
can be calculated simply as shown in Equation 2:
Generally the heat storage capability of the silicon chip in a
power transistor is ignored for duty cycle calculations. Making
this assumption, limiting junction temperature to 175
o
C and
using the T
C
calculated in Equation 2, the expression for ma-
ximum V
DS
under duty cycle operation is shown in Equation 3
:
These values are plotted as Figures 16 through 21 for vari-
ous heatsink thermal resistances.
Limited Time Operations
Protection for a limited period of time is sufficient for many
applications. As stated above the heat storage in the silicon
chip can usually be ignored for computations of over 10 ms,
thereby the thermal equivalent circuit reduces to a simple
enough circuit to allow easy computation on the limiting
conditions. The variation in limiting current with temperature
complicates the calculation of junction temperature, but a
simple straight line approximation of the variation is accurate
enough to allow meaningful computations. The curves shown
as Figures 22 through 25 (RLP03N06CLE) and Figure 26
through 29 (RLD03N06CLE and RLD03N06CLESM) give an
accurate indication of how long the specified voltage can be
applied to the device in the current limiting mode without
exceeding the maximum specified 175
o
C junction temperature.
In practice this tells you how long you have to alleviate the
condition causing the current limiting to occur.
T
C
V
DS
I
D
D
R
CA
(
)
T
AMBIENT
+
=
(EQ. 2)
V
DS
150 C
T
C
o
I
LM
D
R
JC
------------------------------------------
=
(EQ. 3)
Typical Performance Curves
NOTE: Heat Sink Thermal Resistance = HSTR.
FIGURE 15. DC OPERATION IN CURRENT LIMITING
FIGURE 16. MAXIMUM V
DS
vs AMBIENT TEMPERATURE IN
CURRENT LIMITING. (HEATSINK THERMAL
RESISTANCE = 1
o
C/W)
FIGURE 17. MAXIMUM V
DS
vs AMBIENT TEMPERATURE IN
CURRENT LIMITING. (HSTR = 2
o
C/W)
FIGURE 18. MAXIMUM V
DS
vs AMBIENT TEMPERATURE IN
CURRENT LIMITING. (HSTR = 5
o
C/W)
HSTR = 0
o
C/W
HSTR = 1
o
C/W
HSTR = 2
o
C/W
HSTR = 10
o
C/W
HSTR = 25
o
C/W
HSTR = 80
o
C/W
T
J
= 175
o
C
I
LIM
= 0.210A
R
JC
= 5.0
o
C/W
90
75
60
45
30
15
0
25
50
75
100
125
150
175
T
A
, AMBIENT TEMPERATURE (
o
C)
V
DS
, APPLIED V
O
L
T
A
GE (V)
HSTR = 5
o
C/W
DC = 2%
DC = 5%
DC = 10%
DC = 20%
DC = 50%
90
75
60
45
30
15
0
100
125
150
175
T
A
, AMBIENT TEMPERATURE (
o
C)
V
DS
, DRAIN T
O
SOURCE V
O
L
T
A
GE (V)
T
J
= 175
o
C
I
LIM
= 0.210A
R
JC
= 5.0
o
C/W
DUTY CYCLE = DC MAX PULSE WIDTH = 100ms
DC = 2%
DC = 5%
DC = 10%
DC = 20%
DC = 50%
90
75
60
45
30
15
0
100
125
150
175
T
A
, AMBIENT TEMPERATURE (
o
C)
V
DS
, DRAIN T
O
SOURCE V
O
L
T
A
GE (V)
T
J
= 175
o
C
I
LIM
= 0.210A
R
JC
= 5.0
o
C/W
DUTY CYCLE = DC MAX PULSE WIDTH = 100ms
DC = 2%
DC = 5%
DC = 10%
DC = 20%
DC = 50%
90
75
60
45
30
15
0
75
100
125
150
175
T
A
, AMBIENT TEMPERATURE (
o
C)
V
DS
, DRAIN T
O
SOURCE V
O
L
T
A
GE (V)
T
J
= 175
o
C
I
LIM
= 0.210A
R
JC
= 5.0
o
C/W
DUTY CYCLE = DC MAX PULSE WIDTH = 100ms
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE
6-424
FIGURE 19. MAXIMUM V
DS
vs AMBIENT TEMPERATURE IN
CURRENT LIMITING. (HSTR = 10
o
C/W)
FIGURE 20. MAXIMUM V
DS
vs AMBIENT TEMPERATURE IN
CURRENT LIMITING. (HSTR = 25
o
C/W)
NOTE:
Duty Cycyle = DC, Max Pulse Width = 100ms.
FIGURE 21. MAXIMUM V
DS
vs AMBIENT TEMPERATURE IN
CURRENT LIMITING. (HSTR = 80
o
C/W)
FIGURE 22. TIME TO 175
o
C IN CURRENT LIMITING
(HEATSINK THERMAL RESISTANCE = 25
o
C/W)
(HEATSINK THERMAL CAPACITANCE = 0.5J/
o
C)
FIGURE 23. TIME TO 175
o
C IN CURRENT LIMITING
(HEATSINK THERMAL RESISTANCE = 10
o
C/W)
(HEATSINK THERMAL CAPACITANCE = 1.0J/
o
C)
FIGURE 24. TIME TO 175
o
C IN CURRENT LIMITING
(HEATSINK THERMAL RESISTANCE = 5
o
C/W)
(HEATSINK THERMAL CAPACITANCE = 2.0J/
o
C)
Typical Performance Curves
(Continued)
DC = 2%
DC = 5%
DC = 10%
DC = 20%
DC = 50%
90
75
60
45
30
15
0
75
100
125
150
175
T
A
, AMBIENT TEMPERATURE (
o
C)
V
DS
, DRAIN T
O
SOURCE V
O
L
T
A
GE (V)
50
25
T
J
= 175
o
C
I
LIM
= 0.210A
R
JC
= 5.0
o
C/W
DUTY CYCLE = DC MAX PULSE WIDTH = 100ms
DC = 2%
DC = 5%
DC = 10%
DC = 20%
90
75
60
45
30
15
0
75
100
125
150
175
T
A
, AMBIENT TEMPERATURE (
o
C)
V
DS
, DRAIN T
O
SOURCE V
O
L
T
A
GE (V)
50
25
T
J
= 175
o
C
I
LIM
= 0.210A
R
JC
= 5.0
o
C/W
DC = 50%
DUTY CYCLE = DC MAX PULSE WIDTH = 100ms
DC = 2%
DC = 5%
DC = 10%
DC = 20%
DC = 50%
90
75
60
45
30
15
0
75
100
125
150
175
T
A
, AMBIENT TEMPERATURE (
o
C)
V
DS
, DRAIN T
O
SOURCE V
O
L
T
A
GE (V)
50
25
DC = 1%
T
J
= 175
o
C
I
LIM
= 0.210A
R
JC
= 5.0
o
C/W
10
8
6
4
2
0
50
70
90
30
10
TIME T
O
175
o
C (s)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
STARTING T
J
= 75
o
C
STARTING T
J
= 150
o
C
STARTING T
J
= 100
o
C
STARTING T
J
= 125
o
C
10
8
6
4
2
0
50
70
90
30
10
TIME T
O
175
o
C (s)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
STARTING T
J
= 75
o
C
STARTING T
J
= 150
o
C
STARTING T
J
= 100
o
C
STARTING T
J
= 125
o
C
10
8
6
4
2
0
50
70
90
TIME T
O
175
o
C (s)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
30
10
STARTING T
J
= 125
o
C
STARTING T
J
= 150
o
C
STARTING T
J
= 100
o
C
STARTING T
J
= 75
o
C
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE
6-425
FIGURE 25. TIME TO 175
o
C IN CURRENT LIMITING
(HEATSINK THERMAL RESISTANCE = 2
o
C/W)
(HEATSINK THERMAL CAPACITANCE = 4J/
o
C)
FIGURE 26. TIME TO 175
o
C IN CURRENT LIMITING
(HEATSINK THERMAL RESISTANCE = 25
o
C/W)
(HEATSINK THERMAL CAPACITANCE = 0.5J/
o
C)
FIGURE 27. TIME TO 175
o
C IN CURRENT LIMITING
(HEATSINK THERMAL RESISTANCE = 10
o
C/W)
(HEATSINK THERMAL CAPACITANCE = 1.0J/
o
C)
FIGURE 28. TIME TO 175
o
C IN CURRENT LIMITING
(HEATSINK THERMAL RESISTANCE = 5
o
C/W)
(HEATSINK THERMAL CAPACITANCE = 2.0J/
o
C)
FIGURE 29. TIME TO 175
o
C IN CURRENT LIMITING
(HEATSINK THERMAL RESISTANCE = 2
o
C/W)
(HEATSINK THERMAL CAPACITANCE = 4J/
o
C)
Typical Performance Curves
(Continued)
10
8
6
4
2
0
50
70
90
30
10
TIME T
O
175
o
C (s)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
STARTING T
J
= 125
o
C
STARTING T
J
= 150
o
C
STARTING T
J
= 100
o
C
STARTING T
J
= 75
o
C
10
8
6
4
2
0
50
70
90
30
10
TIME T
O
175
o
C (s)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
STARTING T
J
= 75
o
C
STARTING T
J
= 125
o
C
STARTING T
J
= 150
o
C
STARTING T
J
= 100
o
C
10
8
6
4
2
0
50
70
90
TIME T
O
175
o
C (s)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
30
10
STARTING T
J
= 100
o
C
STARTING T
J
= 75
o
C
STARTING T
J
= 125
o
C
STARTING T
J
= 150
o
C
10
8
6
4
2
0
50
70
90
TIME T
O
175
o
C (s)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
30
10
STARTING T
J
= 125
o
C
STARTING T
J
= 150
o
C
STARTING T
J
= 75
o
C
STARTING T
J
= 100
o
C
10
8
6
4
2
0
50
70
90
TIME T
O
175
o
C (s)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
30
10
STARTING T
J
= 125
o
C
STARTING T
J
= 150
o
C
STARTING T
J
= 75
o
C
STARTING T
J
= 100
o
C
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE
6-426
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
PSPICE Electrical Model
SUBCKT RLD03N06CLE 2 1 3;
rev 4/18/94
CA 12 8 0.547e-9
CB 15 14 0.547e-9
CIN 6 8 0.301e-9
DBODY 7 5 DBDMOD
DBREAK 5 11 DBKMOD
DESD1 91 9 DESD1MOD
DESD2 91 7 DESD2MOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 20 17 18 66.5
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1
IT 8 17 1
LDRAIN 2 5 1e-9
LGATE 1 9 2.96e-9
LSOURCE 3 7 2.96e-9
MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01
QCONTROL 20 70 7 QMOD 1
RBREAK 17 18 RBKMOD 1
RDRAIN 5 16 RDSMOD 1.123
RGATE 9 20 3200
RIN 6 8 1e9
RSOURCE1 8 70 RDSMOD 1.12
RSOURCE2 70 7 RSMOD 2.16
RVTO 18 19 RVTOMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6 0.22
.MODEL DBDMOD D (IS = 7.97e-17 RS = 1.82 TRS1 = 3.91e-3 TRS2 = 1.24e-5 CJO = 3.00e-10 TT = 1.83e-7)
.MODEL DBKMOD D (RS = 3150 TRS1 =0 TRS2 = 0)
.MODEL DESD1MOD D (BV = 13.54 TBV1 = 0 TBV2 = 0 RS = 45.5 TRS1 = 0 TRS2 = 0)
.MODEL DESD2MOD D (BV = 11.46 TBV1 = -7.576e-4 TBV2 = -3.0e-6 RS = 0 TRS1 = 0 TRS2 = 0)
.MODEL DPLCAPMOD D (CJO = 74.2e-12 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (VTO = 1.67 KP = 3.40 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL QMOD NPN (BF =5)
.MODEL RBKMOD RES (TC1 = 4e-4 TC2 = 1.13e-8)
.MODEL RDSMOD RES (TC1 = 6.80e-3 TC2 = 6.5e-6)
.MODEL RSMOD RES (TC1 = 2.95e-3 TC2 = -1e-6)
.MODEL RVTOMOD RES (TC1 = -2.22e-3 TC2 = -1.95e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3 VOFF = -1)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1 VOFF = -3)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.85 VOFF = 2.15)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.15 VOFF = -2.85)
.ENDS
NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records 1991.
1
GATE
LGATE
RGATE
EVTO
18
8
9
+
DESD1
DESD2
12
13
8
14
13
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS
EDS
R
IN
C
IN
MOS1
MOS2
RDRAIN
DBREAK
EBREAK
DBODY
LDRAIN
DRAIN
RSOURCE2
LSOURCE
SOURCE
RBREAK
RVTO
VBAT
IT
VTO
ESG
DPLCAP
6
6
8
10
5
16
21
11
17
18
8
-
14
5
8
6
8
7
3
17
18
19
91
2
+
+
+
+
+
+
RSOURCE1
70
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE
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