FN8113.0

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-352-6832

Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X4003, X4005

CPU Supervisor

FEATURES

· Selectable watchdog timer

--Select 200ms, 600ms, 1.4s, off

· Low V

detection and reset assertion

--Five standard reset threshold voltages

nominal 4.62V, 4.38V, 2.92V, 2.68V, 1.75V

--Adjust low V

reset threshold voltage using

special programming sequence

--Reset signal valid to V

= 1V

· Low power CMOS

--12µA typical standby current, watchdog on
--800nA typical standby current watchdog off
--3mA active current

· 400kHz I

C interface

· 1.8V to 5.5V power supply operation
· Available packages

--8-lead SOIC
--8-lead MSOP

DESCRIPTION

These devices combine three popular functions,
Power-on Reset Control, Watchdog Timer, and Supply
Voltage Supervision. This combination lowers system
cost, reduces board space requirements, and
increases reliability.

Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.

The Watchdog Timer provides an independent
protection mechanism for microcontrollers. When the
microcontroller fails to restart a timer within a select-
able time out interval, the device activates the
RESET/RESET signal. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.

The device's low V

detection circuitry protects the

user's system from low voltage conditions, resetting the
system when V

falls below the minimum V

trip

point. RESET/RESET is asserted until V

returns to

proper operating level and stabilizes. Five industry stan-
dard V

TRIP

thresholds are available; however, Intersil's

unique circuits allow the threshold to be reprogrammed
to meet custom requirements, or to fine-tune the thresh-
old for applications requiring higher precision.

BLOCK DIAGRAM

Data

Command

Decode &

Control

Logic

SDA

SCL

Reset &

Watchdog

Timebase

Power-on and

Generation

RESET (X4003)

Reset

Low Voltage

Control

Watchdog Transition

Detector

Threshold

Reset logic

RESET (X4005)

TRIP

Watchdog

Timer Reset

Data Sheet

March 15, 2005

FN8113.0

March 15, 2005

PIN CONFIGURATION

PIN DESCRIPTION

SDA

SCL

RESET

8-Pin JEDEC SOIC, MSOP

Pin

(SOIC/DIP)

Pin

TSSOP

Pin

(MSOP)

Name

Function

No internal connections

RESET/

RESET

Reset Output.

RESET/RESET is an active LOW/HIGH, open

drain output which goes active whenever V

falls below the min-

imum V

sense level. It will remain active until V

rises above

the minimum V

sense level for 250ms. RESET/

RESET goes active if the watchdog timer is enabled and SDA re-

mains either HIGH or LOW longer than the selectable Watchdog

time out period. A falling edge of SDA, while SCL also toggles from

HIGH to LOW followed by a stop condition

resets the watchdog timer. RESET/RESET goes active on power-

up and remains active for 250ms after the power supply stabilizes.

Ground

SDA

Serial Data. SDA is a bidirectional pin used to transfer data into

and out of the device. It has an open drain output and may be wire

ORed with other open drain or open collector outputs. This pin re-

quires a pull up resistor and the input buffer is

always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA while

SCL also toggles from HIGH to LOW follow by a stop condition re-

sets the watchdog timer. The absence of this procedure within the

watchdog time out period results in RESET/RESET going active.

SCL

Serial Clock. The serial clock controls the serial bus timing for

data input and output.

Write Protect. WP HIGH prevents changes to the watchdog

timer setting.

Supply voltage

X4003, X4005

FN8113.0

March 15, 2005

PRINCIPLES OF OPERATION

Power-on Reset
Application of power to the X4003/X4005 activates a
power-on reset circuit that pulls the RESET/RESET
pin active. This signal provides several benefits.

It prevents the system microprocessor from starting

to operate with insufficient voltage.

It prevents the processor from operating prior to

stabilization of the oscillator.

It allows time for an FPGA to download its configura-

tion prior to initialization of the circuit.

When V

exceeds the device V

TRIP

threshold value for

200ms (nominal) the circuit releases RESET/RESET,
allowing the system to begin operation.

Low Voltage Monitoring
During operation, the X4003/X4005 monitors the V

level and asserts RESET/RESET if supply voltage falls
below a preset minimum V

TRIP

. The RESET/RESET

signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET

signal remains active until the voltage drops below 1V.
It also remains active until V

returns and exceeds

TRIP

for 200ms.

Watchdog Timer
The watchdog timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to
LOW periodically, while SCL also toggles from HIGH
to LOW (this is a start bit) followed by a stop condition
prior to the expiration of the watchdog time out period
to prevent a RESET/RESET signal. The state of two
nonvolatile control bits in the control register deter-
mine the watchdog timer period. The microprocessor
can change these watchdog bits, or they may be
"locked" by tying the WP pin HIGH.

Figure 1. Watchdog Restart

Set V

TRIP

Level Sequence (V

= desired V

TRIP

value)

THRESHOLD RESET PROCEDURE

The X4003/X4005 is shipped with a standard V

threshold (V

TRIP

) voltage. This value will not change

over normal operating and storage conditions. How-
ever, in applications where the standard V

TRIP

is not

exactly right, or if higher precision is needed in the
V

TRIP

value, the X4003/X4005 threshold may be

adjusted. The procedure is described below, and uses
the application of a nonvolatile control signal.

Setting the V

TRIP

Voltage

This procedure is used to set the V

TRIP

to a higher

voltage value. For example, if the current V

TRIP

is 4.4V

and the new V

TRIP

is 4.6V, this procedure will directly

make the change. If the new setting is to be lower than
the current setting, then it is necessary to reset the trip
point before setting the new value.

SCL

SDA

.6µs

Start

Condition

Stop

Condition

Restart

0 1 2

4 5 6 7

SCL

SDA

A0h

0 1 2 3 4 5 6 7

01h

= 15-18V

0 1 2 3 4 5 6 7

00h

X4003, X4005

FN8113.0

March 15, 2005

To set the new V

TRIP

voltage, apply the desired V

TRIP

threshold voltage to the V

pin and tie the WP pin to

the programming voltage V

. Then write data 00hto

address 01h. The stop bit following a valid write opera-
tion initiates the V

TRIP

programing sequence. Bring WP

LOW to complete the operation.

Resetting the V

TRIP

Voltage

This procedure is used to set the V

TRIP

to a "native"

voltage level. For example, if the current V

TRIP

is 4.4V

and the new V

TRIP

must be 4.0V, then the V

TRIP

must

be reset. When V

TRIP

is reset, the new V

TRIP

is some-

thing less than 1.7V. This procedure must be used to
set the voltage to a lower value.

To reset the new V

TRIP

voltage, apply the desired

TRIP

threshold voltage to the V

pin and tie the WP

pin to the programming voltage V

. Then write 00h to

address 03h. The stop bit of a valid write operation ini-
tiates the V

TRIP

programming sequence. Bring WP

LOW to complete the operation.

Figure 2. Reset V

TRIP

Level Sequence (V

> 3V. WP = 15-18V)

Figure 3. Sample V

TRIP

Reset Circuit

0 1 2 3 4 5 6 7

SCL

SDA

A0h

0 1 2 3 4 5 6 7

03h

= 15 - 18V

0 1 2 3 4 5 6 7

00h

1
2
3
4

8
7
6
5

X4003/05

TRIP

Adj.

RESET/

4.7K

SDA

SCL

µC

Adjust

Run

RESET

X4003, X4005

FN8113.0

March 15, 2005

Figure 4. V

TRIP

Programming Sequence

Control Register
The control register provides the user a mechanism
for changing the watchdog timer settings. watchdog
timer bits are nonvolatile and do not change when
power is removed.

The control register is accessed with a special preamble
in the slave byte (1011) and is located at address 1FFh.
It can only be modified by performing a control register
write operation. Only one data byte is allowed for each
register write operation. Prior to writing to the control reg-
ister, the WEL and RWEL bits must be set using a two
step process, with the whole sequence requiring 3 steps.
See "Writing to the Control Register" below.

The user must issue a stop after sending the control
byte to the register to initiate the nonvolatile cycle that
stores WD1 and WD0. The X4003/X4005 will not
acknowledge any data bytes written after the first byte
is entered.

The state of the control register can be read at any
time by performing a serial read operation. Only one
byte is read by each register read operation. The
X4003/X4005 resets itself after the first byte is read.
The master should supply a stop condition to be con-
sistent with the bus protocol, but a stop is not required
to end this operation.

TRIP

Programming

Apply 5V to V

Decrement V

RESET pin

goes active?

Measured V

TRIP

Desired V

TRIP

DONE

Execute

Sequence

Reset V

TRIP

Set V

= V

Applied =

Desired V

TRIP

Execute

Sequence

Set V

TRIP

New V

Applied =

Old V

applied + Error

= V

- 50mV)

Execute

Sequence

Reset V

TRIP

New V

Applied =

Old V

Applied - Error

Error

Emax

-Emax < Error < Emax

YES

Error

Emax

Emax = Maximum Allowable V

TRIP

Error

WD1 WD0

RWEL

WEL

X4003, X4005

FN8113.0

March 15, 2005

RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to "1" prior to a write to the
control register.

WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the control register
during a write operation. This bit is a volatile latch that
powers up in the LOW (disabled) state. While the WEL
bit is LOW, writes the control register will be ignored
(no acknowledge will be issued after the data byte).
The WEL bit is set by writing a "1" to the WEL bit and
zeroes to the other bits of the control register. Once
set, WEL remains set until either it is reset to 0 (by
writing a "0" to the WEL bit and zeroes to the other bits
of the control register) or until the part powers up
again. Writes to the WEL bit do not cause a nonvolatile
write cycle, so the device is ready for the next opera-
tion immediately after the stop condition.

WD1, WD0: Watchdog Timer Bits
The bits WD1 and WD0 control the period of the
watchdog timer. The options are shown below.

Writing to the Control Register
Changing any of the nonvolatile bits of the control regis-
ter requires the following steps:

Write a 02H to the control register to set the write

enable latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceeded by a start and ended with a stop.)

Write a 06H to the control register to set both the

register write enable latch (RWEL) and the WEL bit.
This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop.)

Write a value to the control register that has all the

control bits set to the desired state. This can be rep-
resented as 0xy0 0010 in binary, where xy are the
WD bits. (Operation preceeded by a start and ended
with a stop.) Since this is a nonvolatile write cycle it
will take up to 10ms to complete. The RWEL bit is
reset by this cycle and the sequence must be
repeated to change the nonvolatile bits again. If bit 2
is set to `1' in this third step (0xy0 0110) then the
RWEL bit is set, but the WD1 and WD0 bits remain
unchanged. Writing a second byte to the control reg-
ister is not allowed. Doing so aborts the write opera-
tion and returns a NACK.

A read operation occurring between any of the previ-

ous operations will not interrupt the register write
operation.

The RWEL bit cannot be reset without writing to the

nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.

To illustrate, a sequence of writes to the device con-
sisting of [02H, 06H, 02H] will reset all of the nonvola-
tile bits in the control register to 0. A sequence of [02H,
06H, 06H] will leave the nonvolatile bits unchanged
and the RWEL bit remains set.

SERIAL INTERFACE

Serial Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this fam-
ily operate as slaves in all applications.

Serial Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 5.

WD1

WD0

Watchdog Time Out Period

1.4 seconds

600 milliseconds

200 milliseconds

Disabled (factory setting)

X4003, X4005

FN8113.0

March 15, 2005

Figure 5. Valid Data Changes on the SDA Bus

Serial Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met. See Figure 6.

Serial Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 6.

Figure 6. Valid Start and Stop Conditions

Serial Acknowledge
Acknowledge is a software convention used to indi-
cate successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 7.

The device will respond with an acknowledge after
recognition of a start condition and the correct con-
tents of the slave address byte. Acknowledge bits are
also provided by the X4003/4005 after correct recep-
tion of the control register address byte, after receiving
the byte written to the control register and after the
second slave address in a read question (See Figure 8
and See Figure 9.)

SCL

Data Stable

Data Change

Data Stable

SDA

SCL

SDA

Start

Stop

X4003, X4005

FN8113.0

March 15, 2005

Figure 7. Acknowledge Response From Receiver

SERIAL WRITE OPERATIONS

Slave Address Byte
Following a start condition, the master must output a
slave address byte. This byte consists of several parts:

a device type identifier that is always `1011'.
two bits of `0'.
one bit of the slave command byte is a R/W bit. The

R/W bit of the slave address byte defines the opera-
tion to be performed. When the R/W bit is a one,
then a read operation is selected. A zero selects a
write operation. Refer to Figure 8.

After loading the entire slave address byte from the

SDA bus, the device compares the input slave byte
data to the proper slave byte. Upon a correct com-
pare, the device outputs an acknowledge on the
SDA line.

Write Control Register
To write to the control register, the device requires the
slave address byte and a byte address. This gives the
master access to register. After receipt of the address

byte, the device responds with an acknowledge, and
awaits the data. After receiving the 8 bits of the data byte,
the device again responds with an acknowledge. The
master then terminates the transfer by generating a stop
condition, at which time the device begins the internal
write cycle to the nonvolatile memory. During this internal
write cycle, the device inputs are disabled, so the device
will not respond to any requests from the master. If WP is
HIGH, the control register cannot be changed. A write to
the control register will suppress the acknowledge bit and
no data in the control register will change. With WP low,
a second byte written to the control register terminates
the operation and no write occurs.

Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending 1 full data byte
plus the subsequent ACK signal. If a stop is issued in
the middle of a data byte, or before 1 full data byte
plus its associated ACK is sent, then the device will
reset itself without performing the write.

Figure 8. Write Control Register Sequence

Data Output

from

Data Output

from Receiver

Start

Acknowledge

SCL from

Master

Slave

Address

Byte

Address

Data

SDA Bus

Signals from

the Slave

Signals from

the Master

Sta

r
t

Stop

X4003, X4005

FN8113.0

March 15, 2005

Serial Read Operations
The read operation allows the master to access the control
register. To conform to the I

C standard, prior to issu-

ing the slave address byte with the R/W bit set to one,
the master must first perform a "dummy" write opera-
tion. The master issues the start condition and the
slave address byte, receives an acknowledge, then
issues the byte address. After acknowledging receipt
of the byte address, the master immediately issues
another start condition and the slave address byte with
the R/W bit set to one. This is followed by an acknowl-
edge from the device and then by the eight bit control
register. The master terminates the read operation by

not responding with an acknowledge and then issuing
a stop condition. Refer to Figure 9 for the address,
acknowledge, and data transfer sequences.

Operational Notes
The device powers-up in the following state:

The device is in the low power standby state.
The WEL bit is set to `0'. In this state it is not possi-

ble to write to the device.

SDA pin is the input mode.
RESET/RESET signal is active for t

PURST

Figure 9. Control Register Read Sequence

Data Protection
The following circuitry has been included to prevent
inadvertent writes:

The WEL bit must be set to allow a write operation.
The proper clock count and bit sequence is required

prior to the stop bit in order to start a nonvolatile
write cycle.

A three step sequence is required before writing into

the control register to change watchdog timer or
block lock settings.

The WP pin, when held HIGH, prevents all writes to

the control register.

Communication to the device is inhibited below the

TRIP

voltage.

Command to change the control register are termi-

nated if in-progress when RESET/RESET go active.

Symbol Table

Slave

Address

Byte

Address

Slave

Address

Data

SDA Bus

Signals from

the Slave

Signals from

the Master

WAVEFORM

INPUTS

OUTPUTS

Must be

steady

Will be

steady

May change

from LOW

to HIGH

Will change

from LOW

to HIGH

May change

from HIGH

to LOW

Will change

from HIGH

to LOW

Don't Care:

Changes

Allowed

Changing:

State Not

Known

N/A

Center Line

is High

Impedance

X4003, X4005

FN8113.0

March 15, 2005

ABSOLUTE MAXIMUM RATINGS

Temperature under bias ................... -65°C to +135°C
Storage temperature ........................ -65°C to +150°C
Voltage on any pin with

respect to V

...................................... -1.0V to +7V

D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds)........ 300°C

COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; the functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Notes: (1) The device enters the active state after any start, and remains active until: 9 clock cycles later if the device select bits in the slave

address byte are incorrect; 200ns after a stop ending a read operation; or t

after a stop ending a write operation.

(2) The device goes into standby: 200ns after any stop, except those that initiate a nonvolatile write cycle; t

after a stop that initiates a

nonvolatile cycle; or 9 clock cycles after any start that is not followed by the correct device select bits in the slave address byte.

(3) V

min. and V

max. are for reference only and are not tested.

Symbol

Parameter

= 1.8 to 3.6V

= 2.7 to 5.5V

Unit

Test Conditions

Min

Max

Min

Max

(1)

Active supply current

read control register

0.5

1.0

SCL

= 400kHz nonvolatile,

SDA = Open

CC2

(1)

Active supply current

write control register

1.5

3.0

CC3

(2)

Operating current AC

(WDT off)

µA

CC4

(2)

Operating current DC

(WDT off)

µA

SDA

= V

SCL

= V

Others = GND or V

CC5

(2)

Operating current DC

(WDT on)

µA

Input leakage current

µA

= GND to V

Output leakage current

µA

SDA

= GND to V

Device is in Standby

(2)

(3)

Input LOW voltage

-0.5

x 0.3

-0.5

x 0.3

(3)

Input HIGH voltage

x 0.7 V

+ 0.5 V

x 0.7 V

+ 0.5

HYS

Schmitt trigger input

hysteresis fixed input level
V

related level

0.2

.05 x V

0.2

.05 x V

Output LOW voltage

0.4

= 3.0mA (2.7-5.5V)

= 1.8mA (1.8-3.6V)

RECOMMENDED OPERATING CONDITIONS

Temperature

Min.

Max.

Commercial

0°C

70°C

Industrial

-40°C

+85°C

Option

Supply Voltage Limits

-1.8

1.8V to 3.6V

-2.7 and -2.7A

2.7V to 5.5V

Blank and -4.5A

4.5V to 5.5V

X4003, X4005

FN8113.0

March 15, 2005

CAPACITANCE (T

= 25°C, f = 1.0 MHz, V

= 5V)

Note:

(4) This parameter is periodically sampled and not 100% tested.

EQUIVALENT A.C. LOAD CIRCUIT

A.C. TEST CONDITIONS

A.C. CHARACTERISTICS

(Continued)

(Over recommended operating conditions, unless otherwise specified)

Notes: (5) Typical values are for T

= 25°C and V

= 5.0V

(6) Cb = total capacitance of one bus line in pF.

Symbol

Parameter

Max.

Unit

Test Conditions

OUT

(4)

Output capacitance (SDA, RESET/RESET)

OUT

= 0V

(4)

Input capacitance (SCL, WP)

= 0V

4.6k

RESET

100pF

SDA

1533

100pF

For V

= 0.4V

and I

= 3 mA

RESET

Input pulse levels

0.1V

to 0.9V

Input rise and fall times

10ns

Input and output timing levels

0.5V

Output load

Standard output load

Symbol

Parameter

100kHz 400kHz

Unit

Min.

Max.

Min.

Max.

SCL

SCL clock frequency

100

400

kHz

Pulse width suppression time at inputs

n/a

SCL LOW to SDA data out valid

0.1

0.9

0.1

0.9

µs

BUF

Time the bus free before start of new transmission

4.7

1.3

µs

LOW

Clock LOW time

4.7

1.3

µs

HIGH

Clock HIGH time

4.0

0.6

µs

SU:STA

Start condition setup time

4.7

0.6

µs

HD:STA

Start condition hold time

4.0

0.6

µs

SU:DAT

Data in setup time

250

100

HD:DAT

Data in hold time

5.0

µs

SU:STO

Stop condition setup time

0.6

µs

Data output hold time

SDA and SCL rise time

1000

20 +.1Cb

(6)

300

SDA and SCL fall time

300

20 +.1Cb

(6)

300

SU:WP

WP setup time

0.4

0.6

µs

HD:WP

WP hold time

µs

Capacitive load for each bus line

400

X4003, X4005

FN8113.0

March 15, 2005

TIMING DIAGRAMS

Bus Timing

WP Pin Timing

Write Cycle Timing

Nonvolatile Write Cycle Timing

Note:

(7) t

is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is

the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.

Symbol

Parameter

Min.

Typ.

(1)

Max.

Unit

(7)

Write cycle time

SU:STO

HIGH

SU:STA

HD:STA

HD:DAT

SU:DAT

SCL

SDA IN

SDA OUT

LOW

BUF

HD:WP

SCL

SDA IN

SU:WP

Clk 1

Clk 9

Slave Address Byte

Start

SCL

SDA

Bit of Last Byte

ACK

Stop

Condition

Start

Condition

X4003, X4005

FN8113.0

March 15, 2005

Power-Up and Power-Down Timing

RESET/RESET Output Timing

Note:

(8) This parameter is periodically sampled and not 100% tested.

SDA vs. RESET/RESET Timing

Symbol

Parameter

Min.

Typ.

Max.

Unit

TRIP

Reset trip point voltage, X4003-4.5A, X4005-4.5A
Reset trip point voltage, X4003, X4005
Reset trip point voltage, X4003-2.7A, X4005-2.7A
Reset trip point voltage, X4003-2.7, X4005-2.7
Reset trip point voltage, X4003-1.8, X4005-1.8

4.5

4.25
2.85
2.55

1.7

4.62
4.38
2.92
2.62
1.75

4.75

4.5
3.0
2.7
1.8

V
V
V

PURST

Power-up reset time out

100

200

400

RPD

(8)

detect to reset/output

500

(8)

fall time

(8)

rise time

0.1

RVALID

Reset valid V

PURST

RPD

RESET

0 Volts

TRIP

RVALID

RESET

SDA

CST

RESET

WDO

RST

WDO

RST

SCL

RESET

X4003, X4005

FN8113.0

March 15, 2005

RESET/RESET Output Timing

TRIP

Programming Timing Diagram

TRIP

Programming Parameters

Symbol

Parameter

Min.

Typ.

Max.

Unit

WDO

Watchdog time out period,

WD1 = 1, WD0 = 1 (factory setting)
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0

100
450

OFF

200
600

1.4

300
800

ms
ms

sec

CST

CS pulse width to reset the watchdog

400

RST

Reset time out

100

200

400

Parameter

Description

Min. Max. Unit

VPS

TRIP

program enable voltage setup time

µs

VPH

TRIP

program enable voltage hold time

µs

TSU

TRIP

setup time

µs

THD

TRIP

hold (stable) time

TRIP

write cycle time

VPO

TRIP

program enable voltage off time (between successive adjustments)

µs

TRIP

program recovery period (between successive adjustments)

Programming voltage

TRAN

TRIP

programmed voltage range

1.7

5.0

ta1

Initial V

TRIP

program voltage accuracy (V

applied - V

TRIP

) (Programmed at 25°C.)

-0.1

+0.4

ta2

Subsequent V

TRIP

program voltage accuracy [(V

applied - V

ta1

) - V

TRIP

Programmed at 25°C.)

-25

+25

TRIP

program voltage repeatability (Successive program operations. Programmed

at 25°C.)

-25

+25

TRIP

program variation after programming (0-75°C). (programmed at 25°C)

-25

+25

TRIP programming parameters are periodically sampled and are not 100% tested.

TRIP

)

TSU

THD

VPH

VPS

TRIP

VPO

SCL

SDA

A0h

01h or 03h

00h

X4003, X4005

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8113.0

March 15, 2005

Ordering Information

Part Mark Information

Range

TRIP

Range

Package

Operating

Temperature Range

Part Number RESET

(Active LOW)

Part Number RESET

(Active HIGH)

4.5-5.5V

4.5-4.75

8L SOIC

0-70°C

X4003S8-4.5A

X4005S8-4.5A

-40-85°C

X4003S8I-4.5A

X4005S8I-4.5A

8L MSOP

-40-85°C

X4003M8I-4.5A

X4005M8I-4.5A

4.5-5.5V

4.25-4.5

8L SOIC

0-70°C

X4003S8

X4005S8

-40-85°C

X4003S8I

X4005S8I

8L MSOP

-40-85°C

X4003M8I

X4005M8I

2.7-5.5V

2.85-3.0

8L SOIC

0-70°C

X4003S8-2.7A

X4005S8-2.7A

-40-85°C

X4003S8I-2.7A

X4005S8I-2.7A

8L MSOP

-40-85°C

X4003M8I-2.7A

X4005M8I-2.7A

2.7-5.5V

2.55-2.7

8L SOIC

0-70°C

X4003S8-2.7

X4005S8-2.7

-40-85°C

X4003S8I-2.7

X4005S8I-2.7

8L MSOP

-40-85°C

X4003M8I-2.7

X4005M8I-2.7

1.8-3.6V

1.7-1.8

8L SOIC

0-70°C

X4003S8-1.8

X4005S8-1.8

8L MSOP

0-70°C

X4003M8-1.8

X4005M8-1.8

8-Lead TSSOP

ACI/ACR = -4.5A (0 to70°C)

EYWW

XXXXX

ACK/ACT = No Suffix (0 to 70°C)

ACM/ACV = -2.7A (0 to 70°C)

ACO/ACX = -2.7 (0 to 70°C)

8-Lead SOIC

X4003/05 X

Blank = 8-Lead SOIC

AG = -1.8 (0 to +70°C)

F = -2.7 (0 to +70°C)
G = -2.7 (-40 to +85°C)

Blank = No Suffix (0 to +70°C)

I = No Suffix (-40 to +85°C)

ACP/ACY = -1.8 (0 to 70°C)

AN = -2.7A (0 to +70°C)
AP = -2.7A (-40 to +85°C)

AL = -4.5A (0 to +70°C)
AM = -4.5A (-171740 to +85°C)

4003/4005

X4003, X4005

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X4003M8I-4.5A

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X4003M8I-4.5A