FN8251.0

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X40430, X40431, X40434, X40435

4Kbit EEPROM

Triple Voltage Monitor with Integrated

CPU Supervisor

FEATURES

· Monitoring voltages: 5V to 9V
· Independent core voltage monitor
· Triple voltage detection and reset assertion

--Standard reset threshold settings. See selec-

tion table on page 2.

--Adjust low voltage reset threshold voltages

using special programming sequence

--Reset signal valid to V

= 1V

--Monitor three separate voltages

· Fault detection register
· Selectable power-on reset timeout

(0.05s, 0.2s, 0.4s, 0.8s)

· Selectable watchdog timer interval

(25ms, 200ms, 1.4s or off)

· Debounced manual reset input
· Low power CMOS

--25µA typical standby current, watchdog on
--6µA typical standby current, watchdog off

· Memory security
· 4Kbits of EEPROM

--16 byte page write mode
--5ms write cycle time (typical)

· Built-in inadvertent write protection

--Power-up/power-down protection circuitry
--Block lock protect 0, or 1/2, of EEPROM

· 400kHz 2-wire interface
· 2.7V to 5.5V power supply operation
· Available packages

--14-lead SOIC, TSSOP

APPLICATIONS

· Communication Equipment

--Routers, Hubs, Switches
--Disk Arrays, Network Storage

· Industrial Systems

--Process Control
--Intelligent Instrumentation

· Computer Systems

--Computers
--Network Servers

DESCRIPTION

The X40430, X40431, X40434, X40435 combines
power-on reset control, watchdog timer, supply voltage
supervision, second and third voltage supervision,
manual reset, and Block Lock

protect serial EEPROM

in one package. This combination lowers system cost,
reduces board space requirements, and increases
reliability.

Applying voltage to V

activates the power-on reset

circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscilla-
tor to stabilize before the processor can execute code.

Low V

detection circuitry protects the user's system

from low voltage conditions, resetting the system
when V

falls below the minimum V

TRIP1

point.

RESET/RESET is active until V

returns to proper

operating level and stabilizes. A second and third volt-
age monitor circuit tracks the unregulated supply to
provide a power fail warning or monitors different
power supply voltage. Three common low voltage
combinations are available. However, Intersil's unique
circuits allows the threshold for either voltage monitor
to be reprogrammed to meet specific system level
requirements or to fine-tune the threshold for applica-
tions requiring higher precision.

A manual reset input provides debounce circuitry for
minimum reset component count.

The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the WDO signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.

The memory portion of the device is a CMOS Serial
EEPROM array with Intersil's Block Lock protection.
The array is internally organized as x 8. The device
features a 2-wire interface and software protocol
allowing operation on an I

C bus.

The device utilizes Intersil's proprietary Direct Write

cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.

Data Sheet

July 29, 2005

FN8251.0

July 29, 2005

BLOCK DIAGRAM

*Voltage monitor requires Vcc to operate. Others are independent of Vcc.

PIN CONFIGURATION

V3FAIL

V2FAIL

WDO

LOWLINE

RESET

X40430/34

X40431/35

V3 Monitor

Logic

V2 Monitor

Logic

Fault Detection

Status

EEPROM

Array

Data

Command

Decode Test

& Control

Logic

Power-on,

Manual Reset

Low Voltage

Reset

Generation

Monitor

Logic

V3MON

V2MON

SDA

SCL

(V1MON)

Watchdog

and

Reset Logic

TRIP3

TRIP2

TRIP1

*X40430, X40431=

V2MON*

V2MON

X40434, X40435 =V

Device

Expected System

Voltages

Vtrip1(V)

Vtrip2(V)

Vtrip3(V)

POR

(system)

X40430, X40431

-A

-B

-C

5V; 3V or 3.3V; 1.8V

5V; 3V; 1.8V

3.3V; 2.5V; 1.8V

2.04.75*

4.554.65*

4.354.45*

2.953.05*

1.704.75

2.852.95

2.552.65

2.152.25

1.704.75

1.651.75

RESET = X40430

RESET = X40431

X40434, X40435

-A

-B

-C

5V; 3.3V; 1.5V

5V; 3V or 3.3V; 1.5V

5V; 3 or 3.3V; 1.2V

2.04.75*

4.554.65*

0.903.50*

1.251.35*

0.951.05*

1.704.75

3.053.15

2.852.95

RESET = X40434

RESET = X40435

V3MON

SDA

SCL

LOWLINE

RESET

V2MON

V3FAIL

WDO

V2FAIL

V3MON

SDA

SCL

V3FAIL

WDO

LOWLINE

RESET

V2MON

V2FAIL

X40430, X40434

X40431, X40435

14-Pin SOIC, TSSOP

PIN DESCRIPTION

Pin

Name

Function

V2FAIL

V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than V

TRIP2

and goes

HIGH when V2MON exceeds V

TRIP2

. There is no power-up reset delay circuitry on this pin.

V2MON

V2 Voltage Monitor Input. When the V2MON input is less than the V

TRIP2

voltage, V2FAIL goes LOW.

This input can monitor an unregulated power supply with an external resistor divider or can monitor a

second power supply with no external components. Connect V2MON to V

when not used. The

V2MON comparator is supplied by V2MON (X40430, X40431) or by the V

input (X40434, X40435).

3 LOWLINE Early Low V

Detect. This CMOS output signal goes LOW when

< V

TRIP1

and goes high when

> V

TRIP1

No connect.

X40430, X40431, X40434, X40435

FN8251.0

July 29, 2005

PRINCIPLES OF OPERATION

Power-on Reset
Applying power to the X40430, X40431, X40434,
X40435 activates a Power-on Reset Circuit that pulls
the RESET/RESET pins active. This signal provides
several benefits.

It prevents the system microprocessor from starting

to operate with insufficient voltage.

It prevents the processor from operating prior to sta-

bilization of the oscillator.

It allows time for an FPGA to download its configura-

tion prior to initialization of the circuit.

It prevents communication to the EEPROM, greatly

reducing the likelihood of data corruption on power-up.

When V

exceeds the device V

TRIP1

threshold value

for t

PURST

(selectable) the circuit releases the RESET

(X40431, X40435) and RESET (X40430, X40434) pin
allowing the system to begin operation.

Figure 1. Connecting a Manual Reset Push-Button

Manual Reset
By connecting a push-button directly from MR to ground,
the designer adds manual system reset capability. The
MR pin is LOW while the push-button is closed and
RESET/RESET pin remains HIGH/LOW until the push-
button is released and for t

PURST

thereafter.

Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will re-

main HIGH/LOW until the pin is released and for the t

PURST

thereafter.

RESET/

RESET

RESET Output. (X40431, X40435) This open drain pin is an active LOW output which goes LOW when-

ever V

falls below V

TRIP1

voltage or if manual reset is asserted. This output stays active for the pro-

grammed time period (t

PURST

) on power-up. It will also stay active until manual reset is released and for

PURST

thereafter.

RESET Output. (X40430, X40434) This pin is an active HIGH CMOS output which goes HIGH when-

ever V

falls below V

TRIP1

voltage or if manual reset is asserted. This output stays active for the pro-

grammed time period (t

PURST

) on power-up. It will also stay active until manual reset is released and for

PURST

thereafter.

Ground

SDA

Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open

drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a

pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW and

followed by a stop condition) restarts the Watchdog timer. The absence of this transition within the

watchdog time out period results in WDO going active.

SCL

Serial Clock. The Serial Clock controls the serial bus timing for data input and output.

Write Protect. WP HIGH prevents writes to any location in the device (including all the registers). It has

an internal pull down resistor (>10M

typical).

V3MON

V3 Voltage Monitor Input. When the V3MON input is less than the V

TRIP3

voltage, V3FAIL goes LOW.

This input can monitor an unregulated power supply with an external resistor divider or can monitor a

third power supply with no external components. Connect V3MON to V

when not used. The

V3MON comparator is supplied by the V3MON input.

V3FAIL

V3 Voltage Fail Output. This open drain output goes LOW when V3MON is less than V

TRIP3

and goes

HIGH when V3MON exceeds V

TRIP3

. There is no power-up reset delay circuitry on this pin.

WDO

WDO Output. WDO is an active LOW, open drain output which goes active whenever the watchdog

timer goes active.

Supply Voltage

PIN DESCRIPTION

(Continued)

Pin

Name

Function

System

Reset

Manual
Reset

X40430, X40434

RESET

X40430, X40431, X40434, X40435

FN8251.0

July 29, 2005

Low Voltage V

(V1 Monitoring)

During operation, the X40430, X40431, X40434,
X40435 monitors the V

level and asserts

RESET/RESET if supply voltage falls below a preset
minimum V

TRIP1

. The RESET/RESET signal prevents

the microprocessor from operating in a power fail or
brownout condition. The RESET/RESET signal
remains active until the voltage drops below 1V. It also
remains active until V

returns and exceeds V

TRIP1

for

PURST

Low Voltage V2 Monitoring
The X40430 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset mini-
mum V

TRIP2

. The V2FAIL signal is either ORed with

RESET to prevent the microprocessor from operating
in a power fail or brownout condition or used to inter-
rupt the microprocessor with notification of an impend-
ing power failure.

For the X40430 and X40431 the V2FAIL signal
remains active until the V2MON drops below 1V
(V2MON

falling). It also remains active until V2MON

returns and exceeds V

TRIP2

. This voltage sense cir-

cuitry monitors the power supply connected to V2MON
pin. If V

= 0, V2MON can still be monitored.

For the X40434 and X40435, the V2FAIL signal
remains active until V

drops below 1V and remains

active until V2MON returns and exceeds V

TRIP2

. This

sense circuitry is powered by V

. If V

= 0, V2MON

cannot be monitored.

Low Voltage V3 Monitoring
The X40430, X40431, X40434, X40435 also monitors
a third voltage level and asserts V3FAIL if the voltage
falls below a preset minimum V

TRIP3

. The V3FAIL sig-

nal is either ORed with RESET to prevent the micro-
processor from operating in a power fail or brownout
condition or used to interrupt the microprocessor with
notification of an impending power failure. The V3FAIL
signal remains active until the V3MON drops below 1V
(V3MON falling). It also remains active until V3MON
returns and exceeds V

TRIP3

This voltage sense circuitry monitors the power supply
connected to V3MON pin. If V

= 0, V3MON can still

be monitored.

Early Low V

Detection (LOWLINE)

This CMOS output goes LOW earlier than
RESET/RESET whenever V

falls below the V

TRIP1

voltage and returns high when V

exceeds the

TRIP1

voltage. There is no power-up delay circuitry

PURST

) on this pin.

Figure 2. Two Uses of Multiple Voltage Monitoring

6-10V

V3MON

X40431-A

Unreg.

Supply

X40431-B

RESET

V2FAIL

System

Reset

V2FAIL

V3FAIL

System

Reset

Notice: No external components required to monitor three voltages.

V3MON

V3FAIL

V2MON

Reg

3.0V

Reg

1.8V

Reg

3.3V

390K

V2MON

RESET

Power

Fail

Interrupt

(1.7V)

X40430, X40431, X40434, X40435

FN8251.0

July 29, 2005

Figure 3. V

TRIPX

Set/Reset Conditions

WATCHDOG TIMER

The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. A
standard read or write sequence to any slave address
byte restarts the watchdog timer and prevents the
WDO signal going active. A minimum sequence to
reset the watchdog timer requires four microprocessor
instructions namely, a Start, Clock Low, Clock High
and Stop. The state of two nonvolatile control bits in
the Status Register determine the watchdog timer
period. The microprocessor can change these watch-
dog bits by writing to the X40430, X40431, X40434,
X40435 control register (also refer to page 20).

Figure 4. Watchdog Restart

V1, V2 AND V3 THRESHOLD PROGRAM
PROCEDURE (OPTIONAL)

The X40430 is shipped with standard V1, V2 and V3
threshold (V

TRIP1,

TRIP2,

TRIP3

) voltages. These

values will not change over normal operating and stor-
age conditions. However, in applications where the
standard thresholds are not exactly right, or if higher
precision is needed in the threshold value, the X40430,
X40431, X40434, X40435 trip points may be adjusted.
The procedure is described below, and uses the appli-
cation of a high voltage control signal.

Setting a V

TRIPx

Voltage (x = 1, 2, 3)

There are two procedures used to set the threshold
voltages (V

TRIPx

), depending if the threshold voltage

to be stored is higher or lower than the present value.
For example, if the present V

TRIPx

is 2.9 V and the

new V

TRIPx

is 3.2 V, the new voltage can be stored

directly into the V

TRIPx

cell. If however, the new setting

is to be lower than the present setting, then it is neces-
sary to "reset" the V

TRIPx

voltage before setting the

new value.

Setting a Higher V

TRIPx

Voltage (x = 1, 2, 3)

To set a V

TRIPx

threshold to a new voltage which is

higher than the present threshold, the user must apply
the desired V

TRIPx

threshold voltage to the corre-

sponding input pin Vcc(V1MON), V2MON or V3MON.
Then, a programming voltage (Vp) must be applied to the
WDO pin before a START condition is set up on SDA.
Next, issue on the SDA pin the Slave Address A0h, fol-
lowed by the Byte Address 01h for V

TRIP1

, 09h for

TRIP2

, and 0Dh for V

TRIP3

, and a 00h Data Byte in order

to program V

TRIPx

. The STOP bit following a valid write

operation initiates the programming sequence. Pin WDO
must then be brought LOW to complete the operation. To
check if the V

TRIPX

has been set, set VXMON to a value

slightly greater than V

TRIPX

(that was previously set).

Slowly ramp down VXMON and observe when the corre-
sponding outputs (LOWLINE, V2FAIL and V3FAIL)
switch. The voltage at which this occurs is the V

TRIPX

(actual).

/V2MON/V3MON

TRIPX

A0h

SCL

WDO

SDA

(X = 1, 2, 3)

00h

SCL

SDA

.6µs

1.3µs

WDT Reset

Start

Stop

X40430, X40431, X40434, X40435

FN8251.0

July 29, 2005

ASE

Now if the desired V

TRIPX

is greater than the V

TRIPX

(actual), then add the difference between V

TRIPX

(desired) V

TRIPX

(actual) to the original V

TRIPX

desired. This is your new V

TRIPX

that should be

applied to VXMON and the whole sequence should be
repeated again (see Figure 5).

ASE

Now if the V

TRIPX

(actual), is higher than the V

TRIPX

(desired), perform the reset sequence as described in
the next section. The new V

TRIPX

voltage to be applied

to VXMON will now be: V

TRIPX

(desired) (V

TRIPX

(actual) V

TRIPX

(desired)).

Note: This operation does not corrupt the memory array.

Setting a Lower V

TRIPx

Voltage (x = 1, 2, 3)

In order to set V

TRIPx

to a lower voltage than the

present value, then V

TRIPx

must first be "reset" accord-

ing to the procedure described below. Once V

TRIPx

has been "reset", then V

TRIPx

can be set to the desired

voltage using the procedure described in "Setting a
Higher V

TRIPx

Voltage".

Resetting the V

TRIPx

Voltage

To reset a V

TRIPx

voltage, apply the programming volt-

age (Vp) to the WDO pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for
V

TRIP1

, 0Bh for V

TRIP2

, and 0Fh for V

TRIP3

, followed

by 00h for the Data Byte in order to reset V

TRIPx

. The

STOP bit following a valid write operation initiates the
programming sequence. Pin WDO must then be
brought LOW to complete the operation.

After being reset, the value of V

TRIPx

becomes a nomi-

nal value of 1.7V or lesser.

Notes: 1. This operation does not corrupt the memory array.

2. Set V

1.5(V2MON or V3MON), when setting

TRIP2

or V

TRIP3

respectively.

CONTROL REGISTER

The Control Register provides the user a mechanism
for changing the Block Lock and Watchdog Timer set-
tings. The Block Lock and Watchdog Timer bits are
nonvolatile and do not change when power is
removed.

The Control Register is accessed with a special pream-
ble in the slave byte (1011) and is located at address
1FFh. It can only be modified by performing a byte write
operation directly to the address of the register and only
one data byte is allowed for each register write opera-
tion. Prior to writing to the Control Register, the WEL
and RWEL bits must be set using a two step process,
with the whole sequence requiring 3 steps. See "Writing
to the Control Registers" on page 7.

The user must issue a stop, after sending this byte to
the register, to initiate the nonvolatile cycle that stores
WD1, WD0, PUP1, PUP0, and BP. The X40430,
X40431, X40434, X40435 will not acknowledge any
data bytes written after the first byte is entered.

The state of the Control Register can be read at any
time by performing a random read at address 1FFh,
using the special preamble. Only one byte is read by
each register read operation. The master should
supply a stop condition to be consistent with the bus
protocol.

RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to "1" prior to a write to the
Control Register.

Figure 5. Sample V

TRIP

Reset Circuit

PUP1 WD1 WD0

RWEL WEL PUP0

1
6
2
7

9
8

X4043X

TRIP1

Adj.

SDA

SCL

µC

Adjust

Run

V2FAIL

TRIP2

Adj.

RESET

X40430, X40431, X40434, X40435

FN8251.0

July 29, 2005

Figure 6. V

TRIPX

Set/Reset Sequence (X = 1, 2, 3)

WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a vola-
tile latch that powers up in the LOW (disabled) state.
While the WEL bit is LOW, writes to any address,
including any control registers will be ignored (no
acknowledge will be issued after the Data Byte). The
WEL bit is set by writing a "1" to the WEL bit and
zeroes to the other bits of the control register.

Once set, WEL remains set until either it is reset to 0
(by writing a "0" to the WEL bit and zeroes to the other
bits of the control register) or until the part powers up
again. Writes to the WEL bit do not cause a high volt-
age write cycle, so the device is ready for the next
operation immediately after the stop condition.

BP: Block Protect Bits (Nonvolatile)
The Block Protect Bit BP, determines which blocks of
the array are write protected. A write to a protected
block of memory is ignored. The block protect bit will
prevent write operations to half or none of the array.

TRIPX

Programming

Apply V

and Voltage

Decrease V

Actual V

TRIPX -

Desired V

TRIPX

DONE

Set Higher V

Sequence

Error < MDE

| Error | < | MDE |

YES

Error > MDE

> Desired V

TRIPX

to V

Desired

Present Value

TRIPX

Execute

YES

Execute

TRIPX

Reset Sequence

Set V

= desired V

TRIPX

New V

applied =

Old V

applied + | Error |

New V

applied =

Old V

applied - | Error |

Execute Reset V

TRIPX

Sequence

Output Switches?

Note: X = 1, 2, 3
Let: MDE = Maximum Desired Error

Vx = V

, VxMON

MDE

Desired Value

MDE

Acceptable

Error Range

Error = Actual - Desired

Protected Addresses

(Size)

Memory Array

Lock

None

100h 1FFh (256 bytes)

Upper Half of

Memory Array

X40430, X40431, X40434, X40435

FN8251.0

July 29, 2005

PUP1, PUP0: Power-up Bits (Nonvolatile)
The Power-up bits, PUP1 and PUP0, determine the

PURST

time delay. The nominal power-up times are

shown in the following table.

WD1, WD0: Watchdog Timer Bits (Nonvolatile)
The bits WD1 and WD0 control the period of the
Watchdog Timer. The options are shown below.

Writing to the Control Registers
Changing any of the nonvolatile bits of the control and
trickle registers requires the following steps:

Write a 02H to the Control Register to set the Write

Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceded by a start and ended with a stop).

Write a 06H to the Control Register to set the

Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation proceeded by a start
and ended with a stop).

Write one byte value to the Control Register that has

all the control bits set to the desired state. The Con-
trol register can be represented as qxys 001r in
binary, where xy are the WD bits, s is the BP bit and
qr are the power-up bits. This operation proceeded
by a start and ended with a stop bit. Since this is a

nonvolatile write cycle it will take up to 10ms (max.)
to complete. The RWEL bit is reset by this cycle and
the sequence must be repeated to change the non-
volatile bits again. If bit 2 is set to `1' in this third step
(qxys 011r) then the RWEL bit is set, but the WD1,
WD0, PUP1, PUP0, and BP bits remain unchanged.
Writing a second byte to the control register is not
allowed. Doing so aborts the write operation and
returns a NACK.

A read operation occurring between any of the previ-

ous operations will not interrupt the register write
operation.

The RWEL bit cannot be reset without writing to the

nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.

To illustrate, a sequence of writes to the device con-
sisting of [02H, 06H, 02H] will reset all of the nonvola-
tile bits in the Control Register to 0. A sequence of
[02H, 06H, 06H] will leave the nonvolatile bits
unchanged and the RWEL bit remains set.

Notes: 1. t

PURST

is set to 200ms as factory default.

2. Watch Dog Timer bits are shipped disabled.

FAULT DETECTION REGISTER

The Fault Detection Register (FDR) provides the user
the status of what causes the system reset active. The
Manual Reset Fail, Watchdog Timer Fail and Three
Low Voltage Fail bits are volatile

The FDR is accessed with a special preamble in the
slave byte (1011) and is located at address 0FFh. It
can only be modified by performing a byte write opera-
tion directly to the address of the register and only one
data byte is allowed for each register write operation.

There is no need to set the WEL or RWEL in the
control register to access this FDR.

Figure 7. Valid Data Changes on the SDA Bus

PUP1 PUP0

Power-on Reset Delay (

PURST

)

50ms

200ms (factory setting)

400ms

800ms

WD1

WD0

Watchdog Time Out Period

1.4 seconds

200 milliseconds

25 milliseconds

disabled (factory setting)

LV1F LV2F LV3F WDF MRF

SCL

SDA

Data Stable

Data Change

Data Stable

X40430, X40431, X40434, X40435

FN8251.0

July 29, 2005

At power-up, the FDR is defaulted to all "0". The sys-
tem needs to initialize this register to all "1" before the
actual monitoring can take place. In the event of any
one of the monitored sources fail. The corresponding
bit in the register will change from a "1" to a "0" to indi-
cate the failure. At this moment, the system should
perform a read to the register and note the cause of
the reset. After reading the register the system should
reset the register back to all "1" again. The state of the
FDR can be read at any time by performing a random
read at address 0FFh, using the special preamble.

The FDR can be read by performing a random read at
0FFh address of the register at any time. Only one
byte of data is read by the register read operation.

MRF, Manual Reset Fail Bit (Volatile)
The MRF bit will be set to "0" when Manual Reset
input goes active.

WDF, Watchdog Timer Fail Bit (Volatile)
The WDF bit will be set to "0" when the WDO goes
active.

LV1F, Low V

Reset Fail Bit (Volatile)

The LV1F bit will be set to "0" when V

(V1MON)

falls below V

TRIP1

LV2F, Low V2MON Reset Fail Bit (Volatile)
The LV2F bit will be set to "0" when V2MON falls
below V

TRIP2

LV3F, Low V3MON Reset Fail Bit (Volatile)
The LV3F bit will be set to "0" when the V3MON falls
below V

TRIP3

SERIAL INTERFACE

Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this fam-
ily operate as slaves in all applications.

Serial Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 7.

Serial Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met. See Figure 8.

Serial Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 8.

Figure 8. Valid Start and Stop Conditions

SCL

SDA

Start

Stop

X40430, X40431, X40434, X40435

FN8251.0

July 29, 2005

Serial Acknowledge
Acknowledge is a software convention used to indi-
cate successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. See Figure 9.

The device will respond with an acknowledge after
recognition of a start condition and if the correct
Device Identifier and Select bits are contained in the
Slave Address Byte. If a write operation is selected,
the device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for the Slave Address Byte when the Device
Identifier and/or Select bits are incorrect.

In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not

detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.

Serial Write Operations

Byte Write
For a write operation, the device requires the Slave
Address Byte and a Word Address Byte. This gives
the master access to any one of the words in the
array. After receipt of the Word Address Byte, the
device responds with an acknowledge, and awaits the
next eight bits of data. After receiving the 8 bits of the
Data Byte, the device again responds with an
acknowledge. The master then terminates the transfer
by generating a stop condition, at which time the
device begins the internal write cycle to the nonvolatile
memory. During this internal write cycle, the device
inputs are disabled, so the device will not respond to any
requests from the master. The SDA output is at high
impedance. See Figure 10.

A write to a protected block of memory will suppress
the acknowledge bit.

Figure 9. Acknowledge Response From Receiver

Figure 10. Byte Write Sequence

Data Output from

Transmitter

Data Output

from Receiver

Start

Acknowledge

SCL from

Master

Slave

Address

Byte

Address

Data

SDA Bus

Signals from

the Slave

Signals from

the Master

X40430, X40431, X40434, X40435

FN8251.0

July 29, 2005

Page Write
The device is capable of a page write operation. It is
initiated in the same manner as the byte write opera-
tion; but instead of terminating the write cycle after the
first data byte is transferred, the master can transmit
an unlimited number of 8-bit bytes. After the receipt of
each byte, the device will respond with an acknowl-
edge, and the address is internally incremented by
one. The page address remains constant. When the
counter reaches the end of the page, it "rolls over" and
goes back to `0' on the same page.

This means that the master can write 16 bytes to the
page starting at any location on that page. If the mas-
ter begins writing at location 10, and loads 12 bytes,
then the first 6 bytes are written to locations 10
through 15, and the last 6 bytes are written to locations
0 through 5. Afterwards, the address counter would
point to location 6 of the page that was just written. If
the master supplies more than 16 bytes of data, then
new data overwrites the previous data, one byte at a
time.

The master terminates the Data Byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation,
all inputs are disabled until completion of the internal
write cycle. See Figure 11 for the address, acknowl-
edge, and data transfer sequence.

Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte plus the subsequent ACK signal. If a stop is
issued in the middle of a data byte, or before 1 full
data byte plus its associated ACK is sent, then the
device will reset itself without performing the write. The
contents of the array will not be effected.

Acknowledge Polling
The disabling of the inputs during high voltage cycles
can be used to take advantage of the typical 5ms write
cycle time. Once the stop condition is issued to indi-
cate the end of the master's byte load operation, the
device initiates the internal high voltage cycle.
Acknowledge polling can be initiated immediately. To
do this, the master issues a start condition followed by
the Slave Address Byte for a write or read operation. If
the device is still busy with the high voltage cycle then
no ACK will be returned. If the device has completed
the write operation, an ACK will be returned and the
host can then proceed with the read or write operation.
See Figure 13.

Serial Read Operations
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Ran-
dom Reads, and Sequential Reads.

Figure 11. Page Write Operation

Figure 12. Writing 12 bytes to a 16-byte page starting at location 10.

Slave

Address

Byte

Address

Data

(n)

SDA Bus

Signals from

the Slave

Signals from

the Master

Data

(1)

16)

1 0 1 0

address

5 Bytes

n-1

7 Bytes

address

= 6

address pointer
ends here

Addr = 7

X40430, X40431, X40434, X40435

FN8251.0

July 29, 2005

Current Address Read
Internally the device contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power-up, the address of the
address counter is undefined, requiring a read or write
operation for initialization.

Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an acknowledge and
then transmits the eight bits of the Data Byte. The
master terminates the read operation when it does not
respond with an acknowledge during the ninth clock
and then issues a stop condition. See figure 15 for the
address, acknowledge, and data transfer sequence.

Figure 13. Acknowledge Polling Sequence

It should be noted that the ninth clock cycle of the read
operation is not a "don't care." To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.

Random Read
Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master
must first perform a "dummy" write operation. The master
issues the start condition and the Slave Address Byte,
receives an acknowledge, then issues the Word Address
Bytes. After acknowledging receipts of the Word Address
Bytes, the master immediately issues another start con-
dition and the Slave Address Byte with the R/W bit set to
one. This is followed by an acknowledge from the device
and then by the eight bit word. The master terminates the
read operation by not responding with an acknowledge
and then issuing a stop condition. See Figure 16 for the
address, acknowledge, and data transfer sequence.

A similar operation called "Set Current Address" where
the device will perform this operation if a stop is issued
instead of the second start shown in Figure 15. The
device will go into standby mode after the stop and all
bus activity will be ignored until a start is detected.
This operation loads the new address into the address
counter. The next Current Address Read operation will
read from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.

Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicat-
ing it requires additional data. The device continues to
output data for each acknowledge received. The master
terminates the read operation by not responding with an
acknowledge and then issuing a stop condition.

The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments through
all page and column addresses, allowing the entire
memory contents to be serially read during one opera-
tion. At the end of the address space the counter "rolls
over" to address 0000h and the device continues to out-
put data for each acknowledge received. See Figure 17
for the acknowledge and data transfer sequence.

ACK

Returned?

Issue Slave Address
Byte (Read or Write)

Byte Load Completed

by Issuing STOP.

Enter ACK Polling

Issue STOP

Issue START

YES

High Voltage Cycle

Complete. Continue

Command Sequence?

Issue STOP

Continue Normal

Read or Write

Command Sequence

PROCEED

YES

X40430, X40431, X40434, X40435

FN8251.0

July 29, 2005

SERIAL DEVICE ADDRESSING

Memory Address Map
CR, Control Register, CR7: CR0
Address: 1FF

hex

FDR, Fault DetectionRegister, FDR7: FDR0
Address: 0FF

hex

General Purpose Memory Organization, A8:A0
Address: 000h to 1FFh

General Purpose Memory Array Configuration

Slave Address Byte
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several parts:

a device type identifier that is always `101x'. Where

x = 0 is for Array, x = 1 is for Control Register or
Fault Detection Register.

next two bits are `0'.
next bit that becomes the MSB of the address.

Figure 14. X40430, X40431, X40434, X40435
Addressing

last bit of the slave command byte is a R/W bit. The

R/W bit of the Slave Address Byte defines the oper-
ation to be performed. When the R/W bit is a one,
then a read operation is selected. A zero selects a
write operation.

Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is undefined on a power-up condition.

Operational Notes
The device powers-up in the following state:

The device is in the low power standby state.
The WEL bit is set to `0'. In this state it is not possi-

ble to write to the device.

SDA pin is the input mode.
RESET/RESET Signal is active for

PURST

Data Protection
The following circuitry has been included to prevent
inadvertent writes:

The WEL bit must be set to allow write operations.
The proper clock count and bit sequence is required

prior to the stop bit in order to start a nonvolatile
write cycle.

A three step sequence is required before writing into

the Control Register to change Watchdog Timer or
Block Lock settings.

The WP pin, when held HIGH, prevents all writes to

the array and all the Register.

Figure 15. Current Address Read Sequence

Memory Address

A8:A0

000h

0FFh

100h

1FFh

Lower 256 bytes

Upper 256 bytes

Block Protect Option

General Purpose Memory
Control Register
Fault Detection Register

1
1

0
0

1
1

0
1

A8 R/W

Word Address

Slave Byte

1
0

0
0
0

R/W
R/W

General Purpose Memory
Control Register
Fault Detection Register

A6 A5 A4

A1 A0

A3 A2

1
1

Slave

Address

Data

SDA Bus

Signals from

the Slave

Signals from

the Master

1 0 1 0

X40430, X40431, X40434, X40435

FN8251.0

July 29, 2005

ABSOLUTE MAXIMUM RATINGS

Temperature under bias .................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on any pin with

respect to V

...................................... -1.0V to +7V

D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds)........ 300°C

COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

*See Ordering Info

Temperature

Min.

Max.

Commercial

0°C

70°C

Industrial

-40°C

+85°C

Version

Chip Supply

Voltage

Monitored*

Voltages

X40430, X40431

2.7V to 5.5V

1.7V to 5.5V

X40434, X40435

2.7V to 5.5V

1.0V to 5.5V

D.C. OPERATING CHARACTERISTICS

(Over the recommended operating conditions unless otherwise specified)

Symbol

Parameter

Min

Typ

(4)

Max

Unit

Test Conditions

CC1

(1)

Active Supply Current (

) Read

1.5

x 0.1

x 0.9,

SCL

= 400kHz

CC2

(1)

Active Supply Current (

) Write

3.0

SB1

(1)(6)

Standby Current (

) AC (WDT off)

µA

x 0.1

VIH =

x 0.9

SCL

, f

SDA

= 400kHz

SB2

(2)(6)

Standby Current (

) DC (WDT on)

µA

SDA

= V

SCL

= V

Others = GND or V

Input Leakage Current (SCL, MR,

WP)

µA

= GND to

Output Leakage Current (SDA,

V2FAIL, V3FAIL, WDO, RESET)

µA

SDA

= GND to

Device is in Standby

(2)

(3)

Input LOW Voltage (SDA, SCL, MR,

WP)

-0.5

x 0.3

(3)

Input HIGH Voltage (SDA, SCL, MR,

WP)

x 0.7

+ 0.5

HYS

(6)

Schmitt Trigger Input Hysteresis
· Fixed input level
·

related level

0.2

.05 x

V
V

Output LOW Voltage (SDA, RE-

SET/RESET, LOWLINE, V2FAIL,

V3FAIL, WDO)

0.4

= 3.0mA (2.7-5.5V)

= 1.8mA (2.7-3.6V)

Output (RESET, LOWLINE) HIGH

Voltage

0.8

0.4

= -1.0mA (2.7-5.5V)

= -0.4mA (2.7-3.6V)

X40430, X40431, X40434, X40435

FN8251.0

July 29, 2005

Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave

Address Byte are incorrect; 200ns after a stop ending a read operation; or t

after a stop ending a write operation.

(2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; t

after a stop that initiates a high

voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte.

(3) V

Min. and V

Max. are for reference only and are not tested.

(4) At 25°C, V

= 3V

(5) See ordering information for standard programming levels. For custom programmed levels, contact factory.
(6) Based on characterization data.

EQUIVALENT INPUT CIRCUIT FOR VxMON (x = 1, 2, 3)

CAPACITANCE

Supply

TRIP1

(5)

Trip Point Voltage Range

2.0

4.75

4.55

4.6

4.65

X40430, X40431-A, X40434,

X40435

4.35

4.4

4.45

X40430, X40431-B

2.85

2.9

2.95

X40430, X40431-C

Second Supply Monitor

V2MON Current

µA

TRIP2

(5)

V2MON Trip Point Voltage Range

1.7
0.9

4.75

3.5

V
V

x40430, X40431
x40434, X40435

2.85

2.9

2.95

X40430, X40431-A

2.55

2.6

2.65

X40430, X40431-B

2.15

2.2

2.25

X40430, X40431-C

1.25

1.3

1.35

X40434, X40435-A&B

0.95

1.0

1.05

X40434, X40435-C

RPD2

(6)

TRIP2

to V2FAIL

µs

Third Supply Monitor

V3MON Current

µA

TRIP3

(5)

V3MON Trip Point Voltage Range

1.7

4.75

1.65

1.7

1.75

X40430, X40431

3.05

3.1

3.15

X40434, X40435-A

2.85

2.9

2.95

X40434, X40435-B&C

RPD3

(6)

TRIP3

to V3FAIL

µs

D.C. OPERATING CHARACTERISTICS

(Continued)

(Over the recommended operating conditions unless otherwise specified)

Symbol

Parameter

Min

Typ

(4)

Max

Unit

Test Conditions

REF

RPDX

= 5µs worst case

Output Pin

VxMON

V = 100mV

ref

Symbol

Parameter

Max

Unit

Test Conditions

OUT

(1)

Output Capacitance (SDA, RESET/RESET, LOWLINE,

V2FAIL,V3FAIL, WDO)

OUT

= 0V

(1)

Input Capacitance (SCL, WP, MR) 6

= 0V

Note:

(1) This parameter is not 100% tested.

X40430, X40431, X40434, X40435

FN8251.0

July 29, 2005

EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR
V

= 5V

A.C. TEST CONDITIONS

SYMBOL TABLE

A.C. CHARACTERISTICS

Note:

(1) Cb = total capacitance of one bus line in pF.

Input pulse levels

x 0.1 to

x 0.9

Input rise and fall times

10ns

Input and output timing levels

x 0.5

Output load

Standard output load

SDA

30pF

V2MON, V3MON

4.6k

RESET

30pF

2.06k

V2FAIL,

4.6k

30pF

WDO

V3FAIL

Must be

steady

Will be

steady

May change

from LOW

Will change

from LOW

to HIGH

May change

from HIGH

to LOW

Will change

from HIGH

to LOW

Don't Care:

Changes

Allowed

Changing:

State Not

Known

N/A

Center Line

is High

Impedance

WAVEFORM

INPUTS

OUTPUTS

to HIGH

Symbol

Parameter

Min

Max

Unit

SCL

SCL Clock Frequency

400

kHz

Pulse width Suppression Time at inputs

SCL LOW to SDA Data Out Valid

0.1

0.9

µs

BUF

Time the bus free before start of new transmission

1.3

µs

LOW

Clock LOW Time

1.3

µs

HIGH

Clock HIGH Time

0.6

µs

SU:STA

Start Condition Setup Time

0.6

µs

HD:STA

Start Condition Hold Time

0.6

µs

SU:DAT

Data In Setup Time

100

HD:DAT

Data In Hold Time

µs

SU:STO

Stop Condition Setup Time

0.6

µs

Data Output Hold Time

SDA and SCL Rise Time

20 +.1Cb

(1)

300

SDA and SCL Fall Time

20 +.1Cb

(1)

300

SU:WP

WP Setup Time

0.6

µs

HD:WP

WP Hold Time

µs

Capacitive load for each bus line

400

X40430, X40431, X40434, X40435

FN8251.0

July 29, 2005

TIMING DIAGRAMS

Bus Timing

WP Pin Timing

Write Cycle Timing

Nonvolatile Write Cycle Timing

Note:

(1) t

is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is

the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.

SU:STO

HIGH

SU:STA

HD:STA

HD:DAT

SU:DAT

SCL

SDA IN

SDA OUT

LOW

BUF

HD:WP

SCL

SDA IN

SU:WP

Clk 1

Clk 9

Slave Address Byte

START

SCL

SDA

Bit of Last Byte

ACK

Stop

Condition

Start

Condition

Symbol

Parameter

Min

Typ

Max

Unit

(1)

Write Cycle Time

X40430, X40431, X40434, X40435

FN8251.0

July 29, 2005

Power Fail Timings

RESET/RESET/MR Timings

V2MON or

V2FAIL or

RPDX

RVALID

V3MON

V3FAIL

LOWLINE or

TRIPX

RPDX

RPDL

X = 2, 3

[

]

[

]

LOW VOLTAGE AND WATCHDOG TIMINGS PARAMETERS (@25°C, V

= 5V)

Symbol

Parameters

Min

Typ

(1)

Max

Unit

RPD1

(2)

RPDL

TRIP1

to RESET/RESET (Power-down only)

TRIP1

to LOWLINE

µs

LOWLINE to RESET/RESET delay (Power-down only) [= t

RPD1

-t

RPDL

]

500

RPDX

(2)

TRIP2

to V2FAIL, or V

TRIP3

to V3FAIL (x = 2, 3)

µs

PURST

Power-on Reset delay:

PUP1 = 0, PUP0 = 0

PUP1 = 0, PUP0 = 1 (factory setting)

PUP1 = 1, PUP0 = 0

PUP1 = 1, PUP0 = 1

(2)

200

400

(2)

800

(2)

CC,

V2MON

V3MON

Fall Time

µs

CC,

V2MON

V3MON

Rise Time

µs

RVALID

Reset Valid V

(2)

MR to RESET/ RESET delay (activation only)

500

TRIP1

RESET

PURST

RPD1

RVALID

IN1

X40430, X40431, X40434, X40435

FN8251.0

July 29, 2005

Notes: (1) V

= 5V at 25°C.

(2) Values based on characterization data only.

Watchdog Time Out For 2-Wire Interface

in1

Pulse width for MR

µs

WDO

Watchdog Timer Period:

WD1 = 0, WD0 = 0

WD1 = 0, WD0 = 1

WD1 = 1, WD0 = 0

WD1 = 1, WD0 = 1 (factory setting)

1.4

(2)

200

(2)

OFF

RST1

Watchdog Reset Time Out Delay

WD1 = 0, WD0 = 0

WD1 = 0, WD0 = 1

100

200

300

RST2

Watchdog Reset Time Out Delay WD1 = 1, WD0 = 0

12.5

37.5

RSP

Watchdog timer restart pulse width

µs

LOW VOLTAGE AND WATCHDOG TIMINGS PARAMETERS (@25°C, V

= 5V)

(CONTINUED)

Symbol

Parameters

Min

Typ

(1)

Max

Unit

< t

WDO

RST

WDO

SDA

Start

WDO

RST

SCL

Start

RSP

WDT

Restart

Start

SDA

SCL

Minimum Sequence to Reset WDT

Clockin (0 or 1)

X40430, X40431, X40434, X40435

FN8251.0

July 29, 2005

TRIPX

Set/Reset Conditions

TRIP1

, V

TRIP2

, V

TRIP3

Programming Specifications: V

= 2.0 - 5.5V; Temperature = 25°C

Parameter

Description

Min.

Max.

Unit

VPS

WDO Program Voltage Setup time

µs

VPH

WDO Program Voltage Hold time

µs

TSU

TRIPX

Level Setup time

µs

THD

TRIPX

Level Hold (stable) time

µs

TRIPX

Program Cycle

VPO

Program Voltage Off time before next cycle

Programming Voltage

TRAN1

TRIP1

Set Voltage Range

2.0

4.75

TRAN2

TRIP2

Set Voltage Range X40430, X40431

1.7

4.75

TRAN2A

TRIP2

Set to Voltage Range X40434, X40435

0.9

3.5

TRAN3

TRIP3

Set Voltage Range

1.7

4.75

TRIPX

Set Voltage variation after programming (-40 to +85°C).

-25

+25

VPS

WDO Program Voltage Setup time

µs

SCL

SDA

/V2MON/V3MON

TRIPX

)

WDO

TSU

THD

VPH

VPS

VPO

A0h

*0Dh

sets V

TRIP1

sets V

TRIP2

sets V

TRIP3

*01h
*09h

*03h
*0Bh
*0Fh

resets V

TRIP3

resets V

TRIP2

resets V

TRIP1

Start

* all others reserved

00h

X40430, X40431, X40434, X40435

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8251.0

July 29, 2005

ORDERING INFORMATION

PART MARK INFORMATION

Monitored

Supplies

TRIP1

Range

TRIP2

Range

TRIP3

Range

Package

Operating

Temperature

Range

Part Number

with RESET

Part Number

with RESET

1.7-5.5

4.6V±50mV 2.9V±50mV 1.7V±50mV

14L SOIC

0°C70°C

X40430S14-A

X40431S14-A

-40°C85°C

X40430S14I-A

X40431S14I-A

14L TSSOP

0°C70°C

X40430V14-A

X40431V14-A

-40°C85°C

X40430V14I-A

X40431V14I-A

1.7-5.5

4.4V±50mV 2.6V±50mV 1.7V±50mV

14L SOIC

0°C70°C

X40430S14-B

X40431S14-B

-40°C85°C

X40430S14I-B

X40431S14I-B

14L TSSOP

0°C70°C

X40430V14-B

X40431V14-B

-40°C85°C

X40430V14I-B

X40431V14I-B

1.7-3.6

2.9V±50mV 2.2V±50mV 1.7V±50mV

14L SOIC

0°C70°C

X40430S14-C

X40431S14-C

-40°C85°C

X40430S14I-C X40431S14I-C

14L TSSOP

0°C70°C

X40430V14-C

X40431V14-C

-40°C85°C

X40430V14I-C X40431V14I-C

1.3-5.5

4.6V±50mV 1.3V±50mV 3.1V±50mV

14L SOIC

0°C70°C

X40434S14-A

X40435S14-A

-40°C85°C

X40434S14I-A

X40435S14I-A

14L TSSOP

0°C70°C

X40434V14-A

X40435V14-A

-40°C85°C

X40434V14I-A

X40435V14I-A

1.3-5.5

4.6V±50mV 1.3V±50mV 2.9V±50mV

14L SOIC

0°C70°C

X40434S14-B

X40435S14-B

-40°C85°C

X40434S14I-B

X40435S14I-B

14L TSSOP

0°C70°C

X40434V14-B

X40435V14-B

-40°C85°C

X40434V14I-B

X40435V14I-B

1.0-5.5

4.6V±50mV 1.0V±50mV 2.9V±50mV

14L SOIC

0°C70°C

X40434S14-C

X40435S14-C

-40°C85°C

X40434S14I-C X40435S14I-C

14L TSSOP

0°C70°C

X40434V14-C

X40435V14-C

-40°C85°C

X40434V14I-C X40435V14I-C

14-Lead Package

X4043XX

YYWWXX

I Industrial

0/1/4/5

Package - S/V

Blank Commercial

WW Workweek

YY Year

A, B, or C

X40430, X40431, X40434, X40435

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X40431V14I-C

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X40431V14I-C