FN8118.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X4043, X4045

4k, 512 x 8 Bit

CPU Supervisor with 4kbit EEPROM

FEATURES

· Selectable watchdog timer
· Low V

detection and reset assertion

--Five standard reset threshold voltages
--Adjust low V

reset threshold voltage using

special programming sequence

--Reset signal valid to V

= 1V

· Low power CMOS

--<20µA max standby current, watchdog on
--<1µA standby current, watchdog OFF
--3mA active current

· 4kbits of EEPROM

--16-byte page write mode
--Self-timed write cycle
--5ms write cycle time (typical)

· Built-in inadvertent write protection

--Power-up/power-down protection circuitry
--Protect 0, 1/4, 1/2, all or 16, 32, 64 or 128 bytes

of EEPROM array with Block Lock

protection

· 400kHz 2-wire interface
· 2.7V to 5.5V power supply operation
· Available packages

--8 Ld SOIC
--8 Ld MSOP
--8 Ld PDIP

· Pb-free plus anneal available (RoHS compliant)

DESCRIPTION

The X4043/45 combines four popular functions,
Power-on Reset Control, Watchdog Timer, Supply
Voltage Supervision, and Block Lock Protect Serial
EEPROM Memory in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.

Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.

The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the
RESET/RESET signal. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.

The device's low V

detection circuitry protects the

user's system from low voltage conditions, resetting the
system when V

falls below the minimum V

trip

point. RESET/RESET is asserted until V

returns to

proper operating level and stabilizes. Five industry stan-
dard V

TRIP

thresholds are available, however, Intersil's

unique circuits allow the threshold to be reprogrammed
to meet custom requirements or to fine-tune the thresh-
old for applications requiring higher precision.

BLOCK DIAGRAM

Watchdog

Timer Reset

Data

Command

Decode &

Control

Logic

SDA

SCL

Reset &

Watchdog

Timebase

Power-on and

Generation

TRIP

RESET (X4043)

Reset

Low Voltage

Status

Protect Logic

EEPROM Array

Watchdog Transition

Detector

Threshold

Reset logic

Blo

c
k Lock C

ontrol

2Kbits

1Kb

1
Kb

RESET (X4045)

Data Sheet

September 30, 2005

FN8118.1

September 30, 2005

Ordering Information

PART NUMBER RESET

(ACTIVE LOW)

PART

MARKING

PART NUMBER

RESET (ACTIVE HIGH)

PART

MARKING

RANGE (V)

TRIP

RANGE (V)

TEMP

RANGE (°C)

PACKAGE

X4043S8-4.5A

X4043 AL

X4045S8-4.5A

X4045 AL

4.5-5.5

4.5-4.75

0-70

8 Ld SOIC

X4043S8Z-4.5A (Note)

X4043 Z AL

X4045S8Z-4.5A (Note) X4045 Z AL

0-70

8 Ld SOIC (Pb-free)

X4043S8I-4.5A

X4043 AM

X4045S8I-4.5A

X4045 AM

-40-85

8 Ld SOIC

X4043S8IZ-4.5A (Note) X4043 Z AM X4045S8IZ-4.5A (Note) X4045 Z AM

-40-85

8 Ld SOIC (Pb-free)

X4043M8-4.5A

ADA

X4045M8-4.5A

ADJ

0-70

8 Ld MSOP

X4043M8Z-4.5A (Note) DAZ

X4045M8Z-4.5A (Note) DBH

0-70

8 Ld MSOP (Pb-free)

X4043M8I-4.5A

ADB

X4045M8I-4.5A

ADK

-40-85

8 Ld MSOP

X4043M8IZ-4.5A (Note) DAU

X4045M8IZ-4.5A (Note) DBE

-40-85

8 Ld MSOP (Pb-free)

X4043P-4.5A

X4043P AL

X4045PZ-4.5A (Note)

X4045P Z AL

0-70

8 Ld PDIP

X4043PZ-4.5A (Note)

X4043P Z AL X4045P-4.5A

X4045P AL

0-70

8 Ld PDIP (Pb-free)

X4043PI-4.5A

X4043P AM

X4045PI-4.5A

X4045P AM

-40-85

8 Ld PDIP

X4043PIZ-4.5A (Note)

X4043P Z AM X4045PIZ-4.5A (Note)

X4045P Z AM

-40-85

8 Ld PDIP (Pb-free)

X4043S8*

X4043

X4045S8*

X4045

4.5-5.5

4.25-4.5

0-70

8 Ld SOIC

X4043S8Z* (Note)

X4043 Z

X4045S8Z* (Note)

X4045 Z

0-70

8 Ld SOIC (Pb-free)

X4043S8I*

X4043 I

X4045S8I

X4045 I

-40-85

8 Ld SOIC

X4043S8IZ* (Note)

X4043 Z I

X4045S8IZ (Note)

X4045 Z I

-40-85

8 Ld SOIC (Pb-free)

X4043M8

ADC

X4045M8

ADL

0-70

8 Ld MSOP

X4043M8Z* (Note)

DAW

X4045M8Z (Note)

0-70

8 Ld MSOP (Pb-free)

X4043M8I

ADD

X4045M8I

ADM

-40-85

8 Ld MSOP

X4043M8IZ (Note)

DAR

X4045M8IZ (Note)

DBA

-40-85

8 Ld MSOP (Pb-free)

X4043P

X4043P Z

X4045P

0-70

8 Ld PDIP

X4043PZ (Note)

X4043P

X4045PZ (Note)

X4045P Z

0-70

8 Ld PDIP (Pb-free)

X4043PI

X4043P I

X4045PI

X4045P I

-40-85

8 Ld PDIP

X4043PIZ (Note)

X4043P Z I

X4045PIZ (Note)

X4045P Z I

-40-85

8 Ld PDIP (Pb-free)

X4043S8-2.7A*

X4043 AN

X4045S8-2.7A

X4045 AN

2.7-5.5

2.85-3.0

8 Ld SOIC

X4043S8Z-2.7A* (Note) X4043 Z AN

X4045S8Z-2.7A (Note) X4045 Z AN

8 Ld SOIC (Pb-free)

X4043S8I-2.7A*

X4043 AP

X4045S8I-2.7A

X4045 AP

-40-85

8 Ld SOIC

X4043S8IZ-2.7A* (Note) X4043 Z AP

X4045S8IZ-2.7A (Note) X4045 Z AP

-40-85

8 Ld SOIC (Pb-free)

X4043M8-2.7A

ADE

X4045M8-2.7A

AND

0-70

8 Ld MSOP

X4043M8Z-2.7A (Note) DAY

X4045M8Z-2.7A (Note) DBG

0-70

8 Ld MSOP (Pb-free)

X4043M8I-2.7A

ADF

X4045M8I-2.7A

ADO

-40-85

8 Ld MSOP

X4043M8IZ-2.7A (Note) DAT

X4045M8IZ-2.7A (Note) DBC

-40-85

8 Ld MSOP (Pb-free)

X4043P-2.7A

X4043P AN

X4045P-2.7A

X4045P AN

0-70

8 Ld PDIP

X4043PZ-2.7A (Note)

X4043P Z AN X4045PZ-2.7A (Note)

X4045P Z AN

0-70

8 Ld PDIP (Pb-free)

X4043PI-2.7A

X4043P AP

X4045PI-2.7A

X4045P AP

-40-85

8 Ld PDIP

X4043PIZ-2.7A (Note)

X4043P Z AP X4045PIZ-2.7A (Note)

X4045P Z AP

-40-85

8 Ld PDIP (Pb-free)

X4043, X4045

FN8118.1

September 30, 2005

X4043S8-2.7*

X4043 F

X4045S8-2.7*

X4045 F

2.7-5.5

2.55-2.7

0-70

8 Ld SOIC

X4043S8Z-2.7* (Note)

X4043 Z F

X4045S8Z-2.7* (Note)

X4045 Z F

0-70

8 Ld SOIC (Pb-free)

X4043S8I-2.7

X4043 G

X4045S8I-2.7

X4045 G

-40-85

8 Ld SOIC

X4043S8IZ-2.7 (Note)

X4043 Z G

X4045S8IZ-2.7 (Note)

X4045 Z G

-40-85

8 Ld SOIC (Pb-free)

X4043M8-2.7

ADG

X4045M8-2.7

ADP

0-70

8 Ld MSOP

X4043M8Z-2.7 (Note)

DAX

X4045M8Z-2.7 (Note)

DBF

0-70

8 Ld MSOP (Pb-free)

X4043M8I-2.7

ADH

X4045M8I-2.7

ADQ

-40-85

8 Ld MSOP

X4043M8IZ-2.7(Note)

DAS

X4045M8IZ-2.7 (Note)

DBB

-40-85

8 Ld MSOP (Pb-free)

X4043P-2.7

X4043P F

X4045P-2.7

X4045P F

0-70

8 Ld PDIP

X4043PZ-2.7 (Note)

X4043P Z F

X4045PZ-2.7 (Note)

X4045P Z F

0-70

8 Ld PDIP(Pb-free)

X4043PI-2.7

X4043P G

X4045PI-2.7

X4045P G

-40-85

8 Ld PDIP

X4043PIZ-2.7 (Note)

X4043P Z G

X4045PIZ-2.7 (Note)

X4045P Z G

-40-85

8 Ld PDIP

*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Ordering Information

PART NUMBER RESET

(ACTIVE LOW)

PART

MARKING

PART NUMBER

RESET (ACTIVE HIGH)

PART

MARKING

RANGE (V)

TRIP

RANGE (V)

TEMP

RANGE (°C)

PACKAGE

X4043, X4045

FN8118.1

September 30, 2005

The memory portion of the device is a CMOS Serial
EEPROM array with Intersil's block lock

protection.

The array is internally organized as x 8. The device
features an 2-wire interface and software protocol
allowing operation on an I

C bus.

The device utilizes Intersil's proprietary Direct Write

cell, providing a minimum endurance of 1,000,000
cycles and a minimum data retention of 100 years.

PIN CONFIGURATION

SDA

SCL

RESET

8-Pin JEDEC SOIC, MSOP, PDIP

Pin

(SOIC/MSOP/DIP)

Name

Function

No internal connections

RESET/RESET

Reset Output.

RESET is an active LOW, open drain output which goes active

whenever V

falls below V

TRIP

. It will remain active until V

rises above the

TRIP

for t

PURST

. RESET/RESET goes active if the Watchdog Timer is enabled

and SDA remains either HIGH or LOW longer than the selectable Watchdog time

out period. RESET/RESET goes active on power-uppower-up and remains

active for 250ms after the power supply stabilizes. RESET is an active high open

drain output. An external pull up resistor is required on the RESET/RESET pin.

Ground

SDA

Serial Data. SDA is a bidirectional pin used to transfer data into and out of the

device. It has an open drain output and may be wire ORed with other open drain

or open collector outputs. This pin requires a pull up resistor and the input buffer

is always active (not gated).

SCL

Serial Clock. The Serial Clock input controls the serial bus timing for data input and

output.

Write Protect. WP HIGH prevents writes to any location in the device (including

the control register). Connect WP pin to V

when it is not used.

Supply Voltage

X4043, X4045

FN8118.1

September 30, 2005

PRINCIPLES OF OPERATION

Power-on Reset
Application of power to the X4043/45 activates a
Power-on Reset Circuit that pulls the RESET/RESET
pin active. This signal provides several benefits.

It prevents the system microprocessor from starting

to operate with insufficient voltage.

It prevents the processor from operating prior to sta-

bilization of the oscillator.

It allows time for an FPGA to download its configura-

tion prior to initialization of the circuit.

When V

exceeds the device V

TRIP

threshold value

for 200ms (nominal) the circuit releases
RESET/RESET allowing the system to begin operation.

Low Voltage Monitoring
During operation, the X4043/45 monitors the V

level

and asserts RESET/RESET if supply voltage falls
below a preset minimum V

TRIP

. The RESET/RESET

signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET
signal remains active until the voltage drops below 1V.
It also remains active until V

returns and exceeds

TRIP

for 200ms.

Watchdog Timer
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. A
standard read or write sequence to any slave address
byte restarts the watchdog timer and prevents the
(RESET/RESET) signal going active. A minimum
sequence to reset the watchdog timer requires four
microprocessor intructions namely, a Start, Clock Low,
Clock High and Stop. (See Page 18) The state of two

nonvolatile control bits in the status register determine
the watchdog timer period. The microprocessor can
change these watchdog bits, or they may be "locked"
by tying the WP pin HIGH.

Figure 1. Watchdog Restart

EEPROM Inadvertent Write Protection
When RESET/RESET goes active as a result of a low
voltage condition (V

< V

TRIP

), any in-progress com-

munications are terminated. While V

< V

TRIP

, no new

communications are allowed and no nonvolatile write
operation can start. Nonvolatile writes in-progress when
RESET/RESET goes active are allowed to finish.

Additional protection mechanisms are provided with
memory block lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.

TRIP

Programming

The X4043/45 is shipped with a standard V

thresh-

old (V

TRIP

) voltage. This value will not change over

normal operating and storage conditions. However, in
applications where the standard V

TRIP

is not exactly

right, or if higher precision is needed in the V

TRIP

value, the X4043/45 threshold may be adjusted. The
procedure is described below, and uses the applica-
tion of a high voltage control signal.

Figure 2. Set V

TRIP

Level Sequence (V

= desired V

TRIP

values WEL bit set)

SCL

SDA

.6µs

1.3µs

Start

Stop

Reset

WDT

0 1 2 3 4 5 6 7

SCL

SDA

A0h

0 1 2 3 4 5 6 7

01h

= 15-18V

0 1 2 3 4 5 6 7

00h

X4043, X4045

FN8118.1

September 30, 2005

Setting a V

TRIP

Voltage

There are two procedures used to set the threshold
voltages (V

TRIP

), depending if the threshold voltage to

be stored is higher or lower than the present value. For
example, if the present V

TRIP

is 2.9 V and the new

TRIP

is 3.2 V, the new voltage can be stored directly

into the V

TRIP

cell. If however, the new setting is to be

lower than the present setting, then it is necessary to
"reset" the V

TRIP

voltage before setting the new value.

Setting a Higher V

TRIP

Voltage

To set a V

TRIP

threshold to a new voltage which is

higher than the present threshold, the user must apply
the desired V

TRIP

threshold voltage to the V

. Then,

a programming voltage (Vp) must be applied to the
WP pin before a START condition is set up on SDA.
Next, issue on the SDA pin the Slave Address A0h,
followed by the Byte Address 01h for V

TRIP

and a 00h

Data Byte in order to program V

TRIP

. The STOP bit

following a valid write operation initiates the program-
ming sequence. WP pin must then be brought LOW to
complete the operation.

To check if the V

TRIP

has been set, first power-down

the device. Slowly ramp up V

and observe when the

output, RESET (4043) or RESET (4045) switches. The
voltage at which this occurs is the V

TRIP

(actual) (see

Figure 2).

ASE

Now if the desired V

TRIP

is greater than the V

TRIP

(actual), then add the difference between V

TRIP

(desired) - V

TRIP

(actual) to the original V

TRIP

desired.

This is your new V

TRIP

that should be applied to V

and the whole sequence should be repeated again
(see Figure 5).

ASE

Now if the V

TRIP

(actual), is higher than the V

TRIP

(desired), perform the reset sequence as described in
the next section. The new V

TRIP

voltage to be applied to

will now be: V

TRIP

(desired) - (V

TRIP

(actual) - V

TRIP

(desired)).

Note: This operation does not corrupt the memory
array.

Setting a Lower V

TRIP

Voltage

In order to set V

TRIP

to a lower voltage than the

present value, then V

TRIP

must first be "reset" accord-

ing to the procedure described below. Once V

TRIP

has

been "reset", then V

TRIP

can be set to the desired volt-

age using the procedure described in "Setting a Higher
V

TRIP

Voltage".

Resetting the V

TRIP

Voltage

To reset a V

TRIP

voltage, apply the programming volt-

age (Vp) to the WP pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h fol-
lowed by 00h for the Data Byte in order to reset V

TRIP

The STOP bit following a valid write operation initiates
the programming sequence. Pin WP must then be
brought LOW to complete the operation.

After being reset, the value of V

TRIP

becomes a nomi-

nal value of 1.7V or lesser.

Note: This operation does not corrupt the memory
array.

X4043, X4045

FN8118.1

September 30, 2005

Figure 5. V

TRIP

Programming Sequence

Control Register
The control register provides the user a mechanism for
changing the block lock and watchdog timer settings.
The block lock and watchdog timer bits are nonvolatile
and do not change when power is removed.

The control register is accessed with a special pream-
ble in the slave byte (1011) and is located at address
1FFh. It can only be modified by performing a byte
write operation directly to the address of the register
and only one data byte is allowed for each register
write operation. Prior to writing to the control register,
the WEL and RWEL bits must be set using a two step
process, with the whole sequence requiring 3 steps.
See "Writing to the Control Register".

The user must issue a stop after sending this byte to
the register to initiate the nonvolatile cycle that stores
WD1, WD0, BP2, BP1, and BP0. The X4043/45 will
not acknowledge any data bytes written after the first
byte is entered.

TRIP

Programming

Power-down

Actual V

TRIP

Desired V

TRIP

DONE

Set Higher V

TRIP

Sequence

Error < MDE

| Error | < | MDE |

YES

Error > MDE

the Device

Desired

Present Value ?

TRIP

Execute

YES

Execute

TRIP

Reset Sequence

Set V

= desired V

TRIP

New V

applied =

Old V

applied + | Error |

New V

applied =

Old V

applied | Error |

Execute Reset V

TRIP

Sequence

Output Switches?

Let: MDE = Maximum Desired Error

MDE

Desired Value

MDE

Acceptable

Error Range

Error = Actual Desired

(RESET)

Ramp V

= Error

X4043, X4045

FN8118.1

September 30, 2005

The state of the control register can be read at any time
by performing a random read at address 1FFh, using
the special preamble. Only one byte is read by each
register read operation. The X4043/45 resets itself after
the first byte is read. The master should supply a stop
condition to be consistent with the bus protocol, but a
stop is not required to end this operation.

RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to "1" prior to a write to the
Control Register.

WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a vola-
tile latch that powers up in the LOW (disabled) state.
While the WEL bit is LOW, writes to any address,
including any control registers will be ignored (no
acknowledge will be issued after the Data Byte). The
WEL bit is set by writing a "1" to the WEL bit and
zeroes to the other bits of the control register. Once
set, WEL remains set until either it is reset to 0 (by
writing a "0" to the WEL bit and zeroes to the other bits
of the control register) or until the part powers up
again. Writes to the WEL bit do not cause a nonvolatile
write cycle, so the device is ready for the next opera-
tion immediately after the stop condition.

BP2, BP1, BP0: Block Protect Bits (Nonvolatile)
The block protect bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to
a protected block of memory is ignored. The block pro-
tect bits will prevent write operations to one of eight
segments of the array.

WD1, WD0: Watchdog Timer Bits
The bits WD1 and WD0 control the period of the
watchdog timer. The options are shown below.

Writing to the Control Register
Changing any of the nonvolatile bits of the control reg-
ister requires the following steps:

Write a 02H to the control register to set the write

enable latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceeded by a start and ended with a stop).

Write a 06H to the control register to set both the

register write enable latch (RWEL) and the WEL bit.
This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop).

Write a value to the control register that has all the

control bits set to the desired state. This can be rep-
resented as 0xys t01r in binary, where xy are the
WD bits, and rst are the BP bits. (Operation pre-
ceeded by a start and ended with a stop). Since this
is a nonvolatile write cycle it will take up to 10ms to
complete. The RWEL bit is reset by this cycle and
the sequence must be repeated to change the non-
volatile bits again. If bit 2 is set to `1' in this third step
(0xys t11r) then the RWEL bit is set, but the WD1,
WD0, BP2, BP1 and BP0 bits remain unchanged.
Writing a second byte to the control register is not
allowed. Doing so aborts the write operation and
returns a NACK.

A read operation occurring between any of the previ-

ous operations will not interrupt the register write
operation.

The RWEL bit cannot be reset without writing to the

nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.

To illustrate, a sequence of writes to the device con-
sisting of [02H, 06H, 02H] will reset all of the nonvola-
tile bits in the control register to 0. A sequence of [02H,
06H, 06H] will leave the nonvolatile bits unchanged
and the RWEL bit remains set.

WD1 WD0

BP1

BP0

RWEL WEL BP2

BP2

BP1

BP0

Protected Addresses

(Size)

Array Lock

None (factory setting)

None

180h - 1FFh

(128 bytes

)

Upper 1/4 (Q4)

100h - 1FFh

(256 bytes

)

Upper 1/2 (Q3,Q4)

000h - 1FFh

(512 bytes)

Full Array (All)

000h - 00Fh

(16 bytes)

First Page (P1)

000h - 01Fh

(32 bytes)

First 2 pgs (P2)

000h - 03Fh

(64 bytes)

First 4 pgs (P4)

000h - 07Fh

(128 bytes)

First 8 pgs (P8)

WD1

WD0

Watchdog Time Out Period

1.4 seconds

600 milliseconds

200 milliseconds

Disabled (factory setting)

X4043, X4045

FN8118.1

September 30, 2005

SERIAL INTERFACE

Serial Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data

transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this fam-
ily operate as slaves in all applications.

Serial Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 6.

Figure 6. Valid Data Changes on the SDA Bus

Serial Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met. See Figure 7.

Serial Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 6.

Figure 7. Valid Start and Stop Conditions

Serial Acknowledge
Acknowledge is a software convention used to indi-
cate successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 8.

The device will respond with an acknowledge after
recognition of a start condition and if the correct device
identifier and select bits are contained in the slave
address byte. If a write operation is selected, the
device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device

will acknowledge all incoming data and address bytes,
except for the slave address byte when the device
identifier and/or select bits are incorrect.

In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to standby mode and place the
device into a known state.

SCL

SDA

Data Stable

Data Change

Data Stable

SCL

SDA

Start

Stop

X4043, X4045

FN8118.1

September 30, 2005

Figure 8. Acknowledge Response From Receiver

X4043/45 ADDRESSING

Slave Address Byte
Following a start condition, the master must output a
slave address byte. This byte consists of several parts:

a device type identifier that is `1010' to access the

array and `1011' to access the control register.

two bits of `0'.
one bit that becomes the MSB of the address.
one bit of the slave command byte is a R/W bit. The

R/W bit of the slave address byte defines the opera-
tion to be performed. When the R/W bit is a one,
then a read operation is selected. A zero selects a
write operation. Refer to Figure 8.

After loading the entire slave address byte from the

SDA bus, the device compares the input slave byte
data to the proper slave byte. Upon a correct compare,
the device outputs an acknowledge on the SDA line.

Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is undefined on a power-up condition.

Slave Address Byte

Figure 9. X4043/45 Addressing

Operational Notes
The device powers-up in the following state:

The device is in the low power standby state.
The WEL bit is set to `0'. In this state it is not possi-

ble to write to the device.

SDA pin is the input mode.
RESET signal is active for t

PURST

SERIAL WRITE OPERATIONS

Byte Write
For a write operation, the device requires the slave
address byte and a word address byte. This gives the
master access to any one of the words in the array.
After receipt of the word address byte, the device
responds with an acknowledge, and awaits the next
eight bits of data. After receiving the 8 bits of the data
byte, the device again responds with an acknowledge.
The master then terminates the transfer by generating a
stop condition, at which time the device begins the inter-
nal write cycle to the nonvolatile memory. During this
internal write cycle, the device inputs are disabled, so the
device will not respond to any requests from the master.
The SDA output is at high impedance. See Figure 10.

A write to a protected block of memory will suppress
the acknowledge bit.

Data Output

from

Transmitter

Data Output

from Receiver

Start

Acknowledge

SCL from

Master

Array
Control Reg.

1
1

0
0

1
1

0
1

A8 R/W

A1 A0

Word Address

Slave Byte

X4043, X4045

FN8118.1

September 30, 2005

Figure 10. Byte Write Sequence

Page Write
The device is capable of a page write operation. It is
initiated in the same manner as the byte write opera-
tion; but instead of terminating the write cycle after the
first data byte is transferred, the master can transmit
an unlimited number of 8-bit bytes. After the receipt of
each byte, the device will respond with an acknowl-
edge, and the address is internally incremented by
one. The page address remains constant. When the
counter reaches the end of the page, it "rolls over" and

goes back to `0' on the same page. This means that
the master can write 16 bytes to the page starting at
any location on that page. If the master begins writing
at location 10, and loads 12 bytes, then the first 5
bytes are written to locations 10 through 15, and the
last 7 bytes are written to locations 0 through 6. After-
wards, the address counter would point to location 7 of
the page that was just written. If the master supplies
more than 16 bytes of data, then new data over-writes
the previous data, one byte at a time.

Figure 11. Page Write Operation

Figure 12. Writing 12-bytes to a 16-byte page starting at location 10

The master terminates the data byte loading by issu-
ing a stop condition, which causes the device to begin
the nonvolatile write cycle. As with the byte write opera-
tion, all inputs are disabled until completion of the inter-
nal write cycle. See Figure 11 for the address,
acknowledge, and data transfer sequence.

Stops and Write Modes
Stop conditions (that terminate write operations) must
be sent by the master after sending at least 1 full data
byte, plus the subsequent ACK signal. If a stop is
issued in the middle of a data byte, or before 1 full
data byte plus its associated ACK is sent, then the
device will reset itself without performing the write. The
contents of the array will not be effected.

Slave

Address

Byte

Address

Data

SDA Bus

Signals from

the Slave

Signals from

the Master

Slave

Address

Byte

Address

Data

(n)

SDA Bus

Signals from

the Slave

Signals from

the Master

Data

(1)

16)

Address

5 Bytes

n-1

7 Bytes

Address

= 6

Address Pointer
Ends Here

Addr = 7

X4043, X4045

FN8118.1

September 30, 2005

Acknowledge Polling
The disabling of the inputs during nonvolatile cycles
can be used to take advantage of the typical 5kHz
write cycle time. Once the stop condition is issued to
indicate the end of the master's byte load operation,
the device initiates the internal nonvolatile cycle.
Acknowledge polling can be initiated immediately. To
do this, the master issues a start condition followed by
the slave address byte for a write or read operation. If
the device is still busy with the nonvolatile cycle then
no ACK will be returned. If the device has completed
the write operation, an ACK will be returned and the
host can then proceed with the read or write operation.
Refer to the flow chart in Figure 13.

Serial Read Operations
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the slave address byte is set to one. There are three
basic read operations: Current Address Reads, Ran-
dom Reads, and Sequential Reads.

Current Address Read
Internally the device contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power-up, the address of the
address counter is undefined, requiring a read or write
operation for initialization.

Upon receipt of the slave address byte with the R/W bit
set to one, the device issues an acknowledge and then
transmits the eight bits of the data byte. The master ter-
minates the read operation when it does not respond
with an acknowledge during the ninth clock and then
issues a stop condition. Refer to Figure 13 for the
address, acknowledge, and data transfer sequence.

Figure 13. Acknowledge Polling Sequence

It should be noted that the ninth clock cycle of the read
operation is not a "don't care." To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.

Figure 14. Current Address Read Sequence

ACK

Returned?

Issue Slave Address
Byte (Read or Write)

Byte Load Completed

by Issuing STOP.

Enter ACK Polling

Issue STOP

Issue START

YES

Nonvolatile Cycle

Complete. Continue

Command

Issue STOP

Continue Normal Read

or Write Command

Sequence

PROCEED

YES

Slave

Address

Data

SDA Bus

Signals from

the Slave

Signals from

the Master

X4043, X4045

FN8118.1

September 30, 2005

Random Read
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
slave address byte with the R/W bit set to one, the
master must first perform a "dummy" write operation.
The master issues the start condition and the slave
address byte, receives an acknowledge, then issues
the word address bytes. After acknowledging receipts

of the word address bytes, the master immediately
issues another start condition and the slave address
byte with the R/W bit set to one. This is followed by an
acknowledge from the device and then by the eight bit
word. The master terminates the read operation by not
responding with an acknowledge and then issuing a
stop condition. Refer to Figure 15 for the address,
acknowledge, and data transfer sequence.

Figure 15. Random Address Read Sequence

There is a similar operation, called "Set Current
Address" where the device does no operation, but
enters a new address into the address counter if a
stop is issued instead of the second start shown in Fig-
ure 14. The device goes into standby mode after the
stop and all bus activity will be ignored until a start is
detected. The next current address read operation
reads from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.

Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first data
byte is transmitted as with the other modes; however,

the master now responds with an acknowledge, indicat-
ing it requires additional data. The device continues to
output data for each acknowledge received. The master
terminates the read operation by not responding with an
acknowledge and then issuing a stop condition.

The data output is sequential, with the data from address
n followed by the data from address n + 1. The address
counter for read operations increments through all page
and column addresses, allowing the entire memory con-
tents to be serially read during one operation. At the end
of the address space the counter "rolls over" to address
0000

and the device continues to output data for each

acknowledge received. Refer to Figure 16 for the
acknowledge and data transfer sequence.

Figure 16. Sequential Read Sequence

Slave

Address

Byte

Address

Slave

Address

Data

SDA Bus

Signals from

the Slave

Signals from

the Master

Data

(2)

Slave

Address

Data

(n)

SDA Bus

Signals from

the Slave

Signals from

the Master

Data
(n-1)

(n is any integer greater than 1)

Data

(1)

X4043, X4045

FN8118.1

September 30, 2005

Data Protection
The following circuitry has been included to prevent
inadvertent writes:

The WEL bit must be set to allow write operations.
The proper clock count and bit sequence is required

prior to the stop bit in order to start a nonvolatile
write cycle.

A three step sequence is required before writing into

the control register to change watchdog timer or
block lock settings.

The WP pin, when held HIGH, prevents all writes to

the array and the control register.

Communication to the device is inhibited as a result

of a low voltage condition (V

< V

TRIP

)any in-

progress communication is terminated.

Block lock bits can protect sections of the memory

array from write operations.

Symbol Table

WAVEFORM

INPUTS

OUTPUTS

Must be

steady

Will be

steady

May change

from LOW

to HIGH

Will change

from LOW

to HIGH

May change

from HIGH

to LOW

Will change

from HIGH

to LOW

Don't Care:

Changes

Allowed

Changing:

State Not

Known

N/A

Center Line

is High

Impedance

X4043, X4045

FN8118.1

September 30, 2005

ABSOLUTE MAXIMUM RATINGS

Temperature under bias ................... -65°C to +135°C
Storage temperature ........................ -65°C to +150°C
Voltage on any pin with

respect to V

...................................... -1.0V to +7V

D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds)........ 300°C

COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; the functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Notes: (1) The device enters the active state after any start, and remains active until: 9 clock cycles later if the device select bits in the slave

address byte are incorrect; 200ns after a stop ending a read operation; or t

after a stop ending a write operation.

(2) The device goes into standby: 200ns after any stop, except those that initiate a nonvolatile write cycle; t

after a stop that initiates a

nonvolatile cycle; or 9 clock cycles after any start that is not followed by the correct device select bits in the slave address byte.

(3) V

min. and V

max. are for reference only and are not tested.

Symbol

Parameter

= 2.7 to 5.5V

Unit

Test Conditions

Min.

Max.

CC1

(1)

Active supply current read

1.0

= V

x 0.1, V

= V

x 0.9

SCL

= 400kHz

CC2

(1)

Active supply current write

3.0

SB1

(2)

Standby current AC (WDT off)

µA

= V

x 0.1, V

= V

x 0.9

SCL

= 400kHz, SDA = open

= 1.22 x V

min

SB2

(2)

Standby current DC (WDT off)

µA

SDA

= V

SCL

= V

Others = GND or V

SB3

(2)

Standby current DC (WDT on)

µA

SDA

SCL

= V

Others = GND or V

Input leakage current

µA

= GND to V

Output leakage current

µA

SDA

= GND to V

device is in standby

(3)

Input LOW voltage

-0.5

x 0.3

(3)

Input nonvolatile

x 0.7

+ 0.5

HYS

Schmitt trigger input hysteresis
Fixed input level
V

related level

0.2

.05 x V

V
V

Output LOW voltage

0.4

= 3.0mA (2.7-5.5V)

= 1.8mA (2.0-3.6V)

RECOMMENDED OPERATING CONDITIONS

Temperature

Min.

Max.

Commercial

0°C

70°C

Industrial

-40°C

+85°C

Option

Supply Voltage Limits

-2.7 and -2.7A

2.7V to 5.5V

Blank and -4.5A

4.5V to 5.5V

X4043, X4045

FN8118.1

September 30, 2005

CAPACITANCE (T

= 25°C, f = 1.0 MHz, V

= 5V)

Notes: (4) This parameter is periodically sampled and not 100% tested.

EQUIVALENT A.C. LOAD CIRCUIT

A.C. TEST CONDITIONS

A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)

Notes: (5) Typical values are for T

= 25°C and V

= 5.0V

(6) Cb = total capacitance of one bus line in pF.

Symbol

Parameter

Max.

Unit

Test Conditions

OUT

(4)

Output capacitance (SDA, RESET/RESET)

OUT

= 0V

(4)

Input capacitance (SCL, WP)

= 0V

4.6k

RESET

100pF

SDA

1533

100pF

For V

= 0.4V

and I

= 3 mA

Input pulse levels

0.1 V

to 0.9 V

Input rise and fall times

10ns

Input and output timing levels

0.5 V

Output load

Standard output load

Symbol

Parameter

100kHz 400kHz

Unit

Min.

Max.

Min.

Max.

SCL

SCL clock frequency

100

400

kHz

Pulse width suppression time at inputs

n/a

SCL LOW to SDA data out valid

0.1

0.9

0.1

0.9

µs

BUF

Time the bus free before start of new transmission

4.7

1.3

µs

LOW

Clock LOW time

4.7

1.3

µs

HIGH

Clock HIGH time

4.0

0.6

µs

SU:STA

Start condition setup time

4.7

0.6

µs

HD:STA

Start condition hold time

4.0

0.6

µs

SU:DAT

Data in setup time

250

100

HD:DAT

Data in hold time

5.0

µs

SU:STO

Stop condition setup time

0.6

µs

Data output hold time

SDA and SCL rise time

1000 20 + .1Cb

(6)

300

SDA and SCL fall time

300

20 + .1Cb

(6)

300

SU:WP

WP setup time

0.4

0.6

HD:WP

WP hold time

Capacitive load for each bus line

400

X4043, X4045

FN8118.1

September 30, 2005

Power-Up and Power-Down Timing

RESET Output Timing

Notes: (8) This parameter is periodically sampled and not 100% tested.

Symbol

Parameter

Min.

Typ.

Max.

Unit

TRIP

Reset trip point voltage, X4043/45-4.5A
Reset trip point voltage, X4043/45
Reset trip point voltage, X4043/45-2.7A
Reset trip point voltage, X4043/45-2.7

4.5

4.25
2.85
2.55

4.62
4.38
2.92
2.62

4.75

4.5
3.0
2.7

PURST

Power-up reset time out

100

200

400

RPD

(8)

detect to RESET/RESET

µs

(8)

fall time

mV/µs

(8)

rise time

mV/µs

RVALID

Reset valid V

WDO

Watchdog time out period,

WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0

100
450

200
600

1.4

300
800

ms
ms

sec

RSP

Watchdog Time Restart pulse width

µs

RST

Reset time out

100

200

400

PURST

RPD

0 Volts

TRIP

RESET

RVALID

RESET

RVALID

(X4043)

(X4045)

X4043, X4045

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8118.1

September 30, 2005

PACKAGING INFORMATION

NOTE:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH

0.020 (0.51)
0.016 (0.41)

0.150 (3.81)
0.125 (3.18)

0.110 (2.79)
0.090 (2.29)

0.430 (10.92)

0.360 (9.14)

0.300

(7.62) Ref.

Pin 1 Index

0.145 (3.68)
0.128 (3.25)

0.025 (0.64)
0.015 (0.38)

Pin 1

Seating

0.065 (1.65)
0.045 (1.14)

0.260 (6.60)
0.240 (6.10)

0.060 (1.52)
0.020 (0.51)

Typ. 0.010 (0.25)

0°

15°

8-Lead Plastic Dual In-Line Package Type P

Half Shoulder Width On

All End Pins Optional

.073 (1.84)

Max.

0.325 (8.25)
0.300 (7.62)

Plane

X4043, X4045

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X4043S8I-2.7AT1