FN8120.0

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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X4163, X4165

16K, 2K x 8 Bit

CPU Supervisor with 16K EEPROM

FEATURES

· Selectable watchdog timer
· Low V

detection and reset assertion

--Four standard reset threshold voltages
--Adjust low V

reset threshold voltage using

special programming sequence

--Reset signal valid to V

= 1V

· Low power CMOS

--<20µA max standby current, watchdog on
--<1µA standby current, watchdog OFF
--3mA active current

· 16Kbits of EEPROM

--64-byte page write mode
--Self-timed write cycle
--5ms write cycle time (typical)

· Built-in inadvertent write protection

--Power-up/power-down protection circuitry
--Block Lock (1, 2, 4, 8 pages, all, none)

· 400kHz 2-wire interface
· 2.7V to 5.5V power supply operation
· Available Packages

--8-lead SOIC
--8-lead TSSOP

DESCRIPTION

The X4163/5 combines four popular functions, Power-
on Reset Control, Watchdog Timer, Supply Voltage
Supervision, and Serial EEPROM Memory in one pack-
age. This combination lowers system cost, reduces
board space requirements, and increases reliability.

Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.

The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the
RESET/RESET signal. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.

The device's low V

detection circuitry protects the

user's system from low voltage conditions, resetting the
system when V

falls below the set minimum V

trip

point. RESET/RESET is asserted until V

returns to

proper operating level and stabilizes. Four industry
standard V

TRIP

thresholds are available, however, Inter-

sil's unique circuits allow the threshold to be repro-
grammed to meet custom requirements or to fine-tune
the threshold for applications requiring higher precision.

BLOCK DIAGRAM

Watchdog

Timer Reset

Data

Command

Decode &

Control

Logic

SDA

SCL

Reset &

Watchdog

Timebase

Power on and

Generation

TRIP

RESET (X4163)

Reset

Low Voltage

Status

Protect Logic

EEPROM Array

Watchdog Transition

Detector

Threshold

Reset logic

Block Lock C

ontrol

2Kb

RESET (X4165)

S0
S1

Data Sheet

April 13, 2005

FN8120.0

April 13, 2005

PIN CONFIGURATION

PIN FUNCTION

SDA

SCL

8-Pin JEDEC SOIC

RESET/RESET

SCL

RESET/RESET

SDA

8 Pin TSSOP

Pin

(SOIC)

Pin

(TSSOP)

Name

Function

Device Select Input

RESET/

RESET

Reset Output.

RESET/RESET is an active LOW/HIGH, open drain output which

goes active whenever V

falls below the minimum V

sense level. It will remain

active until V

rises above the minimum V

sense level for 250ms.

RESET/RESET goes active if the Watchdog Timer is enabled and SDA remains

either HIGH or LOW longer than the selectable Watchdog time out period. A falling

edge on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET/RESET

goes active on power up and remains active for 250ms after the power supply sta-

bilizes.

Ground

SDA

Serial Data. SDA is a bidirectional pin used to transfer data into and out of the

device. It has an open drain output and may be wire ORed with other open drain

or open collector outputs. This pin requires a pull up resistor and the input buffer

is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts

the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog

time out period results in RESET/RESET going active.

SCL

Serial Clock. The Serial Clock controls the serial bus timing for data input and output.

Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to

the control register.

Supply Voltage

X4163, X4165

FN8120.0

April 13, 2005

PRINCIPLES OF OPERATION

Power On Reset
Application of power to the X4163/5 activates a Power
On Reset Circuit that pulls the RESET/RESET pin
active. This signal provides several benefits.

It prevents the system microprocessor from starting

to operate with insufficient voltage.

It prevents the processor from operating prior to sta-

bilization of the oscillator.

It allows time for an FPGA to download its configura-

tion prior to initialization of the circuit.

It prevents communication to the EEPROM, greatly

reducing the likelihood of data corruption on power up.

When V

exceeds the device V

TRIP

threshold value

for 200ms (nominal) the circuit releases
RESET/RESET allowing the system to begin operation.

LOW VOLTAGE MONITORING

During operation, the X4163/5 monitors the V

level

and asserts RESET/RESET if supply voltage falls
below a preset minimum V

TRIP

. The RESET/RESET

signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET
signal remains active until the voltage drops below 1V.
It also remains active until V

returns and exceeds

TRIP

for 200ms.

WATCHDOG TIMER

The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to
LOW periodically, while SCL is HIGH (this is a start bit)
prior to the expiration of the watchdog time out period to
prevent a RESET/RESET signal. The state of two non-
volatile control bits in the Status Register determine
the watchdog timer period. The microprocessor can
change these watchdog bits, or they may be "locked"
by tying the WP pin HIGH.

EEPROM INADVERTENT WRITE PROTECTION

When RESET/RESET goes active as a result of a low
voltage condition or Watchdog Timer Time Out, any in-
progress communications are terminated. While
RESET/RESET is active, no new communications are
allowed and no nonvolatile write operation can start.
Nonvolatile writes in-progress when RESET/RESET
goes active are allowed to finish.

Additional protection mechanisms are provided with
memory Block Lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.

THRESHOLD RESET PROCEDURE

The X4163/5 is shipped with a standard V

threshold

TRIP

) voltage. This value will not change over normal

operating and storage conditions. However, in applica-
tions where the standard V

TRIP

is not exactly right, or if

higher precision is needed in the V

TRIP

value, the

X4163/5 threshold may be adjusted. The procedure is
described below, and uses the application of a nonvol-
atile control signal.

Figure 1. Set V

TRIP

Level Sequence (V

= desired V

TRIP

values WEL bit set)

0 1 2 3 4 5 6 7

SCL

SDA

A0h

0 1 2 3 4 5 6 7

00h

= 12-15V

0 1 2 3 4 5 6 7

01h

0 1 2 3 4 5 6 7

00h

X4163, X4165

FN8120.0

April 13, 2005

Setting the V

TRIP

Voltage

This procedure is used to set the V

TRIP

to a higher or

lower voltage value. It is necessary to reset the trip
point before setting the new value.

To set the new V

TRIP

voltage, start by setting the WEL

bit in the control register, then apply the desired V

TRIP

threshold voltage to the V

pin and the programming

voltage, V

to the WP pin and 2 byte address and 1

byte of "00" data. The stop bit following a valid write
operation initiates the V

TRIP

programming sequence.

Bring WP

LOW to complete the operation.

Resetting the V

TRIP

Voltage

This procedure is used to set the V

TRIP

to a "native"

voltage level. For example, if the current V

TRIP

is 4.4V

and the new V

TRIP

must be 4.0V, then the V

TRIP

must

be reset. When V

TRIP

is reset, the new V

TRIP

is some-

thing less than 1.7V. This procedure must be used to
set the voltage to a lower value.

To reset the new V

TRIP

voltage start by setting the

WEL bit in the control register, apply V

and the pro-

gramming voltage, V

, to the WP pin and 2 byte

address and 1 byte of "00" data. The stop bit of a valid
write operation initiates the V

TRIP

programming

sequence. Bring WP

LOW to complete the operation.

Figure 2. Reset V

TRIP

Level Sequence (V

> 3V. WP = 1215V, WEL bit set)

Figure 3. Sample V

TRIP

Reset Circuit

0 1 2 3 4 5 6 7

SCL

SDA

A0h

0 1 2 3 4 5 6 7

00h

= 12-15V

0 1 2 3 4 5 6 7

03h

0 1 2 3 4 5 6 7

00h

1
2
3
4

8
7
6
5

X4163

TRIP

Adj.

RESET

4.7K

SDA

SCL

µC

Adjust

Run

SOIC

X4163, X4165

FN8120.0

April 13, 2005

Figure 4. V

TRIP

Programming Sequence

Control Register
The Control Register provides the user a mechanism
for changing the Block Lock and Watchdog Timer set-
tings. The Block Lock and Watchdog Timer bits are
nonvolatile and do not change when power is
removed.

The Control Register is accessed at address FFFFh. It
can only be modified by performing a byte write opera-
tion directly to the address of the register and only one
data byte is allowed for each register write operation.
Prior to writing to the Control Register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps. See "Writing to
the Control Register" below.

The user must issue a stop after sending this byte to
the register to initiate the nonvolatile cycle that stores
WD1, and WD0. The X4163/5 will not acknowledge
any data bytes written after the first byte is entered.

The state of the Control Register can be read at any
time by performing a random read at address FFFFh.
Only one byte is read by each register read operation.
The X4163/5 resets itself after the first byte is read.
The master should supply a stop condition to be con-
sistent with the bus protocol, but a stop is not required
to end this operation.

TRIP

Programming

Apply 5V to V

Decrement V

RESET pin

goes active?

Measured V

TRIP

Desired V

TRIP

DONE

Execute

Sequence

Reset V

TRIP

Set V

= V

Applied =

Desired V

TRIP

Execute

Sequence

Set V

TRIP

New V

Applied =

Old V

Applied + Error

= V

- 50mV)

Execute

Sequence

Reset V

TRIP

New V

Applied =

Old V

Applied - Error

Error

Emax

Emax < Error < Emax

YES

Error

Emax

Emax = Maximum Allowed V

TRIP

Error

WPEN WD1 WD0 BP1 BP0 RWEL WEL BP2

X4163, X4165

FN8120.0

April 13, 2005

BP2, BP1, BP0: Block Protect Bits (Nonvolatile)
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to
a protected block of memory is ignored. The block pro-
tect bits will prevent write operations to the following
segments of the array.

RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to "1" prior to a write to the
Control Register.

WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a vola-
tile latch that powers up in the LOW (disabled) state.
While the WEL bit is LOW, writes to any address,
including any control registers will be ignored (no
acknowledge will be issued after the Data Byte). The
WEL bit is set by writing a "1" to the WEL bit and
zeroes to the other bits of the control register. Once
set, WEL remains set until either it is reset to 0 (by
writing a "0" to the WEL bit and zeroes to the other bits
of the control register) or until the part powers up

again. Writes to the WEL bit do not cause a nonvolatile
write cycle, so the device is ready for the next opera-
tion immediately after the stop condition.

WD1, WD0: Watchdog Timer Bits
The bits WD1 and WD0 control the period of the
Watchdog Timer. The options are shown below.

Write Protect Enable
These devices have an advanced Block Lock scheme
that protects one of five blocks of the array when
enabled. It provides hardware write protection through
the use of a WP pin and a nonvolatile Write Protect
Enable (WPEN) bit.

The Write Protect (WP) pin and the Write Protect
Enable (WPEN) bit in the Control Register control the
programmable Hardware Write Protect feature. Hard-
ware Write Protection is enabled when the WP pin and
the WPEN bit are HIGH and disabled when either the
WP pin or the WPEN bit is LOW. When the chip is
Hardware Write Protected, nonvolatile writes to the
block protected sections in the memory array cannot be
written and the block protect bits cannot be changed.
Only the sections of the memory array that are not
block protected can be written. Note that since the
WPEN bit is write protected, it cannot be changed
back to a LOW state; so write protection is enabled as
long as the WP pin is held HIGH.

Table 1. Write Protect Enable Bit and WP Pin Function

0 Protected Addresses

(Size)

Array Lock

None (factory setting)

None

0000h - 7FFh

(2K bytes)

Full Array (All)

000h - 03Fh

(64 bytes)

First Page (P1)

000h - 07Fh

(128 bytes)

First 2 pgs (P2)

000h - 0FFh

(256 bytes)

First 4 pgs (P4)

000h - 1FFh

(512 bytes)

First 8 pgs (P8)

WD1

WD0

Watchdog Time Out Period

1.4 seconds

600 milliseconds

200 milliseconds

disabled (factory setting)

WPEN

Memory Array not

Block Protected

Memory Array Block

Protected

WPEN Bit

Protection

LOW

Writes OK

Writes Blocked

Writes OK

Software

HIGH

Writes OK

Writes Blocked

Writes OK

Software

HIGH

Writes OK

Writes Blocked

Hardware

X4163, X4165

FN8120.0

April 13, 2005

Writing to the Control Register
Changing any of the nonvolatile bits of the control reg-
ister requires the following steps:

Write a 02H to the Control Register to set the Write

Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceeded by a start and ended with a stop).

Write a 06H to the Control Register to set both the

Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop).

Write a value to the Control Register that has all the

control bits set to the desired state. This can be rep-
resented as 0xys t01r in binary, where xy are the
WD bits. (Operation preceeded by a start and ended
with a stop). Since this is a nonvolatile write cycle it
will take up to 10ms to complete. The RWEL bit is
reset by this cycle and the sequence must be
repeated to change the nonvolatile bits again. If bit 2
is set to `1' in this third step (0xys t11r) then the
RWEL bit is set, but the BP2, BP1, BP0, WD1 and
WD0 bits remain unchanged. Writing a second byte
to the control register is not allowed. Doing so aborts
the write operation and returns a NACK.

A read operation occurring between any of the previ-

ous operations will not interrupt the register write
operation.

The RWEL bit cannot be reset without writing to the

nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.

To illustrate, a sequence of writes to the device con-
sisting of [02H, 06H, 02H] will reset all of the nonvola-
tile bits in the Control Register to 0. A sequence of
[02H, 06H, 06H] will leave the nonvolatile bits
unchanged and the RWEL bit remains set.

SERIAL INTERFACE

Serial Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this fam-
ily operate as slaves in all applications.

Serial Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 5.

Figure 5. Valid Data Changes on the SDA Bus

SCL

SDA

Data Stable

Data Change

Data Stable

X4163, X4165

FN8120.0

April 13, 2005

Figure 6. Valid Start and Stop Conditions

Serial Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met. See Figure 6.

Serial Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 6.

Serial Acknowledge
Acknowledge is a software convention used to indi-
cate successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-

mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 7.

The device will respond with an acknowledge after
recognition of a start condition and if the correct
Device Identifier and Select bits are contained in the
Slave Address Byte. If a write operation is selected,
the device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for the Slave Address Byte when the Device
Identifier and/or Select bits are incorrect.

In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.

Figure 7. Acknowledge Response From Receiver

SCL

SDA

Start

Stop

Data Output

from

Transmitter

Data Output

from Receiver

Start

Acknowledge

SCL from

Master

X4163, X4165

FN8120.0

April 13, 2005

Figure 8. Byte Write Sequence

Serial Write Operations

YTE

RITE

For a write operation, the device requires the Slave
Address Byte and a Word Address Byte. This gives
the master access to any one of the words in the
array. After receipt of the Word Address Byte, the
device responds with an acknowledge, and awaits
the next eight bits of data. After receiving the 8 bits of
the Data Byte, the device again responds with an
acknowledge. The master then terminates the trans-
fer by generating a stop condition, at which time the
device begins the internal write cycle to the nonvola-
tile memory. During this internal write cycle, the
device inputs are disabled, so the device will not
respond to any requests from the master. The SDA
output is at high impedance. See Figure 8.

A write to a protected block of memory will suppress
the acknowledge bit.

Page Write
The device is capable of a page write operation. It is
initiated in the same manner as the byte write opera-
tion; but instead of terminating the write cycle after the
first data byte is transferred, the master can transmit
an unlimited number of 8-bit bytes. After the receipt of
each byte, the device will respond with an acknowl-
edge, and the address is internally incremented by
one. The page address remains constant. When the
counter reaches the end of the page, it "rolls over" and
goes back to `0' on the same page. This means that
the master can write 64 bytes to the page starting at
any location on that page. If the master begins writing
at location 60, and loads 12-bytes, then the first 4-
bytes are written to locations 60 through 63, and the
last 8-bytes are written to locations 0 through 7. After-
wards, the address counter would point to location 8 of
the page that was just written. If the master supplies
more than 64-bytes of data, then new data over-writes
the previous data, one byte at a time.

Figure 9. Page Write Operation

Slave

Address

Word Address

Byte 0

Data

SDA Bus

Signals from

the Slave

Signals from

the Master

Word Address

Byte 1

Slave

Address

Word Address

Byte 1

Data

(n)

SDA Bus

Signals from

the Slave

Signals from

the Master

Data

(1)

(1 < n < 64)

Word Address

Byte 0

X4163, X4165

FN8120.0

April 13, 2005

Figure 10. Writing 12-bytes to a 64-byte page starting at location 60.

The master terminates the Data Byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation,
all inputs are disabled until completion of the internal
write cycle. See Figure 9 for the address, acknowledge,
and data transfer sequence.

Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte plus the subsequent ACK signal. If a stop is
issued in the middle of a data byte, or before 1 full
data byte plus its associated ACK is sent, then the
device will reset itself without performing the write. The
contents of the array will not be effected.

Acknowledge Polling
The disabling of the inputs during nonvolatile cycles
can be used to take advantage of the typical 5ms write
cycle time. Once the stop condition is issued to indi-
cate the end of the master's byte load operation, the
device initiates the internal nonvolatile cycle. Acknowl-
edge polling can be initiated immediately. To do this,
the master issues a start condition followed by the
Slave Address Byte for a write or read operation. If the
device is still busy with the nonvolatile cycle then no
ACK will be returned. If the device has completed the
write operation, an ACK will be returned and the host
can then proceed with the read or write operation.
Refer to the flow chart in Figure 11.

Figure 11. Acknowledge Polling Sequence

Address

4 Bytes

n-1

8 Bytes

Address

= 7

Address Pointer
Ends Here

Addr = 8

ACK

returned?

Issue Slave Address
Byte (Read or Write)

Byte load completed

by issuing STOP.

Enter ACK Polling

Issue STOP

Issue START

YES

Nonvolatile Cycle

complete. Continue

command sequence?

Issue STOP

Continue Normal

Read or Write

Command Sequence

PROCEED

YES

X4163, X4165

FN8120.0

April 13, 2005

Figure 12. Current Address Read Sequence

Serial Read Operations
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Ran-
dom Reads, and Sequential Reads.

Current Address Read
Internally the device contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power up, the address of the
address counter is undefined, requiring a read or write
operation for initialization.

Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an acknowledge and
then transmits the eight bits of the Data Byte. The
master terminates the read operation when it does not
respond with an acknowledge during the ninth clock
and then issues a stop condition. Refer to Figure 12
for the address, acknowledge, and data transfer
sequence.

It should be noted that the ninth clock cycle of the read
operation is not a "don't care." To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.

Random Read
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W bit set to one, the
master must first perform a "dummy" write operation.
The master issues the start condition and the Slave
Address Byte, receives an acknowledge, then issues
the Word Address Bytes. After acknowledging receipts
of the Word Address Bytes, the master immediately
issues another start condition and the Slave Address
Byte with the R/W bit set to one. This is followed by an
acknowledge from the device and then by the eight bit
word. The master terminates the read operation by not
responding with an acknowledge and then issuing a
stop condition. Refer to Figure 13 for the address,
acknowledge, and data transfer sequence.

There is a similar operation, called "Set Current
Address" where the device does no operation, but
enters a new address into the address counter if a
stop is issued instead of the second start shown in Fig-
ure 13. The device goes into standby mode after the
stop and all bus activity will be ignored until a start is
detected. The next Current Address Read operation
reads from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.

Figure 13. Random Address Read Sequence

Slave

Address

Data

SDA Bus

Signals from

the Slave

Signals from

the Master

Slave

Address

Word Address

Byte 1

Slave

Address

Data

SDA Bus

Signals from

the Slave

Signals from

the Master

Word Address

Byte 0

X4163, X4165

FN8120.0

April 13, 2005

Figure 14. Sequential Read Sequence

Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicat-
ing it requires additional data. The device continues to
output data for each acknowledge received. The master
terminates the read operation by not responding with an
acknowledge and then issuing a stop condition.

The data output is sequential, with the data from
address n followed by the data from address n + 1.
The address counter for read operations increments
through all page and column addresses, allowing the
entire memory contents to be serially read during one
operation. At the end of the address space the counter
"rolls over" to address 0000

and the device continues

to output data for each acknowledge received. Refer
to Figure 14 for the acknowledge and data transfer
sequence.

X4163/5 Addressing

LAVE

DDRESS

YTE

Following a start condition, the master must output a
Slave Address Byte. This byte consists of several
parts:

a device type identifier that is `1010' to access the

array.

one bits of `0'.
next two bits are the device address.
one bit of the slave command byte is a R/W bit. The

R/W bit of the Slave Address Byte defines the oper-
ation to be performed. When the R/W bit is a one,
then a read operation is selected. A zero selects a
write operation. Refer to Figure 15.

After loading the entire Slave Address Byte from the

SDA bus, the device compares the input slave byte
data to the proper slave byte. Upon a correct compare,
the device outputs an acknowledge on the SDA line.

Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is undefined on a power up condition.

Data

(2)

Slave

Address

Data

(n)

SDA Bus

Signals from

the Slave

Signals from

the Master

Data
(n-1)

(n is any integer greater than 1)

Data

(1)

X4163, X4165

FN8120.0

April 13, 2005

Figure 15. X4163/5 Addressing

Operational Notes
The device powers-up in the following state:

The device is in the low power standby state.
The WEL bit is set to `0'. In this state it is not possi-

ble to write to the device.

SDA pin is the input mode.
RESET/RESET Signal is active for t

PURST

Data Protection
The following circuitry has been included to prevent
inadvertent writes:

The WEL bit must be set to allow write operations.
The proper clock count and bit sequence is required

prior to the stop bit in order to start a nonvolatile
write cycle.

A three step sequence is required before writing into

the Control Register to change Watchdog Timer or
Block Lock settings.

The WP pin, when held HIGH, and WPEN bit at logic

HIGH will prevent all writes to the Control Register.

Communication to the device is inhibited while

RESET/RESET is active and any in-progress com-
munication is terminated.

Block Lock bits can protect sections of the memory

array from write operations.

SYMBOL TABLE

R/W

Slave Address Byte

Device Identifier

Device Select

A10

Word Address Byte 016K

High Order Word Address

(X4)

(X3)

(X2)

Word Address Byte 0 for all options

Low Order Word Address

(Y2)

(Y1)

(Y0)

(Y3)

(Y4)

(Y5)

(X0)

(X1)

Data Byte for all options

WAVEFORM

INPUTS

OUTPUTS

Must be

steady

Will be

steady

May change

from LOW

to HIGH

Will change

from LOW

to HIGH

May change

from HIGH

to LOW

Will change

from HIGH

to LOW

Don't Care:

Changes

Allowed

Changing:

State Not

Known

N/A

Center Line

is High

Impedance

X4163, X4165

FN8120.0

April 13, 2005

ABSOLUTE MAXIMUM RATINGS

Temperature under bias ................... -65°C to +135°C
Storage temperature ........................ -65°C to +150°C
Voltage on any pin with respect to VSS... -1.0V to +7V
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds)........ 300°C

COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave

Address Byte are incorrect; 200ns after a stop ending a read operation; or t

after a stop ending a write operation.

(2) The device goes into Standby: 200ns after any stop, except those that initiate a nonvolatile write cycle; t

after a stop that initiates a

nonvolatile cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte.

(3) V

Min. and V

Max. are for reference only and are not tested.

Symbol

Parameter

= 2.7 to 5.5V

Unit

Test Conditions

Min

Max

CC1

(1)

Active Supply Current Read

1.0

= V

x 0.1, V

= V

x 0.9

SCL

= 400kHz, SDA = Commands

CC2

(1)

Active Supply Current Write

3.0

(2)

Standby Current DC (WDT off)

µA

SDA

= V

SCL

= V

Others = GND or V

(2)

Standby Current DC (WDT on)

µA

SDA

SCL

Others = GND or V

Input Leakage Current

µA

= GND to V

Output Leakage Current

µA

SDA

= GND to V

Device is in Standby

(2)

(3)

Input LOW Voltage

-0.5

x 0.3

(3)

Input nonvolatile

x 0.7

+ 0.5

HYS

Schmitt Trigger Input Hysteresis

Fixed input level

related level

0.2

.05 x V

V
V

Output LOW Voltage

0.4

= 3.0mA (2.7- 5.5V)

RECOMMENDED OPERATING CONDITIONS

Temperature

Min.

Max.

Commercial

0°C

70°C

Industrial

-40°C

+85°C

Option

Supply Voltage Limits

-2.7 and -2.7A

2.7V to 5.5V

Blank and -4.5A

4.5V to 5.5V

X4163, X4165

FN8120.0

April 13, 2005

CAPACITANCE (T

= 25°C, f = 1.0 MHz, V

= 5V)

Notes: (4) This parameter is periodically sampled and not 100% tested.

EQUIVALENT A.C. LOAD CIRCUIT

A.C. TEST CONDITIONS

A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)

Notes: (1) Typical values are for T

= 25°C and V

= 5.0V

(2) Cb = total capacitance of one bus line in pF.

Symbol

Parameter

Max.

Unit

Test Conditions

OUT

(4)

Output Capacitance (SDA, RST/RST)

OUT

= 0V

(4)

Input Capacitance (SCL, WP)

= 0V

SDA

RESET

1533

100pF

For V

= 0.4V

and I

= 3 mA

Input pulse levels

0.1V

to 0.9V

Input rise and fall times

10ns

Input and output timing levels

0.5V

Output load

Standard output load

Symbol

Parameter

Min.

Max.

Unit

SCL

SCL Clock Frequency

400

kHz

Pulse width Suppression Time at inputs

SCL LOW to SDA Data Out Valid

0.1

0.9

µs

BUF

Time the bus free before start of new transmission

1.3

µs

LOW

Clock LOW Time

1.3

µs

HIGH

Clock HIGH Time

0.6

µs

SU:STA

Start Condition Setup Time

0.6

µs

HD:STA

Start Condition Hold Time

0.6

µs

SU:DAT

Data In Setup Time

100

HD:DAT

Data In Hold Time

µs

SU:STO

Stop Condition Setup Time

0.6

µs

Data Output Hold Time

SDA and SCL Rise Time

20 + .1Cb

300

SDA and SCL Fall Time

20 + .1Cb

300

SU:WP

WP Setup Time

0.6

µs

HD:WP

WP Hold Time

µs

Capacitive load for each bus line

400

X4163, X4165

FN8120.0

April 13, 2005

TIMING DIAGRAMS

Bus Timing

WP Pin Timing

Write Cycle Timing

Nonvolatile Write Cycle Timing

Notes: (1) t

is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is

the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.

Symbol

Parameter

Min.

Typ.

(1)

Max.

Unit

(1)

Write Cycle Time

SU:STO

HIGH

SU:STA

HD:STA

HD:DAT

SU:DAT

SCL

SDA IN

SDA OUT

LOW

BUF

HD:WP

SCL

SDA IN

SU:WP

Clk 1

Clk 9

Slave Address Byte

START

SCL

SDA

8th bit of Last Byte

ACK

Stop

Condition

Start

Condition

X4163, X4165

FN8120.0

April 13, 2005

Power-Up and Power-Down Timing

RESET Output Timing

Notes: (8) This parameter is periodically sampled and not 100% tested.

SDA vs. RESET Timing

Symbol

Parameter

Min.

Typ.

Max.

Unit

TRIP

Reset Trip Point Voltage, X4163/5-4.5A
Reset Trip Point Voltage, X4163/5
Reset Trip Point Voltage, X4163/5-2.7A
Reset Trip Point Voltage, X4163/5-2.7

4.5

4.25
2.85
2.55

4.62
4.38
2.92
2.62

4.75

4.5
3.0
2.7

PURST

Power-up Reset Time Out

100

250

400

RPD

(8)

Detect to Reset/Output

500

(8)

Fall Time

100

µs

(8)

Rise Time

100

µs

RVALID

Reset Valid V

PURST

RPD

0 Volts

TRIP

RESET

RVALID

(X4165)

(X4163)

PURST

RVALID

RSP

WDO

RST

RESET

SDA

RSP

Note: All inputs are ignored during the active reset period (t

RST

SCL

RSP

WDO

RSP

WDO

X4163, X4165

FN8120.0

April 13, 2005

RESET Output Timing

TRIP

Programming Timing Diagram (WEL = 1)

TRIP

Programming Parameters

Symbol

Parameter

Min.

Typ.

Max.

Units

WDO

Watchdog Time Out Period,

WD1 = 1, WD0 = 1 (factory setting)
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0

100
450

OFF

250
650

1.5

400
850

ms
ms

sec

RST

Reset Time Out

100

250

400

Parameter

Description

Min.

Max. Unit

VPS

TRIP

Program Enable Voltage Setup time

µs

VPH

TRIP

Program Enable Voltage Hold time

µs

TSU

TRIP

Setup time

µs

THD

TRIP

Hold (stable) time

TRIP

Write Cycle Time

VPO

TRIP

Program Enable Voltage Off time (Between successive adjustments)

µs

TRIP

Program Recovery Period (Between successive adjustments)

Programming Voltage

TRAN

TRIP

Programmed Voltage Range

2.55

4.75

ta1

Initial V

TRIP

Program Voltage accuracy (V

applied - V

TRIP

) (Programmed at 25°C.)

-0.1

+0.4

ta2

Subsequent V

TRIP

Program Voltage accuracy [(V

applied - V

ta1

) - V

TRIP

Programmed at 25°C.]

-25

+25

TRIP

Program Voltage repeatability (Successive program operations. Programmed

at 25°C.)

-25

+25

TRIP

Program variation after programming (0-75°C). (Programmed at 25°C.)

-25

+25

TRIP

programming parameters are periodically sampled and are not 100% tested.

TRIP

)

TSU

THD

VPH

VPS

TRIP

VPO

SCL

SDA

A0h

01h or 03h

00h

X4163, X4165

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8120.0

April 13, 2005

Ordering Information

Part Mark Information

Range

TRIP

Range

Package

Operating

Temperature Range

Part Number RESET

(Active LOW)

Part Number RESET

(Active HIGH)

4.5-5.5V

4.5-4.75

8L SOIC

0°C - 70°C

X4163S84.5A

X4165S84.5A

-40°C - 85°C

X4163S8I4.5A

X4165S8I4.5A

8L TSSOP

0°C - 70°C

X4163V84.5A

X4165V84.5A

-40°C - 85°C

X4163V8I4.5A

X4165V8I4.5A

4.5-5.5V

4.25-4.5

8L SOIC

0°C - 70°C

X4163S8

X4165S8

-40°C - 85°C

X4163S8I

X4165S8I

8L TSSOP

0°C - 70°C

X4163V8

X4165V8

-40°C - 85°C

X4163V8I

X4165V8I

2.7-5.5V

2.85-3.0

8L SOIC

0°C - 70°C

X4163S82.7A

X4165S82.7A

-40°C - 85°C

X4163S8I2.7A

X4165S8I2.7A

8LTSSOP

0°C - 70°C

X4163V82.7A

X4165V82.7A

-40°C - 85°C

X4163V8I2.7A

X4165V8I2.7A

2.7-5.5V

2.55-2.7

8L SOIC

0°C - 70°C

X4163S82.7

X4165S82.7

-40°C - 85°C

X4163S8I2.7

X4165S8I2.7

8L TSSOP

0°C - 70°C

X4163V82.7

X4165V82.7

-40°C - 85°C

X4163V8I2.7

X4165V8I2.7

8-Lead TSSOP

EYWW

XXXXX

8-Lead SOIC

X4163/5 X

Blank = 8-Lead SOIC

ADB/ADK = -4.5A (0 to +70°C)

ADD/ADM = No Suffix (0 to +70°C)

ADF/ADO = -2.7A (0 to +70°C)

ADH/ADQ= -2.7 (0 to +70°C)

4163/4165

F = -2.7 (0 to +70°C)
G = -2.7 (-40 to +85°C)

Blank = No Suffix (0 to +70°C)

I = No Suffix (-40 to +85°C)
AN = -2.7A (0 to +70°C)
AP = -2.7A (-40 to +85°C)

AL = -4.5A (0 to +70°C)
AM = -4.5A (-40 to +85°C)

X4163, X4165

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X4165V8-2.7

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X4165V8-2.7