FN8128.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-352-6832

Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X5163, X5165

CPU Supervisor with 16Kbit SPI EEPROM

Description

These devices combine four popular functions, Power-on
Reset Control, Watchdog Timer, Supply Voltage Supervision,
and Block Lock Protect Serial EEPROM Memory in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.

Applying power to the device activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and oscillator to stabilize
before the processor can execute code.

The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller
fails to restart a timer within a selectable time out interval, the
device activates the RESET/RESET signal. The user selects
the interval from three preset values. Once selected, the
interval does not change, even after cycling the power.

The device's low V

detection circuitry protects the user's

system from low voltage conditions, resetting the system when
V

falls below the minimum V

trip point. RESET/RESET is

asserted until V

returns to proper operating level and

stabilizes. Five industry standard V

TRIP

thresholds are

available, however, Intersil's unique circuits allow the
threshold to be reprogrammed to meet custom requirements
or to fine-tune the threshold for applications requiring higher
precision.

Features

· Selectable watchdog timer

· Low V

detection and reset assertion

- Five standard reset threshold voltages
- Re-program low V

reset threshold voltage using

special programming sequence

- Reset signal valid to V

= 1V

· Determine watchdog or low voltage reset with a volatile

flag bit

· Long battery life with low power consumption

- <50µA max standby current, watchdog on
- <1µA max standby current, watchdog off
- <400µA max active current during read

· 16Kbits of EEPROM

· Built-in inadvertent write protection

- Power-up/power-down protection circuitry
- Protect 0, 1/4, 1/2 or all of EEPROM array with Block

Lock

protection

- In circuit programmable ROM mode

· 2MHz SPI interface modes (0,0 & 1,1)

· Minimize EEPROM programming time

- 32-byte page write mode
- Self-timed write cycle
- 5ms write cycle time (typical)

· 2.7V to 5.5V and 4.5V to 5.5V power supply operation

· Available packages

- 14-lead TSSOP, 8-lead SOIC

Pinouts

8-LEAD SOIC/PDIP

CS/WDI

RESET/RESET

14-LEAD TSSOP

RESET/RESET

SCK

X5163, X5165

SCK

CS/WDI

X5163, X5165

Data Sheet

May 16, 2005

FN8128.1

May 16, 2005

Block Diagram

Watchdog

Timer Reset

Data

Command

Decode &

Control

Logic

SCK

CS/WDI

Reset &

Watchdog

Timebase

Power-on and

Generation

TRIP

RESET/RESET

Reset

Low Voltage

Status

Protect Logic

4K Bits

8K Bits

EEPRO

r
ray

Watchdog Transition

Detector

X5163 = RESET

X5165 = RESET

Threshold

Reset Logic

Pin Description

PIN

(SOIC/PDIP)

PIN TSSOP

NAME

FUNCTION

CS/WDI

Chip Select Input.

CS HIGH, deselects the device and the SO output pin is at a high impedance

state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode.
CS LOW enables the device, placing it in the active power mode. Prior to the start of any
operation after power-up, a HIGH to LOW transition on CS is required
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The
absence of a HIGH to LOW transition within the watchdog time out period results in
RESET/RESET going active.

Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The
falling edge of the serial clock (SCK) clocks the data out.

Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to "lock" the setting
of the Watchdog Timer control and the memory write protect bits.

Ground

Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this
pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and data MSB first.

SCK

Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge
of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK
changes the data output on the SO pin.

RESET/

RESET

Reset Output.

RESET/RESET is an active LOW/HIGH, open drain output which goes active

whenever V

falls below the minimum V

sense level. It will remain active until V

rises above

the minimum V

sense level for 200ms. RESET/

RESET goes active if the Watchdog Timer is enabled and CS remains either HIGH or LOW longer
than the selectable Watchdog time out period. A falling edge of CS will reset the Watchdog Timer.
RESET/RESET goes active on power-up at 1V and remains active for 200ms after the power
supply stabilizes.

Supply Voltage

3-5,10-12

No internal connections

X5163, X5165

FN8128.1

May 16, 2005

Principles Of Operation

Power-on Reset

Application of power to the X516, /X5165 activates a Power-
on Reset Circuit. This circuit goes active at 1V and pulls the
RESET/RESET pin active. This signal prevents the system
microprocessor from starting to operate with insufficient
voltage or prior to stabilization of the oscillator. When V

exceeds the device V

TRIP

value for 200ms (nominal) the

circuit releases RESET/RESET, allowing the processor to
begin executing code.

Low Voltage Monitoring

During operation, the X5163, X5165 monitors the V

level

and asserts RESET/RESET if supply voltage falls below a
preset minimum V

TRIP

. The RESET/RESET signal prevents

the microprocessor from operating in a power fail or
brownout condition. The RESET/RESET signal remains
active until the voltage drops below 1V. It also remains active
until V

returns and exceeds V

TRIP

for 200ms.

Watchdog Timer

The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the WDI input. The microprocessor
must toggle the CS/WDI pin periodically to prevent a
RESET/RESET signal. The CS/WDI pin must be toggled
from HIGH to LOW prior to the expiration of the watchdog
time out period. The state of two nonvolatile control bits in
the Status Register determine the watchdog timer period.
The microprocessor can change these watchdog bits, or
they may be "locked" by tying the WP pin LOW and setting
the WPEN bit HIGH.

Threshold Reset Procedure

The X5163, X5165 has a standard V

threshold (V

TRIP

)

voltage. This value will not change over normal operating
and storage conditions. However, in applications where the
standard V

TRIP

is not exactly right, or for higher precision in

the V

TRIP

value, the X5163, X5165 threshold may be

adjusted.

Setting the V

TRIP

Voltage

This procedure sets the V

TRIP

to a higher voltage value. For

example, if the current V

TRIP

is 4.4V and the new V

TRIP

4.6V, this procedure directly makes the change. If the new
setting is lower than the current setting, then it is necessary
to reset the trip point before setting the new value.

To set the new V

TRIP

voltage, apply the desired V

TRIP

threshold to the V

pin and tie the CS/WDI pin and the WP

pin HIGH. RESET and SO pins are left unconnected. Then
apply the programming voltage V

to both SCK and SI and

pulse CS/WDI LOW then HIGH. Remove V

and the

sequence is complete.

Resetting the V

TRIP

Voltage

This procedure sets the V

TRIP

to a "native" voltage level. For

example, if the current V

TRIP

is 4.4V and the V

TRIP

is reset,

the new V

TRIP

is something less than 1.7V. This procedure

must be used to set the voltage to a lower value.

To reset the V

TRIP

voltage, apply a voltage between 2.7 and

5.5V to the V

pin. Tie the CS/WDI pin, the WP pin, AND

THE SCK pin HIGH. RESET and SO pins are left
unconnected. Then apply the programming voltage V

to the

SI pin ONLY and pulse CS/WDI LOW then HIGH. Remove V

and the sequence is complete.

SCK

FIGURE 1. SET V

TRIP

VOLTAGE

SCK

FIGURE 2. RESET V

TRIP

VOLTAGE

X5163, X5165

FN8128.1

May 16, 2005

TRIP

PROGRAMMING

APPLY 5V TO V

DECREMENT V

RESET PIN

GOES ACTIVE?

MEASURED V

TRIP

DESIRED V

TRIP

DONE

EXECUTE

SEQUENCE

RESET V

TRIP

SET V

= V

APPLIED =

DESIRED V

TRIP

EXECUTE

SEQUENCE

SET V

TRIP

NEW V

APPLIED =

OLD V

APPLIED + ERROR

= V

- 50MV)

EXECUTE

SEQUENCE

RESET V

TRIP

NEW V

APPLIED =

OLD V

APPLIED - ERROR

ERROR > -EMAX

ERROR < EMAX

YES

ERROR > EMAX

EMAX = MAXIMUM DESIRED ERROR

FIGURE 3. V

TRIP

PROGRAMMING SEQUENCE FLOW CHART

1
2
3
4

8
7
6
5

X5163, X5165

TRIP

ADJ.

PROGRAM

RESET V

TRIP

TEST

TRIP

SET V

TRIP

RESET

4.7K

10K

FIGURE 4. SAMPLE V

TRIP

RESET CIRCUIT

X5163, X5165

FN8128.1

May 16, 2005

SPI Serial Memory

The memory portion of the device is a CMOS Serial EEPROM
array with Intersil's block lock protection. The array is
internally organized as x 8. The device features a Serial
Peripheral Interface (SPI) and software protocol allowing
operation on a simple four-wire bus.

The device utilizes Intersil's proprietary Direct Write

cell,

providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.

The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input, with
data being clocked in on the rising edge of SCK. CS must be
LOW during the entire operation.

All instructions (Table 1), addresses and data are transferred
MSB first. Data input on the SI line is latched on the first
rising edge of SCK after CS goes LOW. Data is output on the
SO line by the falling edge of SCK. SCK is static, allowing
the user to stop the clock and then start it again to resume
operations where left off.

Write Enable Latch

The device contains a Write Enable Latch. This latch must
be SET before a Write Operation is initiated. The WREN
instruction will set the latch and the WRDI instruction will
reset the latch (Figure 7). This latch is automatically reset
upon a power-up condition and after the completion of a
valid Write Cycle.

Status Register

The RDSR instruction provides access to the Status
Register. The Status Register may be read at any time, even
during a Write Cycle. The Status Register is formatted as
follows:

The Write-In-Progress (WIP) bit is a volatile, read only bit
and indicates whether the device is busy with an internal
nonvolatile write operation. The WIP bit is read using the
RDSR instruction. When set to a "1", a nonvolatile write
operation is in progress. When set to a "0", no write is in
progress.

WPEN

FLB

WD1

WD0

BL1

BL0

WEL

WIP

TABLE 1. INSTRUCTION SET

INSTRUCTION NAME

INSTRUCTION FORMAT*

OPERATION

WREN

0000 0110

Set the Write Enable Latch (Enable Write Operations)

SFLB

0000 0000

Set Flag Bit

WRDI/RFLB

0000 0100

Reset the Write Enable Latch/Reset Flag Bit

RSDR

0000 0101

Read Status Register

WRSR

0000 0001

Write Status Register(Watchdog,BlockLock,WPEN & Flag Bits)

READ

0000 0011

Read Data from Memory Array Beginning at Selected Address

WRITE

0000 0010

Write Data to Memory Array Beginning at Selected Address

NOTE: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.

TABLE 2. BLOCK PROTECT MATRIX

WREN CMD

STATUS REGISTER

DEVICE PIN

BLOCK

STATUS REGISTER

WEL

WPEN

WP#

PROTECTED BLOCK

UNPROTECTED BLOCK

WPEN, BL0, BL1, WD0,

WD1

Protected

Writable

Protected

Writable

Protected

Writable

X5163, X5165

FN8128.1

May 16, 2005

The Write Enable Latch (WEL) bit indicates the Status of
the Write Enable Latch. When WEL = 1, the latch is set
HIGH and when WEL = 0 the latch is reset LOW. The WEL
bit is a volatile, read only bit. It can be set by the WREN
instruction and can be reset by the WRDS instruction.

The block lock bits, BL0 and BL1, set the level of block lock
protection. These nonvolatile bits are programmed using the
WRSR instruction and allow the user to protect one quarter,
one half, all or none of the EEPROM array. Any portion of
the array that is block lock protected can be read but not
written. It will remain protected until the BL bits are altered to
disable block lock protection of that portion of memory.

The Watchdog Timer bits, WD0 and WD1, select the
Watchdog Time Out Period. These nonvolatile bits are
programmed with the WRSR instruction.

The FLAG bit shows the status of a volatile latch that can be
set and reset by the system using the SFLB and RFLB
instructions. The Flag bit is automatically reset upon power-
up. This flag can be used by the system to determine
whether a reset occurs as a result of a watchdog time out or
power failure.

The nonvolatile WPEN bit is programmed using the WRSR
instruction. This bit works in conjunction with the WP pin to
provide an In-Circuit Programmable ROM function (Table
2). WP is LOW and WPEN bit programmed HIGH disables
all Status Register Write Operations.

In Circuit Programmable ROM Mode

This mechanism protects the block lock and Watchdog bits
from inadvertent corruption.

In the locked state (Programmable ROM Mode) the WP pin
is LOW and the nonvolatile bit WPEN is "1". This mode
disables nonvolatile writes to the device's Status Register.

Setting the WP pin LOW while WPEN is a "1" while an
internal write cycle to the Status Register is in progress will
not stop this write operation, but the operation disables
subsequent write attempts to the Status Register.

STATUS

REGISTER BITS

ARRAY ADDRESSES PROTECTED

BL1

BL0

X516X

None

$0600-$07FF

$0400-$07FF

$0000-$07FF

STATUS REGISTER BITS

WATCHDOG TIME OUT

(TYPICAL)

WD1

WD0

1.4 seconds

600 milliseconds

200 milliseconds

disabled

STATUS REGISTER BITS

WATCHDOG TIME OUT

(TYPICAL)

WD1

WD0

DATA OUT

SCK

MSB

HIGH IMPEDANCE

INSTRUCTION

16 BIT ADDRESS

FIGURE 5. READ EEPROM ARRAY SEQUENCE

X5163, X5165

FN8128.1

May 16, 2005

When WP is HIGH, all functions, including nonvolatile
writes to the Status Register operate normally. Setting the
WPEN bit in the Status Register to "0" blocks the WP pin
function, allowing writes to the Status Register when WP is
HIGH or LOW. Setting the WPEN bit to "1" while the WP pin
is LOW activates the Programmable ROM mode, thus
requiring a change in the WP pin prior to subsequent Status
Register changes. This allows manufacturing to install the
device in a system with WP pin grounded and still be able
to program the Status Register. Manufacturing can then
load Configuration data, manufacturing time and other
parameters into the EEPROM, then set the portion of
memory to be protected by setting the block lock bits, and
finally set the "OTP mode" by setting the WPEN bit. Data
changes now require a hardware change.

Read Sequence

When reading from the EEPROM memory array, CS is first
pulled low to select the device. The 8-bit READ instruction is
transmitted to the device, followed by the 16-bit address. After
the READ opcode and address are sent, the data stored in the
memory at the selected address is shifted out on the SO line.
The data stored in memory at the next address can be read
sequentially by continuing to provide clock pulses. The address
is automatically incremented to the next higher address after
each byte of data is shifted out. When the highest address is
reached, the address counter rolls over to address $0000
allowing the read cycle to be continued indefinitely. The read
operation is terminated by taking CS high. Refer to the Read
EEPROM Array Sequence (Figure 5).

To read the Status Register, the CS line is first pulled low to
select the device followed by the 8-bit RDSR instruction. After
the RDSR opcode is sent, the contents of the Status Register
are shifted out on the SO line. Refer to the Read Status
Register Sequence (Figure 6).

Write Sequence

Prior to any attempt to write data into the device, the "Write
Enable" Latch (WEL) must first be set by issuing the WREN
instruction (Figure 7). CS is first taken LOW, then the WREN
instruction is clocked into the device. After all eight bits of the
instruction are transmitted, CS must then be taken HIGH. If the
user continues the Write Operation without taking CS HIGH
after issuing the WREN instruction, the Write Operation will be
ignored.

To write data to the EEPROM memory array, the user then
issues the WRITE instruction followed by the 16 bit address
and then the data to be written. Any unused address bits are
specified to be "0's". The WRITE operation minimally takes
32 clocks. CS must go low and remain low for the duration of
the operation. If the address counter reaches the end of a
page and the clock continues, the counter will roll back to the
first address of the page and overwrite any data that may
have been previously written.

For the Page Write Operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of the
last data byte to be written is clocked in. If it is brought HIGH
at any other time, the write operation will not be completed
(Figure 8).

To write to the Status Register, the WRSR instruction is
followed by the data to be written (Figure 9). Data bits 0 and
1 must be "0".

While the write is in progress following a Status Register or
EEPROM Sequence, the Status Register may be read to
check the WIP bit. During this time the WIP bit will be high.

Operational Notes

The device powers-up in the following state:

· The device is in the low power standby state.

· A HIGH to LOW transition on CS is required to enter an

active state and receive an instruction.

· SO pin is high impedance.

· The Write Enable Latch is reset.

· The Flag Bit is reset.

· Reset Signal is active for t

PURST

Data Protection

The following circuitry has been included to prevent
inadvertent writes:

· A WREN instruction must be issued to set the Write Enable

Latch.

· CS must come HIGH at the proper clock count in order to

start a nonvolatile write cycle.

X5163, X5165

FN8128.1

May 16, 2005

Absolute Maximum Ratings

Recommended Operating Conditions

Temperature under bias . . . . . . . . . . . . . . . . . . . . . . . .-65 to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . .-65 to +150°C
Voltage on any pin with

respect to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +7V

D.C. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . 300°C

Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Specifications

Over operating conditions unless otherwise specified.

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

MIN

TYP

MAX

CC1

Write Current (Active)

SCK = V

x 0.1/V

x 0.9 @ 2MHz, SO =

Open

CC2

Read Current (Active)

SCK = V

x 0.1/V

x 0.9 @ 2MHz, SO =

Open

0.4

SB1

Standby Current WDT = OFF CS = V

, V

= V

or V

, V

= 5.5V

µA

SB2

Standby Current WDT = ON

CS = V

, V

= V

or V

, V

= 5.5V

µA

SB3

Standby Current WDT = ON

CS = V

, V

= V

or V

, V

= 3.6V 20

µA

Input Leakage Current

= V

to V

0.1

µA

Output Leakage Current

OUT

= V

to V

0.1

µA

(1)

Input LOW Voltage

-0.5

x 0.3

(1)

Input HIGH Voltage

x 0.7

+ 0.5

OL1

Output LOW Voltage

> 3.3V, I

= 2.1mA

0.4

OL2

Output LOW Voltage

2V < V

3.3V, I

= 1mA

0.4

OL3

Output LOW Voltage

2V, I

= 0.5mA

0.4

OH1

Output HIGH Voltage

> 3.3V, I

= 1.0mA

- 0.8

OH2

Output HIGH Voltage

2V < V

3.3V, I

= 0.4mA

- 0.4

OH3

Output HIGH Voltage

2V, I

= 0.25mA

- 0.2

OLS

Reset Output LOW Voltage

= 1mA

0.4

Capacitance T

= +25°C, f = 1MHz, V

= 5V

SYMBOL

TEST

MAX.

UNIT

CONDITIONS

OUT

(2)

Output Capacitance (SO, RESET, RESET)

OUT

= 0V

(2)

Input Capacitance (SCK, SI, CS, WP)

= 0V

NOTES:

1. V

min. and V

max. are for reference only and are not tested.

2. This parameter is periodically sampled and not 100% tested.

X5163, X5165

FN8128.1

May 16, 2005

OUTPUT

100pF

3.3k

RESET/RESET

30pF

1.64k

FIGURE 10. EQUIVALENT A.C. LOAD CIRCUIT AT 5V V

A.C. Test Conditions

Input pulse levels

x 0.1 to V

x 0.9

Input rise and fall times

10ns

Input and output timing level

x0.5

AC Electrical Specifications

Serial Input Timing

(Over operating conditions unless otherwise specified.)

SYMBOL

PARAMETER

2.7-5.5V

UNIT

MIN MAX

SCK

Clock Frequency

MHz

CYC

Cycle Time

500

LEAD

CS Lead Time

250

LAG

CS Lag Time

250

Clock HIGH Time

200

Clock LOW Time

200

Data Setup Time

Data Hold Time

(3)

Input Rise Time

100

(3)

Input Fall Time

100

CS Deselect Time

500

(4)

Write Cycle Time

SCK

MSB IN

LAG

LEAD

LSB IN

HIGH IMPEDANCE

FIGURE 11. SERIAL INPUT TIMING

X5163, X5165

FN8128.1

May 16, 2005

AC Electrical Specifications

Serial Output Timing

(Over operating conditions unless otherwise specified.)

SYMBOL

PARAMETER

2.7-5.5V

UNIT

MIN

MAX

SCK

Clock Frequency

MHz

DIS

Output Disable Time

250

Output Valid from Clock Low

200

Output Hold Time

(3)

Output Rise Time

100

(3)

Output Fall Time

100

NOTES:

3. This parameter is periodically sampled and not 100% tested.
4. t

is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.

SCK

MSB OUT

MSB1 OUT

LSB OUT

ADDR

LSB IN

CYC

DIS

LAG

TABLE 3. SERIAL OUTPUT TIMING

PURST

RPD

RESET (X5163)

0 Volts

TRIP

RESET (X5165)

TABLE 4. POWER-UP AND POWER-DOWN TIMING

X5163, X5165

FN8128.1

May 16, 2005

RESET Output Timing

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

TRIP

Reset Trip Point Voltage, X5163-4.5A, X5163-4.5A
Reset Trip Point Voltage, X5163, X5165
Reset Trip Point Voltage, X5163-2.7A, X5165-2.7A
Reset Trip Point Voltage, X5163-2.7, X5165-2.7

4.5

4.25
2.85
2.55

4.63
4.38
2.92
2.63

4.75

4.5
3.0
2.7

TRIP

Hysteresis (HIGH to LOW vs. LOW to HIGH V

TRIP

voltage)

PURST

Power-up Reset Time Out

100

200

280

RPD

(5)

Detect to Reset/Output

500

(5)

Fall Time

100

µs

(5)

Rise Time

100

µs

RVALID

Reset Valid V

NOTES:

5. This parameter is periodically sampled and not 100% tested.
6. Typical values not tested.

RESET/RESET Output Timing

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

WDO

Watchdog Time Out Period,

WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0

100
450

200
600

1.4

300
800

ms
ms

sec

CST

CS Pulse Width to Reset the Watchdog

400

RST

Reset Time Out

100

200

300

CS/WDI

CST

RESET

WDO

RST

RESET

WDO

RST

FIGURE 12. CS/WDI VS. RESET/RESET TIMING

X5163, X5165

FN8128.1

May 16, 2005

TRIP

Programming Specifications: V

= 1.7-5.5V; Temperature = 0°C to 70°C

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

VPS

SCK V

TRIP

Program Voltage Setup time

µs

VPH

SCK V

TRIP

Program Voltage Hold time

µs

TRIP

Program Pulse Width

µs

TSU

TRIP

Level Setup time

µs

THD

TRIP

Level Hold (stable) time

TRIP

Write Cycle Time

TRIP

Program Cycle Recovery Period (Between successive programming cycles)

VPO

SCK V

TRIP

Program Voltage Off time before next cycle

Programming Voltage

TRAN

TRIP

Programed Voltage Range

1.7

5.0

ta1

Initial V

TRIP

Program Voltage accuracy (

CC applied-V

TRIP

) (Programmed at 25°C.)

-0.1

+0.4

ta2

Subsequent V

TRIP

Program Voltage accuracy [(

CC applied-V

ta1

)-V

TRIP

] (Programmed at 25°C.)

-25

+25

TRIP

Program Voltage repeatability (Successive program operations.) (Programmed at 25°C.)

-25

+25

TRIP

Program variation after programming (0-75°C). (Programmed at 25°C.)

-25

+25

TRIP

programming parameters are periodically sampled and are not 100% tested.

X5163, X5165

FN8128.1

May 16, 2005

FIGURE 15. V

SUPPLY CURRENT VS. TEMPERATURE (I

)

FIGURE 16. t

WDO

VS. VOLTAGE/TEMPERATURE (WD1, 0 = 1, 1)

FIGURE 17. V

TRIP

vs. Temperature (programmed at 25°C)

FIGURE 18. t

WDO

VS. VOLTAGE/TEMPERATURE (WD1, 0 = 1, 0)

FIGURE 19. t

PURST

VS. TEMPERATURE

FIGURE 20. t

WDO

VS. VOLTAGE/TEMPERATURE (WD1, 0 0 = 0, 1)

WATCHDOG TIMER ON (V

= 5V)

WATCHDOG TIMER ON (V

= 5V)

WATCHDOG TIMER OFF (V

= 3V, 5V)

-40

TEMP (°C)

B (µA)

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.7

2.4

3.1

3.8

4.5

5.2

90°C

25°C

-40°C

RESET (SE

ONDS)

VOLTAGE

5.025

5.000

4.975

3.525

3.500

3.475

2.525

2.500

2.475

LTA

TEMPERATURE

TRIP

= 5V

TRIP

= 3.5V

TRIP

= 2.5V

0.8

0.75

0.7

0.65

0.6

0.55

0.5

0.45

1.7

5.2

SET (SE

ONDS)

VOLTAGE

2.4

3.1

3.8

4.5

90°C

25°C

-40°C

200

195

190

185

180

175

170

165

160

-40

DEGREES °C

205

TIME (

90°C

25°C

-40°C

200

195

190

185

180

175

170
165

160

205

RESE

T (S

ECONDS)

VOLTAGE

1.7

5.2

2.4

3.1

3.8

4.5

X5163, X5165

FN8128.1

May 16, 2005

Ordering Information

RANGE

TRIP

RANGE

PACKAGE

OPERATING TEMPERATURE

RANGE

PART NUMBER RESET

(ACTIVE LOW)

PART NUMBER RESET

(ACTIVE HIGH)

4.5-5.5V

4.5.4.75

8-Pin PDIP

0°C - 70°C

X5163P-4.5A

-40°C - 85°C

X5163PI-4.5A

X5165PI-4.5A

8L SOIC

0°C - 70°C

X5163S8-4.5A

X5165S8-4.5A

-40°C - 85°C

X5163S8I-4.5A

X5165S8I-4.5A

14L TSSOP

0°C - 70°C

X5163V14-4.5A

X5165V14-4.5A

-40°C - 85°C

X5163V14I-4.5A

X5165V14I-4.5A

4.5-5.5V

4.25.4.5

8-Pin PDIP

0°C - 70°C

X5163P

X5165P

-40°C - 85°C

X5163PI

X5165PI

8L SOIC

0°C - 70°C

X5163S8

X5165S8

0°C - 70°C

X51638S8

0°C - 70°C

X5163S8T1

X5165S8T1

0°C - 70°C

X5163S8T2

-40°C - 85°C

X5163S8I

X5165S8I

-40°C - 85°C

X5163S8IT1

X5165S8IT1

14L TSSOP

0°C - 70°C

X5163V14

X5165V14

0°C - 70°C

X5163V14T1

X5165V14T1

-40°C - 85°C

X5163V14I

X5165V14I

-40°C - 85°C

X5163V14IT1

X5165V14IT1

2.7-5.5V

2.85-3.0

8-Pin PDIP

0°C - 70°C

X5163P-2.7A

X5165P-2.7A

-40°C - 85°C

X5163PI-2.7A

X5165PI-2.7A

8L SOIC

0°C - 70°C

X5163S8-2.7A

X5165S8-2.7A

0°C - 70°C

X5163S8-2.7AT1

-40°C - 85°C

X5163S8I-2.7A

X5165S8I-2.7A

-40°C - 85°C

X5163S8I-2.7AT1

14L TSSOP

0°C - 70°C

X5163V14-2.7A

X5165V14-2.7A

-40°C - 85°C

X5163V14I-2.7A

X5165V14I-2.7A

-40°C - 85°C

X5163V14I-2.7T1

X5165V14I-2.7T1

2.7-5.5V

2.55-2.7

8-Pin PDIP

0°C - 70°C

X5163P-2.7

X5165P-2.7

-40°C - 85°C

X5163PI-2.7

X5165PI-2.7

8L SOIC

0°C - 70°C

X5163S8-2.7

X5165S8-2.7

0°C - 70°C

X5163S8-2.7T1

X5165S8-2.7T1

-40°C - 85°C

X5163S8I-2.7

X5165S8I-2.7

-40°C - 85°C

X5165S8I-2.7T1

14L TSSOP

0°C - 70°C

X5163V14-2.7

X5165V14-2.7

0°C - 70°C

X5163V14-2.7T1

X5165V14-2.7T1

-40°C - 85°C

X5163V14I-2.7

X5165V14I-2.7

X5163, X5165

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8128.1

May 16, 2005

Part Mark Information

Blank = 8-Lead SOIC
V = 14 Lead TSSOP

Blank = 5V ±10%, 0°C to +70°C, V

TRIP

= 4.25-4.5

A = 5V±10%, 0°C to +70°C, V

TRIP

= 4.5-4.75

I = 5V ±10%, -40°C to +85°C, V

TRIP

= 4.25-4.5

IA = 5V ±10%, -40°C to +85°C, V

TRIP

= 4.5-4.75

F = 2.7V to 5.5V, 0°C to +70°C, V

TRIP

= 2.55-2.7

FA = 2.7V to 5.5V, 0°C to +70°C, V

TRIP

= 2.85-3.0

G = 2.7V to 5.5V, -40°C to +85°C, V

TRIP

= 2.55-2.7

GA = 2.7V to 5.5V, -40°C to +85°C, V

TRIP

= 2.85-3.0

X5163, X51665

X5163, X5165

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X5165S8I-2.7T1

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X5165S8I-2.7T1