FN8132.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X5328, X5329

(Replaces X25328, X25329)

CPU Supervisor with 32Kbit SPI EEPROM

FEATURES

· Low V

detection and reset assertion

--Five standard reset threshold voltages
--Re-program low V

reset threshold voltage

using special programming sequence

--Reset signal valid to V

= 1V

· Long battery life with low power consumption

--<1µA max standby current
--<400µA max active current during read

· 32Kbits of EEPROM
· Built-in inadvertent write protection

--Power-up/power-down protection circuitry
--Protect 0, 1/4, 1/2 or all of EEPROM array with

Block Lock

protection

--In circuit programmable ROM mode

· 2MHz SPI interface modes (0,0 & 1,1)
· Minimize EEPROM programming time

--32-byte page write mode
--Self-timed write cycle
--5ms write cycle time (typical)

· 2.7V to 5.5V and 4.5V to 5.5V power supply

operation

· Available packages

--14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP

· Pb-free plus anneal available (RoHS compliant)

DESCRIPTION

These devices combine three popular functions, Power-
on Reset Control, Supply Voltage Supervision, and Block
Lock Protect Serial EEPROM Memory in one package.
This combination lowers system cost, reduces board
space requirements, and increases reliability.

Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.

The device's low V

detection circuitry protects the

user's system from low voltage conditions by holding
RESET/RESET active when V

falls below a mini-

mum V

trip point. RESET/RESET remains asserted

until V

returns to proper operating level and stabi-

lizes. Five industry standard V

TRIP

thresholds are

available, however, Intersil's unique circuits allow the
threshold to be reprogrammed to meet custom
requirements or to fine-tune the threshold in applica-
tions requiring higher precision.

BLOCK DIAGRAM

Data

Command

Decode &

Control

Logic

SCK

Reset

Timebase

Power-on and

Generation

TRIP

RESET/RESET

Reset

Low Voltage

Status

Protect Logic

8Kbits

16Kbits

EEPROM Array

X5328 = RESET
X5329 = RESET

Data Sheet

October 17, 2005

FN8132.1

October 17, 2005

Ordering Information

PART NUMBER

RESET

(ACTIVE LOW)

PART

MARKING

PART NUMBER

RESET

(ACTIVE HIGH)

PART

MARKING

RANGE

(V)

TRIP

RANGE

TEMP

RANGE (°C)

PACKAGE

X5328P-4.5A

X5329P-4.5A

4.5-5.5

4.5-4.75

0 to 70

8 Ld PDIP

X5328PZ-4.5A (Note) X5328P Z AL X5329PZ-4.5A (Note) X5329P Z AL

0 to 70

8 Ld PDIP (Pb-free)

X5328PI-4.5A

X5329PI-4.5A

-40 to 85

8 Ld PDIP

X5328PIZ-4.5A (Note) X5328P Z AM X5329PIZ-4.5A (Note) X5329P Z AM

-40 to 85

8 Ld PDIP (Pb-free)

X5328S8-4.5A

X5328 AL

X5329S8-4.5A

0 to 70

8 Ld SOIC

X5328S8Z-4.5A (Note) X5328 Z AL

X5329S8Z-4.5A (Note) X5329 Z AL

0 to 70

8 Ld SOIC (Pb-free)

X5328S8I-4.5A

X5328 AM

X5329S8I-4.5A

-40 to 85

8 Ld SOIC

X5328S8IZ-4.5A
(Note)

X5328 Z AM

X5329S8IZ-4.5A
(Note)

X5329 Z AM

-40 to 85

8 Ld SOIC (Pb-free)

X5328V14-4.5A

X5329V14-4.5A

0 to 70

14 Ld TSSOP

X5328V14Z-4.5A
(Note)

X5328V Z AL X5329V14Z-4.5A

(Note)

X5329V Z AL

0 to 70

14 Ld TSSOP
(Pb-free)

X5328V14I-4.5A

X5329V14I-4.5A

-40 to 85

14 Ld TSSOP

X5328V14IZ-4.5A
(Note)

X5328V Z AM X5329V14IZ-4.5A

(Note)

X5329V Z AM

-40 to 85

14 Ld TSSOP
(Pb-free)

X5328P

X5329P

4.5-5.5

4.25-4.5

0 to 70

8 Ld PDIP

X5328PZ (Note)

X5328P Z

X5329PZ (Note)

X5329P Z

0 to 70

8 Ld PDIP (Pb-free)

X5328PI

X5328P I

X5329PI

X5329P I

-40 to 85

8 Ld PDIP

X5328PIZ (Note)

X5328P Z I

X5329PIZ (Note)

X5329P Z I

-40 to 85

8 Ld PDIP (Pb-free)

X5328S8*

X5328

X5329S8*

0 to 70

8 Ld SOIC

X5328S8Z* (Note)

X5328 Z

X5329S8Z* (Note)

X5329 Z

0 to 70

8 Ld SOIC (Pb-free)

X5328S8I*

X5328 I

X5329S8I*

-40 to 85

8 Ld SOIC

X5328S8IZ* (Note)

X5328 Z I

X5329S8IZ* (Note)

X5329 Z I

-40 to 85

8 Ld SOIC (Pb-free)

X5328V14*

X5328V

X5329V14*

0 to 70

14 Ld TSSOP

X5328V14Z* (Note)

X5328V Z

X5329V14Z* (Note)

X5329V Z

0 to 70

14 Ld TSSOP
(Pb-free)

X5328V14I*

X5329V14I*

-40 to 85

14 Ld TSSOP

X5328V14IZ* (Note)

X5328V Z I

X5329V14IZ* (Note)

X5329V Z I

-40 to 85

14 Ld TSSOP
(Pb-free)

X5328P-2.7A

X5329P-2.7A

2.7-5.5

2.85-3.0

0 to 70

8 Ld PDIP

X5328PZ-2.7A (Note) X5328P Z AN X5329PZ-2.7A (Note) X5329P Z AN

0 to 70

8 Ld PDIP (Pb-free)

X5328PI-2.7A

X5329PI-2.7A

-40 to 85

8 Ld PDIP

X5328PIZ-2.7A (Note) X5328P Z AP X5329PIZ-2.7A (Note) X5329P Z AP

-40 to 85

8 Ld PDIP (Pb-free)

X5328S8-2.7A

X5328 AN

X5329S8-2.7A

0 to 70

8 Ld SOIC

X5328S8Z-2.7A (Note) X5328 Z AN

X5329S8Z-2.7A (Note) X5329 Z AN

0 to 70

8 Ld SOIC (Pb-free)

X5328S8I-2.7A

X5328 AP

X5329S8I-2.7A

-40 to 85

8 Ld SOIC

X5328S8IZ-2.7A
(Note)

X5328 Z AP

X5329S8IZ-2.7A
(Note)

X5329 Z AP

-40 to 85

8 Ld SOIC (Pb-free)

X5328V14-2.7A

X5328V AN

X5329V14-2.7A

0 to 70

14 Ld TSSOP

X5328V14Z-2.7A
(Note)

X5328V Z AN X5329V14Z-2.7A

(Note)

X5329V Z AN

0 to 70

14 Ld TSSOP
(Pb-free)

X5328, X5329

FN8132.1

October 17, 2005

X5328V14I-2.7A

X5329V14I-2.7A

2.7-5.5

2.85-3.0

-40 to 85

14 Ld TSSOP

X5328V14IZ-2.7A
(Note)

X5328V Z AP X5329V14IZ-2.7A

(Note)

X5329V Z AP

-40 to 85

14 Ld TSSOP
(Pb-free)

X5328P-2.7

X5328P F

X5329P-2.7

X5329P F

2.7-5.5

2.55-2.7

0 to 70

8 Ld PDIP

X5328PZ-2.7 (Note)

X5328P Z F

X5329PZ-2.7 (Note)

X5329P Z F

0 to 70

8 Ld PDIP (Pb-free)

X5328PI-2.7

X5328P G

X5329PI-2.7

X5329P G

-40 to 85

8 Ld PDIP

X5328PIZ-2.7 (Note)

X5328P Z G

X5329PIZ-2.7 (Note)

X5329P Z G

-40 to 85

8 Ld PDIP (Pb-free)

X5328S8-2.7*

X5328 F

X5329S8-2.7*

0 to 70

8 Ld SOIC

X5328S8Z-2.7* (Note) X5328 Z F

X5329S8Z-2.7* (Note) X5329 Z F

0 to 70

8 Ld SOIC (Pb-free)

X5328S8I-2.7*

X5328 G

X5329S8I-2.7*

-40 to 85

8 Ld SOIC

X5328S8IZ-2.7* (Note) X5328 Z G

X5329S8IZ-2.7* (Note) X5329 Z G

-40 to 85

8 Ld SOIC (Pb-free)

X5328V14-2.7*

X5329V14-2.7*

0 to 70

14 Ld TSSOP

X5328V14Z-2.7*
(Note)

X5328V Z F

X5329V14Z-2.7*
(Note)

X5329V Z F

0 to 70

14 Ld TSSOP
(Pb-free)

X5328V14I-2.7*

X5329V14I-2.7*

-40 to 85

14 Ld TSSOP

X5328V14IZ-2.7*
(Note)

X5328V Z G

X5329V14IZ-2.7*
(Note)

X5329V Z G

-40 to 85

14 Ld TSSOP
(Pb-free)

*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Ordering Information

(Continued)

PART NUMBER

RESET

(ACTIVE LOW)

PART

MARKING

PART NUMBER

RESET

(ACTIVE HIGH)

PART

MARKING

RANGE

(V)

TRIP

RANGE

TEMP

RANGE (°C)

PACKAGE

X5328, X5329

FN8132.1

October 17, 2005

PIN DESCRIPTION

PIN CONFIGURATION

Pin

(SOIC/PDIP)

Pin

TSSOP

Name

Function

Chip Select Input.

CS HIGH, deselects the device and the SO output pin is at

a high impedance state. Unless a nonvolatile write cycle is underway, the device

will be in the standby power mode. CS LOW enables the device, placing it in the

active power mode. Prior to the start of any operation after power-up, a HIGH to

LOW transition on CS is required.

Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out

on this pin. The falling edge of the serial clock (SCK) clocks the data out.

Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and

memory data on this pin. The rising edge of the serial clock (SCK) latches the input

data. Send all opcodes (Table 1), addresses and data MSB first.

SCK

Serial Clock. The Serial Clock controls the serial bus timing for data input and out-

put. The rising edge of SCK latches in the opcode, address, or data bits present on

the SI pin. The falling edge of SCK changes the data output on the SO pin.

Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to

"lock" the setting of the Watchdog Timer control and the memory write protect bits.

Ground

Supply Voltage

RESET/

RESET

Reset Output. RESET/RESET is an active LOW/HIGH, open drain output

which goes active whenever V

falls below the minimum V

sense level. It

will remain active until V

rises above the minimum V

sense level for 200ms.

RESET/RESET goes active on power-up at about 1V and remains active for

200ms after the power supply stabilizes.

3-5,10-12

No internal connections

8 Ld SOIC/PDIP

RESET/RESET

14 Ld TSSOP

2
3

4
5

6
7

RESET/RESET

SCK
SI

13
12

11
10

X5328/29

SCK

NC
NC

X5328/29

X5328, X5329

FN8132.1

October 17, 2005

PRINCIPLES OF OPERATION

Power-On Reset
Application of power to the X5328/X5329 activates a
Power-on Reset Circuit. This circuit goes active at
about 1V and pulls the RESET/RESET pin active. This
signal prevents the system microprocessor from start-
ing to operate with insufficient voltage or prior to stabi-
lization of the oscillator. When V

exceeds the device

TRIP

value for 200ms (nominal) the circuit releases

RESET/RESET, allowing the processor to begin exe-
cuting code.

Low Voltage Monitoring
During operation, the X5328/X5329 monitors the V

level and asserts RESET/RESET if supply voltage
falls below a preset minimum V

TRIP

. The

RESET/RESET signal prevents the microprocessor
from operating in a power fail or brownout condition.
The RESET/RESET signal remains active until the
voltage drops below 1V. It also remains active until
V

returns and exceeds V

TRIP

for 200ms.

Threshold Reset Procedure

The X5328/X5329 has a standard V

threshold

TRIP

) voltage. This value will not change over normal

operating and storage conditions. However, in applica-
tions where the standard V

TRIP

is not exactly right, or

for higher precision in the V

TRIP

value, the

X5328/X5329 threshold may be adjusted.

Setting the V

TRIP

Voltage

This procedure sets the V

TRIP

to a higher voltage

value. For example, if the current V

TRIP

is 4.4V and

the new V

TRIP

is 4.6V, this procedure directly makes

the change. If the new setting is lower than the current
setting, then it is necessary to reset the trip point
before setting the new value.

To set the new V

TRIP

voltage, apply the desired V

TRIP

threshold to the V

pin and tie the CS pin and the WP

pin HIGH. RESET/RESET and SO pins are left uncon-
nected. Then apply the programming voltage V

both SCK and SI and pulse CS LOW then HIGH.
Remove V

and the sequence is complete.

Figure 1. Set V

TRIP

Voltage

Resetting the V

TRIP

Voltage

This procedure sets the V

TRIP

to a "native" voltage

level. For example, if the current V

TRIP

is 4.4V and the

TRIP

is reset, the new V

TRIP

is something less than

1.7V. This procedure must be used to set the voltage
to a lower value.

To reset the V

TRIP

voltage, apply a voltage between

2.7 and 5.5V to the V

pin. Tie the CS pin, the WP

pin, and the SCK pin HIGH. RESET/RESET and SO
pins are left unconnected. Then apply the program-
ming voltage V

to the SI pin ONLY and pulse CS

LOW then HIGH. Remove V

and the sequence is

complete.

Figure 2. Reset V

TRIP

Voltage

SCK

X5328, X5329

FN8132.1

October 17, 2005

Figure 3. V

TRIP

Programming Sequence Flow Chart

Figure 4. Sample V

TRIP

Reset Circuit

TRIP

Programming

Apply 5V to V

Decrement V

RESET pin

goes active?

Measured V

TRIP

Desired V

TRIP

DONE

Execute

Sequence

Reset V

TRIP

Set V

= V

Applied =

Desired V

TRIP

Execute

Sequence

Set V

TRIP

New V

Applied =

Old V

Applied + Error

= V

- 10mV)

Execute

Sequence

Reset V

TRIP

New V

Applied =

Old V

Applied - Error

Error

Emax

Error < Emax

YES

Error > Emax

Emax = Maximum Desired Error

1
2
3
4

8
7
6
5

X5328/29

TRIP

Adj.

Program

Reset

TRIP

Test

TRIP

Set

TRIP

RESET

4.7K

10K

X5328, X5329

FN8132.1

October 17, 2005

SPI SERIAL MEMORY

The memory portion of the device is a CMOS Serial
EEPROM array with Intersil's block lock protection. The
array is internally organized as x 8. The device features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.

The device utilizes Intersil's proprietary Direct Write

cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.

The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input,
with data being clocked in on the rising edge of SCK.
CS must be LOW during the entire operation.

All instructions (Table 1), addresses and data are
transferred MSB first. Data input on the SI line is
latched on the first rising edge of SCK after CS goes
LOW. Data is output on the SO line by the falling edge
of SCK. SCK is static, allowing the user to stop the
clock and then start it again to resume operations
where left off.

Write Enable Latch
The device contains a Write Enable Latch. This latch
must be SET before a Write Operation is initiated. The
WREN instruction will set the latch and the WRDI
instruction will reset the latch (Figure 3). This latch is
automatically reset upon a power-up condition and
after the completion of a valid Write Cycle.

Status Register
The RDSR instruction provides access to the Status
Register. The Status Register may be read at any
time, even during a Write Cycle. The Status Register
is formatted as follows:

*Bits (5,4) should be written as `1' only.

The Write-In-Progress (WIP) bit is a volatile, read only
bit and indicates whether the device is busy with an
internal nonvolatile write operation. The WIP bit is read
using the RDSR instruction. When set to a "1", a non-
volatile write operation is in progress. When set to a
"0", no write is in progress.

Table 1. Instruction Set

Note:

*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.

Table 2. Block Protect Matrix

WPEN

FLB

BL1 BL0

WEL

WIP

Instruction Name

Instruction Format*

Operation

WREN

0000 0110

Set the Write Enable Latch (Enable Write Operations)

SFLB

0000 0000

Set Flag Bit

WRDI/RFLB

0000 0100

Reset the Write Enable Latch/Reset Flag Bit

RSDR

0000 0101

Read Status Register

WRSR

0000 0001

Write Status Register (Block Lock, WPEN & Flag Bits)

READ

0000 0011

Read Data from Memory Array Beginning at Selected Address

WRITE

0000 0010

Write Data to Memory Array Beginning at Selected Address

WREN CMD

Status Register

Device Pin

Block

Status Register

WEL

WPEN

WP#

Protected Block

Unprotected Block

WPEN, BL0, BL1,

WD0, WD1

Protected

Writable

Protected

Writable

Protected

Writable

X5328, X5329

FN8132.1

October 17, 2005

The Write Enable Latch (WEL) bit indicates the Status
of the Write Enable Latch. When WEL = 1, the latch is
set HIGH and when WEL = 0 the latch is reset LOW.
The WEL bit is a volatile, read only bit. It can be set by
the WREN instruction and can be reset by the WRDS
instruction.

The block lock bits, BL0 and BL1, set the level of block
lock protection. These nonvolatile bits are pro-
grammed using the WRSR instruction and allow the
user to protect one quarter, one half, all or none of the
EEPROM array. Any portion of the array that is block
lock protected can be read but not written. It will
remain protected until the BL bits are altered to disable
block lock protection of that portion of memory.

The FLAG bit shows the status of a volatile latch that
can be set and reset by the system using the SFLB and
RFLB instructions. The Flag bit is automatically reset
upon power-up.

The nonvolatile WPEN bit is programmed using the
WRSR instruction. This bit works in conjunction with the
WP pin to provide an In-Circuit Programmable ROM

function (Table 2). WP is LOW and WPEN bit pro-
grammed HIGH disables all Status Register Write
Operations.

In Circuit Programmable ROM Mode
This mechanism protects the block lock and Watchdog
bits from inadvertent corruption.

In the locked state (

Programmable ROM Mode) the WP

pin is LOW and the nonvolatile bit WPEN is "1". This
mode disables nonvolatile writes to the device's Status
Register.

Setting the WP pin LOW while WPEN is a "1" while an
internal write cycle to the Status Register is in progress
will not stop this write operation, but the operation dis-
ables subsequent write attempts to the Status Register.

When WP is HIGH, all functions, including nonvolatile
writes to the Status Register operate normally.

Setting the WPEN bit in the Status Register to "0"
blocks the WP pin function, allowing writes to the Status
Register when WP is HIGH or LOW. Setting the WPEN
bit to "1" while the WP pin is LOW activates the Pro-
grammable ROM mode, thus requiring a change in the
WP pin prior to subsequent Status Register changes.
This allows manufacturing to install the device in a sys-
tem with WP pin grounded and still be able to program
the Status Register. Manufacturing can then load Con-
figuration data, manufacturing time and other parame-
ters into the EEPROM, then set the portion of memory
to be protected by setting the block lock bits, and finally
set the "OTP mode" by setting the WPEN bit. Data
changes now require a hardware change.

Figure 5. Read EEPROM Array Sequence

Status Register Bits Array Addresses Protected

BL1

BL0

X5328/X5329

None

$0C00-$0FFF

$0800-$0FFF

$0000-$0FFF

20 21 22 23 24 25 26 27 28 29 30

Data Out

SCK

MSB

High Impedance

Instruction

16 Bit Address

15 14 13

X5328, X5329

FN8132.1

October 17, 2005

Read Sequence
When reading from the EEPROM memory array, CS is
first pulled low to select the device. The 8-bit READ
instruction is transmitted to the device, followed by the
16-bit address. After the READ opcode and address
are sent, the data stored in the memory at the selected
address is shifted out on the SO line. The data stored
in memory at the next address can be read sequen-
tially by continuing to provide clock pulses. The
address is automatically incremented to the next
higher address after each byte of data is shifted out.
When the highest address is reached, the address
counter rolls over to address $0000 allowing the read
cycle to be continued indefinitely. The read operation
is terminated by taking CS high. Refer to the Read
EEPROM Array Sequence (Figure 1).

To read the Status Register, the CS line is first pulled
low to select the device followed by the 8-bit RDSR
instruction. After the RDSR opcode is sent, the contents
of the Status Register are shifted out on the SO line.
Refer to the Read Status Register Sequence (Figure 2).

Write Sequence
Prior to any attempt to write data into the device, the
"Write Enable" Latch (WEL) must first be set by issu-
ing the WREN instruction (Figure 3). CS is first taken
LOW, then the WREN instruction is clocked into the
device. After all eight bits of the instruction are trans-
mitted, CS must then be taken HIGH. If the user con-
tinues the Write Operation without taking CS HIGH
after issuing the WREN instruction, the Write Opera-
tion will be ignored.

To write data to the EEPROM memory array, the user
then issues the WRITE instruction followed by the
16-bit address and then the data to be written. Any
unused address bits are specified to be "0's". The
WRITE operation minimally takes 32 clocks. CS must
go low and remain low for the duration of the opera-
tion. If the address counter reaches the end of a page
and the clock continues, the counter will roll back to
the first address of the page and overwrite any data
that may have been previously written.

For the Page Write Operation (byte or page write) to
be completed, CS can only be brought HIGH after bit 0
of the last data byte to be written is clocked in. If it is
brought HIGH at any other time, the write operation
will not be completed (Figure 4).

To write to the Status Register, the WRSR instruction
is followed by the data to be written (Figure 5). Data
bits 0 and 1 must be "0".

While the write is in progress following a Status Regis-
ter or EEPROM Sequence, the Status Register may
be read to check the WIP bit. During this time the WIP
bit will be high.

OPERATIONAL NOTES

The device powers-up in the following state:

The device is in the low power standby state.
A HIGH to LOW transition on CS is required to enter

an active state and receive an instruction.

SO pin is high impedance.
The Write Enable Latch is reset.
The Flag Bit is reset.
Reset Signal is active for t

PURST

Data Protection
The following circuitry has been included to prevent
inadvertent writes:

A WREN instruction must be issued to set the Write

Enable Latch.

CS must come HIGH at the proper clock count in

order to start a nonvolatile write cycle.

X5328, X5329

FN8132.1

October 17, 2005

Figure 6. Read Status Register Sequence

Figure 7. Write Enable Latch Sequence

Figure 8. Write Sequence

9 10 11 12 13 14

SCK

MSB

High Impedance

Instruction

Data Out

SCK

High Impedance

32 33 34 35 36 37 38 39

SCK

Instruction

16 Bit Address

Data Byte 1

40 41 42 43 44 45 46 47

Data Byte 2

Data Byte 3

15 14 13

20 21 22 23 24 25 26 27 28 29 30 31

Data Byte N

X5328, X5329

FN8132.1

October 17, 2005

ABSOLUTE MAXIMUM RATINGS

Temperature under bias .................... -65°C to +135°C
Storage temperature ........................ -65°C to +150°C
Voltage on any pin with

respect to V

...................................... -1.0V to +7V

D.C. output current ............................................... 5mA
Lead temperature (soldering, 10s) .................... 300°C

COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

CAPACITANCE T

= +25°C, f = 1MHz, V

= 5V

Notes: (1) V

min. and V

max. are for reference only and are not tested.

(2) This parameter is periodically sampled and not 100% tested.

Symbol

Parameter

Limits

Unit

Test Conditions

Min.

Typ.

Max.

CC1

Write Current (Active)

SCK = V

x 0.1/V

x 0.9 @ 2MHz,

SO = Open

CC2

Read Current (Active)

0.4

SCK = V

x 0.1/V

x 0.9 @ 2MHz,

SO = Open

Standby Current

µA

CS = V

, V

= V

or V

= 5.5V

Input Leakage Current

0.1

µA

= V

to V

Output Leakage Current

0.1

µA

OUT

= V

to V

(1)

Input LOW Voltage

-0.5

x 0.3

(1)

Input HIGH Voltage

x 0.7

+ 0.5

OL1

Output LOW Voltage

0.4

> 3.3V, I

= 2.1mA

OL2

Output LOW Voltage

0.4

2V < V

3.3V, I

= 1mA

OL3

Output LOW Voltage

0.4

2V, I

= 0.5mA

OH1

Output HIGH Voltage

- 0.8

> 3.3V, I

= -1.0mA

OH2

Output HIGH Voltage

- 0.4

2V < V

3.3V, I

= -0.4mA

OH3

Output HIGH Voltage

- 0.2

2V, I

= -0.25mA

OLS

Reset Output LOW Voltage

0.4

= 1mA

Symbol

Test

Max.

Unit

Conditions

OUT

(2)

Output Capacitance (SO, RESET, RESET)

OUT

= 0V

(2)

Input Capacitance (SCK, SI, CS, WP)

= 0V

RECOMMENDED OPERATING CONDITIONS

Temperature

Min.

Max.

Commercial

0°C

70°C

Industrial

-40°C

+85°C

Voltage Option

Supply Voltage

-2.7 or -2.7A

2.7V to 5.5V

BLank or -4.5A

4.5V-5.5V

X5328, X5329

FN8132.1

October 17, 2005

EQUIVALENT A.C. LOAD CIRCUIT AT 5V V

A.C. TEST CONDITIONS

A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)

Serial Input Timing

Output

100pF

4.6k

RESET/RESET

30pF

2.06k

3.03k

Input pulse levels

x 0.1 to V

x 0.9

Input rise and fall times

10ns

Input and output timing level

x0.5

Symbol

Parameter

2.7-5.5V

Unit

Min.

Max.

SCK

Clock Frequency

MHz

CYC

Cycle Time

500

LEAD

CS Lead Time

250

LAG

CS Lag Time

250

Clock HIGH Time

200

Clock LOW Time

250

Data Setup Time

Data Hold Time

(3)

Input Rise Time

100

(3)

Input Fall Time

100

CS Deselect Time

500

(4)

Write Cycle Time

X5328, X5329

FN8132.1

October 17, 2005

Serial Input Timing

Serial Output Timing

Notes: (3) This parameter is periodically sampled and not 100% tested.

(4) t

is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile

write cycle.

Serial Output Timing

SCK

MSB IN

LAG

LEAD

LSB IN

High Impedance

Symbol Parameter

2.7-5.5V

Unit

Min.

Max.

SCK

Clock Frequency

MHz

DIS

Output Disable Time

250

Output Valid from Clock Low

250

Output Hold Time

(3)

Output Rise Time

100

(3)

Output Fall Time

100

SCK

MSB Out

MSB1 Out

LSB Out

ADDR

LSB IN

CYC

DIS

LAG

X5328, X5329

FN8132.1

October 17, 2005

Power-Up and Power-Down Timing

RESET Output Timing

Note:

(5) This parameter is periodically sampled and not 100% tested.

Symbol

Parameter

Min.

Typ.

Max.

Unit

TRIP

Reset Trip Point Voltage, X5328-4.5A, X5328-4.5A
Reset Trip Point Voltage, X5328, X5329
Reset Trip Point Voltage, X5328-2.7A, X5329-2.7A
Reset Trip Point Voltage, X5328-2.7, X5329-2.7

4.5

4.25
2.85
2.55

4.63
4.38
2.93
2.63

4.75

4.5
3.0
2.7

TRIP

Hysteresis (HIGH to LOW vs. LOW to HIGH V

TRIP

voltage)

PURST

Power-up Reset Time Out

100

200

280

RPD

(5)

Detect to Reset/Output

500

(5)

Fall Time

100

µs

(5)

Rise Time

100

µs

RVALID

Reset Valid V

PURST

RPD

RESET (X5328)

0 Volts

TRIP

RESET (X5329)

TRIP

PURST

X5328, X5329

FN8132.1

October 17, 2005

TRIP

Programming Specifications V

= 1.7-5.5V; Temperature = 0°C to 70°C

Parameter

Description

Min. Max. Unit

VPS

SCK V

TRIP

Program Voltage Setup time

µs

VPH

SCK V

TRIP

Program Voltage Hold time

µs

TRIP

Program Pulse Width

µs

TSU

TRIP

Level Setup time

µs

THD

TRIP

Level Hold (stable) time

TRIP

Write Cycle Time

TRIP

Program Cycle Recovery Period (Between successive programming cycles)

VPO

SCK V

TRIP

Program Voltage Off time before next cycle

Programming Voltage

TRAN

TRIP

Programed Voltage Range

1.7

5.0

ta1

Initial V

TRIP

Program Voltage accuracy (V

applied-V

TRIP

) (Programmed at 25°C.)

-0.1

+0.4

ta2

Subsequent V

TRIP

Program Voltage accuracy [(V

applied-V

ta1

)-V

TRIP

]

(Programmed at 25°C.)

-25

+25

TRIP

Program Voltage repeatability (Successive program operations.) (programmed at

25°C)

-25

+25

TRIP

Program variation after programming (0-75°C). (programmed at 25°C)

-25

+25

TRIP

programming parameters are periodically sampled and are not 100% tested.

X5328, X5329

FN8132.1

October 17, 2005

PACKAGING INFORMATION

NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH

0.020 (0.51)
0.016 (0.41)

0.150 (3.81)
0.125 (3.18)

0.110 (2.79)
0.090 (2.29)

0.430 (10.92)

0.360 (9.14)

0.300

(7.62) Ref.

Pin 1 Index

0.145 (3.68)
0.128 (3.25)

0.025 (0.64)
0.015 (0.38)

Pin 1

Seating

0.065 (1.65)
0.045 (1.14)

0.260 (6.60)
0.240 (6.10)

0.060 (1.52)
0.020 (0.51)

Typ. 0.010 (0.25)

0°

15°

8-Lead Plastic Dual In-Line Package Type P

Half Shoulder Width On

All End Pins Optional

.073 (1.84)

Max.

0.325 (8.25)
0.300 (7.62)

Plane

X5328, X5329

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8132.1

October 17, 2005

PACKAGING INFORMATION

0.150 (3.80)
0.158 (4.00)

0.228 (5.80)
0.244 (6.20)

0.014 (0.35)
0.020 (0.51)

Pin 1

Pin 1 Index

0.050 (1.27)

0.336 (8.55)
0.345 (8.75)

0.004 (0.10)
0.010 (0.25)

0.053 (1.35)
0.069 (1.75)

(4X) 7°

14-Lead Plastic Small Outline Gullwing Package Type S

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

0.250"

0.050"Typical

0.030"Typical

14 Places

FOOTPRINT

0.010 (0.25)
0.020 (0.50)

0.016 (0.410)
0.037 (0.937)

0.0075 (0.19)

0.010 (0.25)

0° - 8°

X 45°

X5328, X5329

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X5328S8I-2.7A

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X5328S8I-2.7A