FN8135.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-352-6832

Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

X5643, X5645

(Replaces X25643, X25645)

CPU Supervisor with 64Kbit SPI EEPROM

FEATURES

· Selectable watchdog timer
· Low V

detection and reset assertion

--Five standard reset threshold voltages
--Re-program low V

reset threshold voltage

using special programming sequence

--Reset signal valid to V

= 1V

· Determine watchdog or low voltage reset with a

volatile flag bit

· Long battery life with low power consumption

--<50µA max standby current, watchdog on
--<1µA max standby current, watchdog off
--<400µA max active current during read

· 64Kbits of EEPROM
· Built-in inadvertent write protection

--Power-up/power-down protection circuitry
--Protect 0, 1/4, 1/2 or all of EEPROM array with

Block Lock

protection

--In circuit programmable ROM mode

· 2MHz SPI interface modes (0,0 & 1,1)
· Minimize EEPROM programming time

--32-byte page write mode
--Self-timed write cycle
--5ms write cycle time (typical)

· 2.7V to 5.5V and 4.5V to 5.5V power supply

operation

· Available packages

--8-lead PDIP, 14-lead SOIC

DESCRIPTION

These devices combine four popular functions, Power-
on Reset Control, Watchdog Timer, Supply Voltage
Supervision, and Block Lock Protect Serial EEPROM
Memory in one package. This combination lowers sys-
tem cost, reduces board space requirements, and
increases reliability.

Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.

The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcon-
troller fails to restart a timer within a selectable time out
interval, the device activates the RESET/RESET signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even after
cycling the power.

The device's low V

detection circuitry protects the

user's system from low voltage conditions, resetting
the system when V

falls below the minimum V

trip point. RESET/RESET is asserted until V

returns

to proper operating level and stabilizes. Five industry
standard V

TRIP

thresholds are available, however,

Intersil's unique circuits allow the threshold to be repro-
grammed to meet custom requirements or to fine-tune
the threshold for applications requiring higher precision.

BLOCK DIAGRAM

Watchdog

Timer Reset

Data

Command

Decode &

Control

Logic

SCK

CS/WDI

Reset &

Watchdog

Timebase

Power-on and

Generation

TRIP

RESET/RESET

Reset

Low Voltage

Status

Protect Logic

16Kbits

32Kbits

EEPROM Arr

Watchdog Transition

Detector

Threshold

Reset logic

X5643 = RESET
X5645 = RESET

Data Sheet

July 18, 2005

FN8135.1

July 18, 2005

PIN CONFIGURATION

8-Lead PDIP

CS/WDI

RESET/RESET

14-Lead SOIC

RESET/RESET

SCK

X5643/45

SCK

CS/WDI

X5643/45

CS/WDI

Pin

PDIP

Pin

SOIC

Pin

TSSOP

Name

Function

2 & 3

CS/WDI

Chip Select Input.

CS HIGH, deselects the device and the SO output pin is at

a high impedance state. Unless a nonvolatile write cycle is underway, the de-
vice will be in the standby power mode. CS LOW enables the device, placing it
in the active power mode. Prior to the start of any operation after power-up, a
HIGH to LOW transition on CS is required.
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the watchdog
timer. The absence of a HIGH to LOW transition within the watchdog time out
period results in RESET/RESET going active.

Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out
on this pin. The falling edge of the serial clock (SCK) clocks the data out.

Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin. The rising edge of the serial clock (SCK) latches the input
data. Send all opcodes (Table 1), addresses and data MSB first.

SCK

Serial Clock. The serial clock controls the serial bus timing for data input and out-
put. The rising edge of SCK latches in the opcode, address, or data bits present on
the SI pin. The falling edge of SCK changes the data output on the SO pin.

Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to
"lock" the setting of the watchdog timer control and the memory write protect bits.

Ground

12 & 13

Supply Voltage

RESET/

RESET

Reset Output.

RESET/RESET is an active LOW/HIGH, open drain output

which goes active whenever V

falls below the minimum V

sense level. It

will remain active until V

rises above the minimum V

sense level for

200ms. RESET/RESET goes active if the watchdog timer is enabled and CS
remains either HIGH or LOW longer than the selectable watchdog time out pe-
riod. A falling edge of CS will reset the watchdog timer. RESET/RESET goes
active on power-up at about 1V and remains active for 200ms after the power
supply stabilizes.

1, 7, 8,

1, 4-6,

9-12,

15-17, 20

No internal connections

X5643, X5645

FN8135.1

July 18, 2005

PRINCIPLES OF OPERATION

Power-on Reset

Application of power to the X5643/X5645 activates a
power-on reset circuit. This circuit goes active at about
1V and pulls the RESET/RESET pin active. This signal
prevents the system microprocessor from starting to
operate with insufficient voltage or prior to stabilization
of the oscillator. When V

exceeds the device V

TRIP

value for 200ms (nominal) the circuit releases
RESET/RESET, allowing the processor to begin execut-
ing code.

Low Voltage Monitoring

During operation, the X5643/X5645 monitors the V

level and asserts RESET/RESET if supply voltage falls
below a preset minimum V

TRIP

. The RESET/RESET

signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET
signal remains active until the voltage drops below 1V.
It also remains active until V

returns and exceeds

TRIP

for 200ms.

Watchdog Timer

The watchdog timer circuit monitors the microprocessor
activity by monitoring the WDI input. The microproces-
sor must toggle the CS/WDI pin periodically to prevent a
RESET/RESET signal. The CS/WDI pin must be toggled
from HIGH to LOW prior to the expiration of the watch-
dog time out period. The state of two nonvolatile con-
trol bits in the status register determine the watchdog
timer period. The microprocessor can change these
watchdog bits, or they may be "locked" by tying the WP
pin LOW and setting the WPEN bit HIGH.

Threshold Reset Procedure

The X5643/X5645 has a standard V

threshold

TRIP

) voltage. This value will not change over normal

operating and storage conditions. However, in applica-
tions where the standard V

TRIP

is not exactly right, or

for higher precision in the V

TRIP

value, the

X5643/X5645 threshold may be adjusted.

Setting the V

TRIP

Voltage

This procedure sets the V

TRIP

to a higher voltage

value. For example, if the current V

TRIP

is 4.4V and the

new V

TRIP

is 4.6V, this procedure directly makes the

change. If the new setting is lower than the current set-
ting, then it is necessary to reset the trip point before
setting the new value.

To set the new V

TRIP

voltage, apply the desired V

TRIP

threshold to the Vcc pin and tie the CS/WDI pin and
the WP pin HIGH. RESET/RESET and SO pins are
left unconnected. Then apply the programming voltage
V

to both SCK and SI and pulse CS/WDI LOW then

HIGH. Remove V

and the sequence is complete.

Figure 1. Set V

TRIP

Voltage

Resetting the V

TRIP

Voltage

This procedure sets the V

TRIP

to a "native" voltage

level. For example, if the current V

TRIP

is 4.4V and the

TRIP

is reset, the new V

TRIP

is something less than

1.7V. This procedure must be used to set the voltage
to a lower value.

To reset the V

TRIP

voltage, apply a voltage between 2.7

and 5.5V to the V

pin. Tie the CS/WDI pin, the WP pin,

and the SCK pin HIGH. RESET/RESET and SO pins are
left unconnected. Then apply the programming voltage
V

to the SI pin ONLY and pulse CS/WDI LOW then

HIGH. Remove V

and the sequence is complete.

Figure 2. Reset V

TRIP

Voltage

SCK

X5643, X5645

FN8135.1

July 18, 2005

Figure 4. Sample V

TRIP

Reset Circuit

SPI SERIAL MEMORY

The memory portion of the device is a CMOS serial
EEPROM array with Intersil's block lock protection.
The array is internally organized as x 8. The device
features a Serial Peripheral Interface (SPI) and soft-
ware protocol allowing operation on a simple four-wire
bus.

The device utilizes Intersil's proprietary Direct Write

cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.

The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input,
with data being clocked in on the rising edge of SCK.
CS must be LOW during the entire operation.

All instructions (Table 1), addresses and data are trans-
ferred MSB first. Data input on the SI line is latched on
the first rising edge of SCK after CS goes LOW. Data is
output on the SO line by the falling edge of SCK. SCK is
static, allowing the user to stop the clock and then start
it again to resume operations where left off.

Write Enable Latch

The device contains a write enable latch. This latch
must be SET before a write operation is initiated. The
WREN instruction will set the latch and the WRDI
instruction will reset the latch (Figure 3). This latch is
automatically reset upon a power-up condition and
after the completion of a valid Write Cycle.

Status Register

The RDSR instruction provides access to the status regis-
ter. The status register may be read at any time, even dur-
ing a write cycle. The status register is formatted as
follows:

The Write-In-Progress (WIP) bit is a volatile, read only
bit and indicates whether the device is busy with an
internal nonvolatile write operation. The WIP bit is read
using the RDSR instruction. When set to a "1", a non-
volatile write operation is in progress. When set to a
"0", no write is in progress.

Table 1. Instruction Set

Note:

*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.

X5643/45

2
3

7
6

TRIP

Adj.

Program

Reset V

TRIP

Test

TRIP

Set V

TRIP

RESET

4.7K

10K

WPEN

FLB

WD1

WD0

BL1

BL0

WEL

WIP

Instruction Name

Instruction Format*

Operation

WREN

0000 0110

Set the write enable latch (enable write operations)

SFLB

0000 0000

Set flag bit

WRDI/RFLB

0000 0100

Reset the write enable latch/reset flag bit

RSDR

0000 0101

Read status register

WRSR

0000 0001

Write status register (watchdog, block lock, WPEN & flag bits)

READ

0000 0011

Read data from memory array beginning at selected address

WRITE

0000 0010

Write data to memory array beginning at selected address

X5643, X5645

FN8135.1

July 18, 2005

Table 2. Block Protect Matrix

The Write Enable Latch (WEL) bit indicates the sta-
tus of the write enable latch. When WEL = 1, the
latch is set HIGH and when WEL = 0 the latch is reset
LOW. The WEL bit is a volatile, read only bit. It can
be set by the WREN instruction and can be reset by
the WRDS instruction.

The block lock bits, BL0 and BL1, set the level of block
lock protection. These nonvolatile bits are pro-
grammed using the WRSR instruction and allow the
user to protect one quarter, one half, all or none of the
EEPROM array. Any portion of the array that is block
lock protected can be read but not written. It will
remain protected until the BL bits are altered to disable
block lock protection of that portion of memory.

The watchdog timer bits, WD0 and WD1, select the
watchdog time out period. These nonvolatile bits are
programmed with the WRSR instruction.

The FLAG bit shows the status of a volatile latch that
can be set and reset by the system using the SFLB
and RFLB instructions. The flag bit is automatically
reset upon power-up. This flag can be used by the sys-
tem to determine whether a reset occurs as a result of
a watchdog time out or power failure.

The nonvolatile WPEN bit is programmed using the
WRSR instruction. This bit works in conjunction with the
WP pin to provide an in-circuit programmable ROM func-
tion (Table 2). WP is LOW and WPEN bit programmed
HIGH disables all status register write operations.

In Circuit Programmable ROM Mode

This mechanism protects the block lock and watchdog
bits from inadvertent corruption.

In the locked state (

programmable ROM mode) the WP pin

is LOW and the nonvolatile bit WPEN is "1". This mode
disables nonvolatile writes to the device's status register.

WREN CMD

Status Register

Device Pin

Block

Status Register

WEL

WPEN

WP#

Protected Block

Unprotected Block

WPEN, BL0, BL1

WD0, WD1

Protected

Writable

Protected

Writable

Protected

Writable

Status

Register Bits

Array Addresses Protected

BL1

BL0

X5643/X5645

None

$1800-$1FFF

$1000-$1FFF

$0000-$1FFF

Status Register Bits

Watchdog Time Out

(Typical)

WD1

WD0

1.4 seconds

600 milliseconds

200 milliseconds

disabled

X5643, X5645

FN8135.1

July 18, 2005

Figure 5. Read EEPROM Array Sequence

Setting the WP pin LOW while WPEN is a "1" while an
internal write cycle to the status register is in progress
will not stop this write operation, but the operation dis-
ables subsequent write attempts to the status register.

When WP is HIGH, all functions, including nonvolatile
writes to the status register operate normally. Setting
the WPEN bit in the status register to "0" blocks the
WP pin function, allowing writes to the status register
when WP is HIGH or LOW. Setting the WPEN bit to "1"
while the WP pin is LOW activates the programmable
ROM mode, thus requiring a change in the WP pin
prior to subsequent status register changes. This
allows manufacturing to install the device in a system
with WP pin grounded and still be able to program the
status register. Manufacturing can then load configura-
tion data, manufacturing time and other parameters
into the EEPROM, then set the portion of memory to
be protected by setting the block lock bits, and finally
set the "OTP mode" by setting the WPEN bit. Data
changes now require a hardware change.

Read Sequence

When reading from the EEPROM memory array, CS is
first pulled low to select the device. The 8-bit READ
instruction is transmitted to the device, followed by the 16-
bit address. After the READ opcode and address are sent,
the data stored in the memory at the selected address is
shifted out on the SO line. The data stored in memory at
the next address can be read sequentially by continuing to
provide clock pulses. The address is automatically incre-
mented to the next higher address after each byte of data
is shifted out. When the highest address is reached, the
address counter rolls over to address $0000 allowing the
read cycle to be continued indefinitely. The read opera-
tion is terminated by taking CS high. Refer to the read
EEPROM array sequence (Figure 1).

To read the status register, the CS line is first pulled low
to select the device followed by the 8-bit RDSR instruc-
tion. After the RDSR opcode is sent, the contents of the
status register are shifted out on the SO line. Refer to
the read status register sequence (Figure 2).

Write Sequence

Prior to any attempt to write data into the device, the
"Write Enable" Latch (WEL) must first be set by issuing
the WREN instruction (Figure 3). CS is first taken LOW,
then the WREN instruction is clocked into the device.
After all eight bits of the instruction are transmitted, CS
must then be taken HIGH. If the user continues the
write operation without taking CS HIGH after issuing the
WREN instruction, the write operation will be ignored.

To write data to the EEPROM memory array, the user
then issues the WRITE instruction followed by the 16
bit address and then the data to be written. Any
unused address bits are specified to be "0's". The
WRITE operation minimally takes 32 clocks. CS must
go low and remain low for the duration of the opera-
tion. If the address counter reaches the end of a page
and the clock continues, the counter will roll back to
the first address of the page and overwrite any data
that may have been previously written.

For the page write operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of
the last data byte to be written is clocked in. If it is
brought HIGH at any other time, the write operation
will not be completed (Figure 4).

To write to the status register, the WRSR instruction is
followed by the data to be written (Figure 5). Data bits
0 and 1 must be "0".

20 21 22 23 24 25

26 27 28 29 30

Data Out

SCK

MSB

High Impedance

Instruction

16 Bit Address

15 14 13

X5643, X5645

FN8135.1

July 18, 2005

While the write is in progress following a status register or
EEPROM sequence, the status register may be read to
check the WIP bit. During this time the WIP bit will be high.

OPERATIONAL NOTES

The device powers-up in the following state:

The device is in the low power standby state.

A HIGH to LOW transition on CS is required to enter

an active state and receive an instruction.

SO pin is high impedance.

The write enable latch is reset.

The flag bit is reset.

Reset signal is active for t

PURST

Data Protection

The following circuitry has been included to prevent
inadvertent writes:

A WREN instruction must be issued to set the write

enable latch.

CS must come HIGH at the proper clock count in

order to start a nonvolatile write cycle.

Figure 6. Read Status Register Sequence

Figure 7. Write Enable Latch Sequence

11 12 13 14

Data Out

SCK

MSB

High Impedance

Instruction

SCK

High Impedance

X5643, X5645

FN8135.1

July 18, 2005

Figure 8. Write Sequence

Figure 9. Status Register Write Sequence

SYMBOL TABLE

32 33 34 35 36 37 38 39

SCK

Instruction

16 Bit Address

Data Byte 1

40 41 42 43 44 45 46 47

Data Byte 2

Data Byte 3

Data Byte N

15 14 13

20 21 22 23 24 25 26 27 28 29 30 31

SCK

High Impedance

Instruction

Data Byte

11 12 13 14 15

WAVEFORM

INPUTS

OUTPUTS

Must be
steady

Will be
steady

May change
from LOW
to HIGH

Will change
from LOW
to HIGH

May change
from HIGH
to LOW

Will change
from HIGH
to LOW

Don't Care:
Changes
Allowed

Changing:
State Not
Known

N/A

Center Line
is High
Impedance

X5643, X5645

FN8135.1

July 18, 2005

ABSOLUTE MAXIMUM RATINGS

Temperature under bias .................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on any pin with respect to V

.... -1.0V to +7V

D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds) ........ 300°C

COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; the functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Symbol

Parameter

Limits

Unit

Test Conditions

Min.

Typ.

Max.

CC1

write current (active)

SCK = V

x 0.1/V

x 0.9 @ 2MHz,

SO = Open

CC2

read current (active)

0.4

SCK = V

x 0.1/V

x 0.9 @ 2MHz,

SO = Open

SB1

standby current

WDT=OFF

µA

CS = V

, V

= V

or V

= 5.5V

SB2

standby current

WDT=ON

µA

CS = V

, V

= V

or V

= 5.5V

SB3

standby current

WDT=ON

µA

CS = V

, V

= V

or V

= 3.6V

Input leakage current

0.1

µA

= V

to V

Output leakage current

0.1

µA

OUT

= V

to V

(1)

Input LOW voltage

-0.5

x 0.3

(1)

Input HIGH voltage

x 0.7

+ 0.5

OL1

Output LOW voltage

0.4

> 3.3V, I

= 2.1mA

OL2

Output LOW voltage

0.4

2V < V

3.3V, I

= 1mA

OL3

Output LOW voltage

0.4

2V, I

= 0.5mA

OH1

Output HIGH voltage

- 0.8

> 3.3V, I

= -1.0mA

OH2

Output HIGH voltage

- 0.4

2V < V

3.3V, I

= -0.4mA

OH3

Output HIGH voltage

- 0.2

2V, I

= -0.25mA

OLS

Reset output LOW voltage

0.4

= 1mA

RECOMMENDED OPERATING CONDITIONS

Temperature

Min.

Max.

Commercial

0°C

70°C

Industrial

-40°C

+85°C

Device Option

Supply Voltage

-2.7 or -2.7A

2.7V to 5.5V

Blank or -4.5A

4.5V-5.5V

X5643, X5645

FN8135.1

July 18, 2005

CAPACITANCE T

= +25°C, f = 1MHz, V

= 5V

Notes: (1) V

min. and V

max. are for reference only and are not tested.

(2) This parameter is periodically sampled and not 100% tested.

EQUIVALENT A.C. LOAD CIRCUIT AT 5V V

A.C. TEST CONDITIONS

A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)

Serial Input Timing

Symbol

Test

Max.

Unit

Conditions

OUT

(2)

Output Capacitance (SO, RESET/RESET)

OUT

= 0V

(2)

Input Capacitance (SCK, SI, CS, WP)

= 0V

Output

100pF

4.6k

RESET/RESET

30pF

2.06k

3.03k

Input pulse levels

x 0.1 to V

x 0.9

Input rise and fall times

10ns

Input and output timing level

x0.5

Symbol

Parameter

2.7-5.5V

Unit

Min.

Max.

SCK

Clock frequency

MHz

CYC

Cycle time

500

LEAD

CS lead time

250

LAG

CS lag time

250

Clock HIGH time

200

Clock LOW time

250

Data setup time

Data hold time

(3)

Input rise time

100

(3)

Input fall time

100

CS deselect time

500

(4)

Write cycle time

X5643, X5645

FN8135.1

July 18, 2005

Serial Input Timing

Serial Output Timing

Notes: (3) This parameter is periodically sampled and not 100% tested.

(4) t

is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile

write cycle.

Serial Output Timing

Symbol

Parameter

2.7-5.5V

Unit

Min. Max.

SCK

Clock frequency

MHz

DIS

Output disable time

250

Output valid from clock low

250

Output hold time

(3)

Output rise time

100

(3)

Output fall time

100

SCK

MSB IN

LAG

LEAD

LSB IN

High Impedance

SCK

MSB Out

MSB1 Out

LSB Out

ADDR

LSB IN

CYC

DIS

LAG

X5643, X5645

FN8135.1

July 18, 2005

Power-Up and Power-Down Timing

RESET Output Timing

Note:

(5) This parameter is periodically sampled and not 100% tested.

CS/WDI vs. RESET/RESET Timing

Symbol

Parameter

Min.

Typ.

Max.

Unit

TRIP

Reset trip point voltage, X5643-4.5A, X5643-4.5A
Reset trip point voltage, X5643, X5645
Reset trip point voltage, X5643-2.7A, X5645-2.7A
Reset trip point voltage, X5643-2.7, X5645-2.7

4.5

4.25
2.85
2.55

4.63
4.38
2.93
2.63

4.75

4.5
3.0
2.7

TRIP

hysteresis (HIGH to LOW vs. LOW to HIGH V

TRIP

voltage)

PURST

Power-up reset time out

100

200

280

RPD

(5)

detect to reset/output

500

(5)

fall time

100

µs

(5)

rise time

100

µs

RVALID

Reset valid V

RESET (X5643)

RESET (X5645)

PURST

RPD

0 Volts

TRIP

CS/WDI

CST

RESET

WDO

RST

RESET

WDO

RST

X5643, X5645

FN8135.1

July 18, 2005

TRIP

Programming Specifications V

= 1.7-5.5V; Temperature = 0°C to 70°C

Parameter

Description

Min.

Max.

Unit

VPS

SCK V

TRIP

program voltage setup time

µs

VPH

SCK V

TRIP

program voltage hold time

µs

TRIP

program pulse width

µs

TSU

TRIP

level setup time

µs

THD

TRIP

level hold (stable) time

TRIP

write cycle time

TRIP

program cycle recovery period (between successive programming cycles)

VPO

SCK V

TRIP

program voltage off time before next cycle

Programming voltage

TRAN

TRIP

programed voltage range

1.7

5.0

ta1

Initial V

TRIP

program voltage accuracy (V

applied-V

TRIP

) (programmed at 25°C)

-0.1

+0.4

ta2

Subsequent V

TRIP

Program Voltage accuracy [(V

applied-V

ta1

)-V

TRIP

]

(programmed at 25°C)

-25

+25

TRIP

Program Voltage repeatability (successive program operations)

(programmed at 25°C)

-25

+25

TRIP

program variation after programming (0-75°C). (programmed at 25°C)

-25

+25

TRIP

programming parameters are periodically sampled and are not 100% tested.

X5643, X5645

FN8135.1

July 18, 2005

TYPICAL PERFORMANCE

Watchdog Timer On (V

= 5V)

Watchdog Timer On (V

= 5V)

Watchdog Timer Off (V

= 3V, 5V)

-40

Temp (°C)

Isb

(µ

Supply Current vs. Temperature (I

)

WDO

vs. Voltage/Temperature (WD1, 0 = 1, 1)

TRIP

vs. Temperature (programmed at 25°C)

WDO

vs. Voltage/Temperature (WD1, 0 = 1, 0)

PURST

vs. Temperature

WDO

vs. Voltage/Temperature (WD1, 0 0 = 0, 1)

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.7

2.4

3.1

3.8

4.5

5.2

90°C

25°C

-40°C

Reset (seco

nds

)

Voltage

5.025

5.000

4.975

3.525

3.500

3.475

2.525

2.500

2.475

Voltage

Temperature

TRIP

= 5V

TRIP

= 3.5V

TRIP

= 2.5V

0.8

0.75

0.7

0.65

0.6

0.55

0.5

0.45

1.7

5.2

Reset (seconds)

Voltage

2.4

3.1

3.8

4.5

90°C

25°C

-40°C

200

195

190

185

180

175

170

165

160

-40

Degrees °C

205

Tim

90°C

25°C

-40°C

200

195

190

185

180

175

170

165

160

205

eset (secon

Voltage

1.7

5.2

2.4

3.1

3.8

4.5

X5643, X5645

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8135.1

July 18, 2005

Ordering Information

Part Mark Information

Range

TRIP

Range

Package

Operating

Temperature Range

Part Number

RESET (Active LOW)

Part Number

RESET (Active HIGH)

4.5-5.5V

4.5.4.75

8 pin PDIP

0-70°C

X5643P-4.5A

X5645P-4.5A

14L SOIC

0-70°C

X5643S14-4.5A

X5645S14-4.5A

-40-85°C

X5643S14I-4.5A

X5645S14I-4.5A

4.5-5.5V

4.25.4.5

8 pin PDIP

0-70°C

X5643P

X5645P

14L SOIC

0-70°C

X5643S14

X5645S14

-40-85°C

X5643S14I

X5645S14I

2.7-5.5V

2.85-3.0

14L SOIC

0-70°C

X5643S14-2.7A

X5645S14-2.7A

2.7-5.5V

2.55-2.7

14L SOIC

0-70°C

X5643S14-2.7

X5645S14-2.7

P = 8-Lead PDIP
S14 = 14 Lead SOIC

Blank = 5V ±10%, 0°C to +70°C, V

TRIP

= 4.25-4.5

AL = 5V±10%, 0°C to +70°C, V

TRIP

= 4.5-4.75

I = 5V ±10%, -40°C to +85°C, V

TRIP

= 4.25-4.5

AM = 5V ±10%, -40°C to +85°C, V

TRIP

= 4.5-4.75

F = 2.7V to 5.5V, 0°C to +70°C, V

TRIP

= 2.55-2.7

AN = 2.7V to 5.5V, 0°C to +70°C, V

TRIP

= 2.85-3.0

G = 2.7V to 5.5V, -40°C to +85°C, V

TRIP

= 2.55-2.7

AP = 2.7V to 5.5V, -40°C to +85°C, V

TRIP

= 2.85-3.0

X5643/45

X5643, X5645

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X5645S14

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X5645S14