1
FN8158.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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XDCP is a trademark of Intersil Americas INC. Copyright Intersil Americas Inc. 2005. All Rights Reserved
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X9110
Dual Supply/Low Power/1024-Tap/SPI Bus
Single Digitally-Controlled (XDCPTM)
Potentiometer
The X9110 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS integrated
circuit.
The digital controlled potentiometer is implemented using
1023 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the SPI bus interface. The
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and four non-volatile Data Registers that
can be directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the resistor
array though the switches. Power-up recalls the contents of
the default data register (DR0) to the WCR.
The XDCP can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Features
1024 Resistor Taps 10-Bit Resolution
SPI Serial Interface for write, read, and transfer operations
of the potentiometer
Wiper Resistance, 40
Typical @ 5V
Four Non-Volatile Data Registers
Non-Volatile Storage of Multiple Wiper Positions
Power-on Recall. Loads Saved Wiper Position on Power-up
Standby Current < 3A Max
System V
CC
: 2.7V to 5.5V Operation
Analog V+/V-: -5V to +5V
100k
End to End Resistance
100 yr. Data Retention
Endurance: 100, 000 Data Changes Per Bit Per Register
14 Ld TSSOP
Dual Supply Version of the X9111
Low Power CMOS
Pb-Free Plus Anneal Available (RoHS Compliant)
Pinout
X9110
14 LD TSSOP
TOP VIEW
Functional Diagram
V
CC
R
L
VSS
1
2
3
4
5
6
7
8
14
13
12
11
10
9
A0
R
W
SCK
CS
R
H
S0
V+
SI
HOLD
WP
V-
R
H
R
L
BUS
R
W
INTERFACE &
CONTROL
POT
V
CC
V
SS
SPI
BUS
ADDRESS
DATA
STATUS
WRITE
READ
WIPER
1024-TAPS
TRANSFER
NC
NC
100k
POWER-ON RECALL
WIPER COUNTER
REGISTER (WCR)
DATA REGISTERS
(DR0-DR3)
CONTROL
INTERFACE
V+
V-
Data Sheet
October 7, 2005
2
FN8158.2
October 7, 2005
Detailed Functional Diagram
Ordering Information
PART NUMBER
PART MARKING
VCC LIMITS (V)
POTENTIOMETER
RANGE (k
)
TEMP RANGE (C)
PACKAGE
X9110TV14
X9110TV
5 10
100
0 to 70
14 Ld TSSOP
X9110TV14Z (Note)
X9110TV Z
0 to 70
14 Ld TSSOP (Pb-free)
X9110TV14I
X9110TV I
-40 to 85
14 Ld TSSOP
X9110TV14IZ (Note)
X9110TV Z I
-40 to 85
14 Ld TSSOP (Pb-free)
X9110TV14-2.7
X9110TV F
2.7 to 5.5
0 to 70
14 Ld TSSOP
X9110TV14Z-2.7 (Note)
X9110TV Z F
0 to 70
14 Ld TSSOP (Pb-free)
X9110TV14I-2.7
X9110TV G
-40 to 85
14 Ld TSSOP
X9110TV14IZ-2.7 (Note)
X9110TV Z G
-40 to 85
14 Ld TSSOP (Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
CS
SCK
A0
SO
SI
HOLD
WP
INTERFACE
AND
CONTROL
CIRCUITRY
V-
V+
V
CC
V
SS
DR0
DR1
DR2
DR3
WIPER
COUNTER
REGISTER
(WCR)
R
H
R
L
DATA
R
W
1024-TAPS
100k
CONTROL
POWER ON
RECALL
X9110
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FN8158.2
October 7, 2005
Circuit Level Applications
Vary the gain of a voltage amplifier
Provide programmable dc reference voltages for
comparators and detectors
Control the volume in audio circuits
Trim out the offset voltage error in a voltage amplifier
circuit
Set the output voltage of a voltage regulator
Trim the resistance in Wheatstone bridge circuits
Control the gain, characteristic frequency and Q-factor in
filter circuits
Set the scale factor and zero point in sensor signal
conditioning circuits
Vary the frequency and duty cycle of timer ICs
Vary the dc biasing of a pin diode attenuator in RF circuits
Provide a control variable (I, V, or R) in feedback circuits
System Level Applications
Adjust the contrast in LCD displays
Control the power level of LED transmitters in
communication systems
Set and regulate the DC biasing point in an RF power
amplifier in wireless systems
Control the gain in audio and home entertainment systems
Provide the variable DC bias for tuners in RF wireless
systems
Set the operating points in temperature control systems
Control the operating point for sensors in industrial
systems
Trim offset and gain errors in artificial intelligent systems
Bus Interface Pins
SERIAL OUTPUT (SO)
SO is a serial data output pin. During a read cycle, data is
shifted out on this pin. Data is clocked out on the falling edge
of the serial clock.
SERIAL INPUT (SI)
SI is the serial data input pin. All opcodes, byte addresses
and data to be written to the pots and pot registers are input
on this pin. Data is latched by the rising edge of the serial
clock.
SERIAL CLOCK (SCK)
The SCK input is used to clock data into and out of the
X9110.
HOLD (HOLD)
HOLD is used in conjunction with the CS pin to select the
device. Once the part is selected and a serial sequence is
underway, HOLD may be used to pause the serial
communication with the controller without resetting the serial
sequence. To pause, HOLD must be brought LOW while SCK is
LOW. To resume communication, HOLD is brought HIGH, again
while SCK is LOW. If the pause feature is not used, HOLD should
be held HIGH at all times.
DEVICE ADDRESS (A0)
The address input is used to set the 8-bit slave address. A
match in the slave address serial data stream A0 must be
made with the address input (A0) in order to initiate
communication with the X9110.
CHIP SELECT (CS)
When CS is HIGH, the X9110 is deselected and the SO pin
is at high impedance, and (unless an internal write cycle is
underway) the device will be in the standby state. CS LOW
enables the X9110, placing it in the active power mode. It
should be noted that after a power-up, a HIGH to LOW
transition on CS is required prior to the start of any
operation.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when LOW prevents nonvolatile writes to the
Data Registers.
Pin Descriptions
PIN
(TSSOP) SYMBOL
FUNCTION
1
V+
Analog Supply Voltage
2
SO
Serial Data Output
3
A0
Device Address
4
SCK
Serial Clock
5
WP
Hardware Write Protect
6
SI
Serial Data Input
7
V
SS
System Ground
8
V
-
Analog Supply Voltage
9
CS
Chip Select
10
HOLD
Device Select. Pause the Serial Bus
11
R
W
Wiper Terminal of the Potentiometer
12
R
H
High Terminal of the Potentiometer
13
R
L
Low Terminal of the Potentiometer
14
V
CC
System Supply Voltage
Pin Descriptions
PIN
(TSSOP) SYMBOL
FUNCTION
X9110
4
FN8158.2
October 7, 2005
Potentiometer Pins
R
H
, R
L
The R
H
and R
L
pins are equivalent to the terminal
connections on a mechanical potentiometer.
R
W
The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer.
Bias Supply Pins
SYSTEM SUPPLY VOLTAGE (V
CC
) AND SUPPLY
GROUND (V
SS
)
The V
CC
pin is the system supply voltage. The V
SS
pin is
the system ground.
ANALOG SUPPLY VOLTAGES (V+ AND V
-
)
These supplies are the analog voltage supplies for the
potentiometer. The V+ supply is tied to the wiper switches
while the V- supply is used to bias the switches and the
internal P+ substrate of the integrated circuit. Both of these
supplies set the voltage limits of the potentiometer.
Principles Of Operation
Device Description
SERIAL INTERFACE
The X9110 supports the SPI interface hardware conventions.
The device is accessed via the SI input with data clocked-in
on the rising SCK. CS must be LOW and the HOLD and WP
pins must be HIGH during the entire operation.
The SO and SI pins can be connected together, since they
have three state outputs. This can help to reduce system pin
count.
ARRAY DESCRIPTION
The X9110 is comprised of a resistor array (Figure 1). The
array contains the equivalent of 1023 discrete resistive
segments that are connected in series. The physical ends of
each array are equivalent to the fixed terminals of a
mechanical potentiometer (R
H
and R
L
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper (R
W
)
output. Within the individual array only one switch may be
turned on at a time.
These switches are controlled by a Wiper Counter Register
(WCR). The 10-bits of the WCR (WCR[9:0]) are decoded to
select, and enable, one of 1024 switches.
WIPER COUNTER REGISTER (WCR)
The X9110 contains a Wiper Counter Register (See Table 1)
for the XDCP potentiometer. The WCR is equivalent to a
serial-in, parallel-out register/counter with its outputs
decoded to select one of 1024 switches along its resistor
array. The contents of the WCR can be altered in one of
three ways: (1) it may be written directly by the host via the
write Wiper Counter Register instruction (serial load); (2) it
Serial Data Path
From Interface
Register 0
Serial
Bus
Input
Parallel
Bus
Input
Counter
Register
RH
RL
RW
10
10
C
O
U
N
T
E
R
D
E
C
O
D
E
If WCR = 000[HEX] then R
W
= R
L
If WCR = 3FF[HEX] then R
W
= R
H
Wiper
(WCR)
(DR0)
Circuitry
Register 1
(DR1)
Register 2
(DR2)
Register 3
(DR3)
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
X9110
5
FN8158.2
October 7, 2005
may be written indirectly by transferring the contents of one
of four associated Data Registers via the XFR Data Register;
(3) it is loaded with the contents of its data register zero
(DR0) upon power-up.
The Wiper Counter Register is a volatile register; that is, its
contents are lost when the X9110 is powered-down. Although
the register is automatically loaded with the value in DR0 upon
power-up, this may be different from the value present at
power-down. Power-up guidelines are recommended to ensure
proper loadings of the DR0 value into the WCR.
DATA REGISTERS (DR)
The potentiometer has four 10-bit non-volatile Data
Registers. These can be read or written directly by the host.
Data can also be transferred between any of the four Data
Registers and the Wiper Counter Register. All operations
changing data in one of the Data Registers is a nonvolatile
operation and will take a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as regular memory locations for system parameters or
user preference data.
DR[9:0] is used to store one of the 1024 wiper position (0
~1023). Table 2.
STATUS REGISTER (SR)
This 1-bit status register is used to store the system status
(see Table 3).
WIP: Write In Progress status bit, read only.
When WIP=1, indicates that high-voltage write cycle is in
progress.
When WIP=0, indicates that no high-voltage write cycle is
in progress.
TABLE 3. STATUS REGISTER, SR (1-BIT)
TABLE 1. WIPER CONTROL REGISTER, WCR (10-BIT), WCR9WCR0: Used To Store The Current Wiper Position (Volatile, V)
WCR9
WCR8
WCR7
WCR6
WCR5
WCR4
WCR3
WCR2
WCR1
WCR0
V
V
V
V
V
V
V
V
V
V
(MSB)
(LSB)
TABLE 2. DATA REGISTER, DR (10-BIT), BIT 9BIT 0: Used to store wiper positions or data (Non-Volatile, NV)
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
MSB
LSB
WIP
(LSB)
X9110
6
FN8158.2
October 7, 2005
TABLE 4. IDENTIFICATION BYTE FORMAT
TABLE 5. INSTRUCTION BYTE FORMAT
Device Instructions
Identification Byte (ID and A)
The first byte sent to the X9110 from the host, following a CS
going HIGH to LOW, is called the Identification Byte. The
most significant four bits of the slave address are a device
type identifier. The ID[3:0] bits is the device ID for the X9110;
this is fixed as 0101[B] (refer to Table 4).
The A0 bit in the ID byte is the internal slave address. The
physical device address is defined by the state of the A0 input
pin. The slave address is externally specified by the user. The
X9110 compares the serial data stream with the address input
state; a successful compare of the address bit is required for
the X9110 to successfully continue the command sequence.
Only the device whose slave address matches the incoming
device address sent by the master executes the instruction.
The A0 input can be actively driven by CMOS input signals or
tied to V
CC
or V
SS
. The R/W bit is used to set the device to
either read or write mode.
Instruction Byte and Register Selection
The next byte sent to the X9110 contains the instruction and
register pointer information. The three most significant bits
are used provide the instruction opcode (I[2:0]). The RB and
RA bits point to one of the four registers. The format is
shown in Table 5.
Five of the seven instructions are four bytes in length. These
instructions are:
Read Wiper Counter Register read the current wiper
position of the selected pot,
Write Wiper Counter Register change current wiper
position of the selected pot,
Read Data Register read the contents of the selected
data register;
Write Data Register write a new value to the selected
data register.
Read Status This command returns the contents of the
WIP bit which indicates if the internal write cycle is in
progress.
The basic sequence of the four byte instructions is illustrated
in Figure 3. These four-byte instructions exchange data
between the WCR and one of the Data Registers. A transfer
from a Data Register to a WCR is essentially a write to a
static RAM, with the static RAM controlling the wiper
position. The response of the wiper to this action will be
delayed by t
WRL
. A transfer from the WCR (current wiper
position), to a Data Register is a write to nonvolatile memory
and takes a minimum of t
WR
to complete. The transfer can
occur between the potentiometer and one of its associated
registers. The Read Status Register instruction is the only
unique format (see Figure 4).
Two instructions require a two-byte sequence to complete
(See Figure 2). These instructions transfer data between the
host and the X9110; either between the host and one of the
Data Registers or directly between the host and the Wiper
Counter Register. These instructions are:
XFR Data Register to Wiper Counter Register This
transfers the contents of one specified Data Register to
the associated Wiper Counter Register.
XFR Wiper Counter Register to Data Register This
transfers the contents of the specified Wiper Counter
Register to the specified associated Data Register.
ID3
ID2
ID1
ID0
0
0
A0
R/W
0
1
0
1
(MSB)
(LSB)
Device Type
Identifier
Internal Slave
Address
Read or
Write Bit
I2
I1
I0
0
RB
RA
0
0
(MSB)
(LSB)
Instruction
Opcode
Register
Selection
RB
RA
Register
0
0
1
1
0
1
0
1
DR0
DR1
DR2
DR3
X9110
7
FN8158.2
October 7, 2005
See Instruction format for more details.
Write in Process (WIP bit)
The contents of the Data Registers are saved to nonvolatile
memory when the CS pin goes from LOW to HIGH after a
complete write sequence is received by the device. The
progress of this internal write operation can be monitored by
a Write In Process bit (WIP). The WIP bit is read with a Read
Status command (See Figure 4).
Power-up and Down Requirements
At all times, the V+ voltage must be greater than or equal to
the voltage at R
H
or R
L
, and the voltage at R
H
or R
L
must be
greater than or equal to the voltage at V-. During power-up
and power-down, V
CC
, V+, and V- must reach their final
values within 1msec of each other.
ID3 ID2 ID1 ID0
0
0
A0
I2
I1
I0
RB
RA
SCK
SI
CS
0
1
0
1
R/W
Device ID
Internal
Instruction
Opcode
Address
Register
0
0
0
0
Address
0
0
0
FIGURE 2. TWO-BYTE INSTRUCTION SEQUENCE
ID3 ID2 ID1 ID0 0
A0 R/W I2
0 0
SCK
SI
0
0
X X 0
0
X X X
W
C
R
9
W
C
R
8
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
CS
I1 I0 0 RB RA
0
1
0
1
0
X X
X
Device ID
Internal
Address
Instruction
Opcode
Register
Address
Wiper
Position
0
FIGURE 3. FOUR-BYTE INSTRUCTION SEQUENCE (WRITE OR READ FOR WCR OR DATA REGISTERS)
ID3 ID2 ID1 ID0 0
A0 R/W I2
0
0
SCK
SI
1
0
X X 0
0
X X X
WIP
CS
I1 I0
0 RB RA
0
1
0
1
0
X X
X
Device ID
Internal
Address
Instruction
Opcode
Register
Address
Status
Bit
X X
0 0
0 0 0 0 0
0
0
FIGURE 4. FOUR-BYTE INSTRUCTION SEQUENCE (READ STATUS REGISTERS)
X9110
8
FN8158.2
October 7, 2005
Instruction Format
TABLE 6. INSTRUCTION SET
INSTRUCTION
INSTRUCTION SET
OPERATION
R/W
I
2
I
1
I
0
0
RB
RA
0
0
Read Wiper Counter
Register
1
1
0
0
0
0
0
0
0
Read the contents of the Wiper Counter
Register
Write Wiper Counter
Register
0
1
0
1
0
0
0
0
0
Write new value to the Wiper Counter
Register
Read Data Register
1
1
0
1
0
1/0
1/0
0
0
Read the contents of the Data Register
pointed to RB-RA
Write Data Register
0
1
1
0
0
1/0
1/0
0
0
Write new value to the Data Register
pointed to RB-RA
XFR Data Register to
Wiper Counter Register
1
1
1
0
0
1/0
1/0
0
0
Transfer the contents of the Data Register
pointed to by RB-RA to the Wiper Counter
Register
XFR Wiper Counter
Register to Data Register
0
1
1
1
0
1/0
1/0
0
0
Transfer the contents of the Wiper Counter
Register to the Data Register pointed to by
RB-RA
Read Status (WIP bit)
1
0
1
0
0
0
0
0
1
Read the status of the internal write cycle,
by checking the WIP bit (read status
register).
NOTE: 1/0 = data is one or zero
Read Wiper Counter Register (WCR)
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
Register
Addresses
Wiper Position
(Sent by X9110 on SO)
Wiper Position
(sent by X9110 on SO)
CS
Rising
Edge
0 1 0 1 0 0 A0
R/
W
= 1
1 0 0 0 0 0 0 0 X X X X X X
W
C
R
9
W
C
R
8
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
Write Wiper Counter Register (WCR)
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
Register
Addresses
Wiper Position
(Sent by Master on SI)
Wiper Position
(Sent by Master on SI)
CS
Rising
Edge
0 1 0 1 0 0 A0
R/ W
= 0
1 0 1 0 0 0 0 0 X X X X X X
W
C
R
9
W
C
R
8
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
Read Data Register (DR)
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
Register
Addresses
Wiper Position
(Sent by X9110 on SO)
Wiper Position
(sent by X9110 on SO)
CS
Rising
Edge
0 1 0 1 0 0 A0
R/ W
= 1
1 0 1 0 RB RA 0 0 X X X X X X
W
C
R
9
W
C
R
8
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
X9110
9
FN8158.2
October 7, 2005
NOTES:
1. "A0": stands for the device address sent by the master.
2. WCRx refers to wiper position data in the Wiper Counter Register
3. "X": Don't Care.
Write Data Register (DR)
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
Register
Address
Wiper Position or Data
(Sent by Master on SI)
Wiper Position or Data
(Sent by Master on SI)
CS
Rising
Edge
HIGH-VO
L
T
A
GE
WRITE CYCLE
0 1 0 1 0 0 A0
R/
W
= 0
1 1 0 0 RB RA 0 0 X X X X X X
W
C
R
9
W
C
R
8
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
Transfer Data Register (DR) to Wiper Counter Register (WCR)
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
Register
Address
CS
Rising
Edge
0
1
0
1
0
0 A0
R/ W
= 1
1
1
0
0 RB RA 0
0
Transfer Wiper Counter Register (WCR) to Data Register (DR)
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
Register
Address
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
0
1
0
1
0
0 A0
R/
W
= 0
1
1
1
0
RB
RA
0
0
Read Status Register (SR)
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
Register
Addresses
Status Data
(Sent by Slave on SO)
Status Data
(Sent by Slave on SO)
CS
Rising
Edge
0
1
0
1
0
0 A0
R/ W
= 1
0
1
0 X 0
0
0
1 X X X X X X X X 0
0
0
0
0
0
0 WIP
X9110
10
FN8158.2
October 7, 2005
Absolute Maximum Ratings
Recommended Operating Conditions
Temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65C to +135C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C
Voltage on SCK any address input
with respect to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
Voltage on V+ (referenced to V
SS
) (Note 4) . . . . . . . . . . . . . . . .10V
Voltage on V- (referenced to V
SS
) (Note 4) . . . . . . . . . . . . . . . . -10V
(V+) - (V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
Any Voltage on R
H
/R
L
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V+
Any Voltage on R
L
/R
H
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-
Lead temperature (soldering, 10s). . . . . . . . . . . . . . . . . . . . . . 300
C
I
W
(10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA
Temperature Range
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C
Supply Voltage (V
CC
) Limits (Note 4)
X9110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
10%
X9110-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Analog Specifications
Over recommended industrial (2.7V) operation conditions unless otherwise stated.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
R
TOTAL
End to End Resistance
100
k
End to End Resistance Tolerance
20
%
Power Rating
25C, each pot
50
mW
I
W
Wiper Current
3
mA
R
W
Wiper Resistance
Wiper Current =
3mA, V
CC
= 3V
150
500
R
W
Wiper Resistance
I
W
=
3mA, V
CC
= 5V
100
Vv+
Voltage on V+ pin
X9110 (Note4)
+4.5
+5.5
V
X9110-2.7 (Note 4)
+2.7
+5.5
Vv-
Voltage on V- pin
X9110 (Note 4)
-5.5
-4.5
V
X9110-2.7 (Note4)
-5.5
-2.7
V
TERM
Voltage on any R
H
or R
L
Pin
V
SS
= 0V
V-
V+
V
Noise
Ref: 1V
-120
dBV
Resolution
0.1
%
Absolute Linearity (Note 1)
R
w(n)(actual)
R
w(n)(expected)
, where n = 8 to 1006
1
MI (Note 3)
R
w(n)(actual)
R
w(n)(expected)
(Note 5)
1.5
MI
(Note 3)
Relative Linearity (Note 2)
R
w(m + 1)
[R
w(m)
+ MI], where m = 8 to 1006
0.5
MI
(Note 3)
R
w(m + 1)
[R
w(m)
+ MI] (Note 5)
1
MI
(Note 3)
Temperature Coefficient of R
TOTAL
300
ppm/C
Ratiometric Temp. Coefficient
20
ppm/C
C
H
/C
L
/C
W
Potentiometer Capacitancies
See Macro model
10/10/25
pF
NOTES:
1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
2. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is
a measure of the error in step size.
3. MI = RTOT / 1023 or (R
H
R
L
) / 1023, single pot
4. V
CC
, V+, V- must reach their final values within 1 msec of each other.
5. n = 0, 1, 2, ...,1023; m =0, 1, 2, ..., 1022.
X9110
11
FN8158.2
October 7, 2005
D.C. Operating Specifications
Over the recommended operating conditions unless otherwise specified
.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
CC1
V
CC
supply current
(active)
f
SCK
= 2.5 MHz, SO = Open, V
CC
= 5.5V
Other Inputs = V
SS
400
A
I
CC2
V
CC
supply current
(nonvolatile write)
f
SCK
= 2.5MHz, SO = Open, V
CC
= 5.5V
Other Inputs = V
SS
1
5
mA
I
SB
V
CC
current (standby)
SCK = SI = V
SS
, Addr. = V
SS
,
CS = V
CC
= 5.5V
3
A
I
LI
Input leakage current
V
IN
= V
SS
to V
CC
10
A
I
LO
Output leakage current
V
OUT
= V
SS
to V
CC
10
A
V
IH
Input HIGH voltage
V
CC
x 0.7
V
CC
+ 1
V
V
IL
Input LOW voltage
-1
V
CC
x 0.3
V
V
OL
Output LOW voltage
I
OL
= 3mA
0.4
V
V
OH
Output HIGH voltage
I
OH
= -1mA, V
CC
+3V
V
CC
- 0.8
V
V
OH
Output HIGH voltage
I
OH
= -0.4mA, V
CC
+3V
V
CC
- 0.4
V
Endurance and Data Retention
PARAMETER
MIN
UNITS
Minimum Endurance
100,000
Data changes per bit per register
Data Retention
100
years
Capacitance
SYMBOL
TEST
TEST CONDITIONS
MAX
UNITS
C
IN/OUT
(Notes 4,6
)
Input/Output capacitance (SI)
V
OUT
= 0V
8
pF
C
OUT
(Note 6)
Output capacitance (SO)
V
OUT
= 0V
8
pF
C
IN
(Note 6)
Input capacitance (A0, CS, WP, HOLD, and SCK)
V
IN
= 0V
6
pF
Power-up Timing
SYMBOL
PARAMETER MIN
MAX
UNITS
t
r
V
CC
(Note 6)
V
CC
Power-up Rate
0.2
50
V/ms
t
PUR
(Note7)
Power-up to Initiation of read operation
1
ms
t
PUW
(Note 7)
Power-up to Initiation of write operation
50
ms
NOTES:
6. This parameter is not 100% tested
7. t
PUR
and t
PUW
are the delays required from the time the (last) power supply (V
CC
-) is stable until the specific instruction can be issued. These
parameters are not 100% tested.
8. ESD Rating on RH, RL, RW pins is 1.5kV (HBM, 1.0A leakage maximum), ESD rating on all other pins is 2.0kV.
A.C. Test Conditions
I
nput pulse levels
V
CC
x 0.1 to V
CC
x 0.9
Input rise and fall times
10ns
Input and output timing level
V
CC
x 0.5
X9110
12
FN8158.2
October 7, 2005
Equivalent A.C. Load Circuit
5V
1462
100pF
SO pin
R
H
10pF
C
L
C
L
R
W
R
TOTAL
C
W
25pF
10pF
R
L
SPICE Macromodel
2714
2.7V
1382
100pF
SO pin
1217
AC Timing
SYMBOL
PARAMETER
MIN
MAX
UNITS
f
SCK
SSI/SPI clock frequency
2.0
MHz
t
CYC
SSI/SPI clock cycle time
400
ns
t
WH
SSI/SPI clock high time
150
ns
t
WL
SSI/SPI clock low time
150
ns
t
LEAD
Lead time
150
ns
t
LAG
Lag time
150
ns
t
SU
SI, SCK, HOLD and CS input setup time
50
ns
t
H
SI, SCK, HOLD and CS input hold time
50
ns
t
RI
SI, SCK, HOLD and CS input rise time
50
ns
t
FI
SI, SCK, HOLD and CS input fall time
50
ns
t
DIS
SO output disable time
0
500
ns
t
V
SO output valid time
100
ns
t
HO
SO output hold time
0
ns
t
RO
SO output rise time
50
ns
t
FO
SO output fall time
50
ns
t
HOLD
HOLD time
400
ns
t
HSU
HOLD setup time
50
ns
t
HH
HOLD hold time
50
ns
t
HZ
HOLD low to output in high Z
100
ns
t
LZ
HOLD high to output in low Z
100
ns
T
I
Noise suppression time constant at
SI, SCK, HOLD and CS inputs
20
ns
t
CS
CS deselect time
100
ns
t
WPASU
WP, A0 setup time
0
ns
t
WPAH
WP, A0 hold time
0
ns
X9110
13
FN8158.2
October 7, 2005
Symbol Table
High-Voltage Write Cycle Timing
SYMBOL
PARAMETER
TYP.
MAX.
UNITS
t
WR
High-voltage write cycle time (store instructions)
5
10
ms
XDCP Timing
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
t
WRPO
Wiper response time after the third (last) power supply is stable
5
10
s
t
WRL
Wiper response time after instruction issued (all load instructions)
5
10
s
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don't Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
X9110
14
FN8158.2
October 7, 2005
Timing Diagrams
Input Timing
Output Timing
Hold Timing
...
CS
SCK
SI
SO
MSB
LSB
High Impedance
t
LEAD
t
H
t
SU
t
FI
t
CS
t
LAG
t
CYC
t
WL
...
t
RI
t
WH
...
CS
SCK
SO
SI
ADDR
MSB
LSB
t
DIS
t
HO
t
V
...
...
CS
SCK
SO
SI
HOLD
t
HSU
t
HH
t
LZ
t
HZ
t
HOLD
t
RO
t
FO
X9110
15
FN8158.2
October 7, 2005
XDCP Timing (For All Load Instructions)
Write Protect And Device Address Pins Timing
Applications information
Basic Configurations Of Electronic Potentiometers
...
CS
SCK
SI
MSB
LSB
R
W
t
WRL
...
SO
High Impedance
CS
WP
A0
A1
t
WPASU
t
WPAH
(Any Instruction)
V
R
RW
+V
R
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
X9110
16
FN8158.2
October 7, 2005
Application Circuits
Noninverting Amplifier
Voltage Regulator
Offset Voltage Adjustment
Comparator with Hysterisis
+
V
S
V
O
R
2
R
1
V
O
= (1+R
2
/R
1
)V
S
R
1
R
2
I
adj
V
O
(REG) = 1.25V (1+R
2
/R
1
)+I
adj
R
2
V
O
(REG)
V
IN
317
+
V
S
V
O
R
2
R
1
V
UL
= {R
1
/(R
1
+R
2
)} V
O
(max)
RL
L
= {R
1
/(R
1
+R
2
)} V
O
(min)
100k
10k
10k
10k
-12V
+12V
TL072
+
V
S
V
O
R
2
R
1
}
}
X9110
17
FN8158.2
October 7, 2005
Application Circuits
(continued)
Attenuator
Filter
Inverting Amplifier
Equivalent L-R Circuit
+
V
S
V
O
R
3
R
1
V
O
= G V
S
-1/2
G +1/2
G
O
= 1 + R
2
/R
1
fc = 1/(2
RC)
+
V
S
V
O
R
2
R
1
Z
IN
= R
2
+ s R
2
(R
1
+ R
3
) C
1
= R
2
+ s Leq
(R
1
+ R
3
) >> R
2
+
V
S
Function Generator
R
2
R
4
R
1
= R
2
= R
3
= R
4
= 10kW
+
V
S
R
2
R
1
R
C
}
}
V
O
= G V
S
G = - R
2
/R
1
R
2
C
1
R
1
R
3
Z
IN
+
R
2
+
R
1
}
}
R
A
R
B
frequency
R
1
, R
2
, C
amplitude
R
A
, R
B
C
V
O
X9110
18
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8158.2
October 7, 2005
Packaging Information
NOTE:
ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
14-Lead Plastic, TSSOP, Package Type V
See Detail "A"
.031 (.80)
.041 (1.05)
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.025 (.65) BSC
.193 (4.9)
.200 (5.1)
.002 (.05)
.006 (.15)
.047 (1.20)
.0075 (.19)
.0118 (.30)
0
8
.010 (.25)
.019 (.50)
.029 (.75)
Gage Plane
Seating Plane
Detail A (20X)
X9110
PDF 
ZIP