X9221A

64 Taps, 2-Wire Serial Bus

Dual Digitally Controlled Potentiometer

(XDCPTM)

FEATURES

· Two XDCPs in one package
· 2-wire serial interface
· Register oriented format, 8 registers total

--Directly write wiper position
--Read wiper position
--Store as many as four positions per pot

· Instruction format

--Quick transfer of register contents to resistor

array

· Direct write cell

--Endurance100,000 writes per bit per register

· Resistor array values

--2k

, 10k

, 50k

· Resolution: 64 taps each pot
· 20 Ld plastic DIP and 20-lead SOIC packages
· Pb-free plus anneal available (RoHS compliant)

DESCRIPTION

The X9221A integrates two digitally controlled potenti-
ometers (XDCP) on a monolithic CMOS integrated
microcircuit.

The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and 2 non-
volatile Data Registers (DR0:DR1) that can be directly
written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor
array through the switches. Power up recalls the con-
tents of DR0 to the WCR.

The XDCP can be used as a three-terminal potentiom-
eter or as a two-terminal variable resistor in a wide
variety of applications including control, parameter
adjustments, and signal processing.

BLOCK DIAGRAM

Wiper

Counter

(WCR)

Array

Pot 1

Wiper

Counter

(WCR)

Data

SCL
SDA

A0
A1
A2
A3

Interface

and

Control

Circuitry

Pot 0

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Data Sheet

FN8163.1

September 14, 2005

FN8163.1

September 14, 2005

Ordering Information

PART NUMBER

PART MARKING

LIMITS (V)

TOTAL

(K)

TEMP RANGE (°C)

PACKAGE

X9221AYP

5 ±10%

0 to 70

20 Ld PDIP

X9221AYPZ (Note)

X9221AYP Z

0 to 70

20 Ld PDIP (Pb-free)

X9221AYPI

-40 to 85

20 Ld PDIP

X9221AYPIZ (Note)

X9221AYPI Z

-40 to 85

20 Ld PDIP (Pb-Free)

X9221AYS*

X9221AYS

0 to 70

20 Ld SOIC (300MIL)

X9221AYSZ* (Note)

X9221AYS Z

0 to 70

20 Ld SOIC (300MIL) (Pb-Free)

X9221AYSI*

X9221AYSI

-40 to 85

20 Ld SOIC (300MIL)

X9221AYSIZ* (Note)

X9221AYSI Z

-40 to 85

20 Ld SOIC (300MIL) (Pb-Free)

X9221AWP

0 to 70

20 Ld PDIP

X9221AWPZ (Note)

X9221AWP Z

0 to 70

20 Ld PDIP (Pb-Free)

X9221AWPI

-40 to 85

20 Ld PDIP

X9221AWPIZ (Note)

X9221AWPI Z

-40 to 85

20 Ld PDIP (Pb-Free)

X9221AWS*

X9221AWS

0 to 70

20 Ld SOIC (300MIL)

X9221AWSZ* (Note)

X9221AWS Z

0 to 70

20 Ld SOIC (300MIL) (Pb-Free)

X9221AWSI*

X9221AWSI

-40 to 85

20 Ld SOIC (300MIL)

X9221AWSIZ* (Note)

X9221AWSI Z

-40 to 85

20 Ld SOIC (300MIL) (Pb-Free)

X9221AUP

0 to 70

20 Ld PDIP

X9221AUPZ (Note)

X9221AUP Z

0 to 70

20 Ld PDIP (Pb-Free)

X9221AUPI

-40 to 85

20 Ld PDIP

X9221AUPIZ (Note)

X9221AUPI Z

-40 to 85

20 Ld PDIP (Pb-Free)

X9221AUS*

X9221AUS

0 to 70

20 Ld SOIC (300MIL)

X9221AUSZ* (Note)

X9221AUS Z

0 to 70

20 Ld SOIC (300MIL) (Pb-Free)

X9221AUSI*

X9221AUSI

-40 to 85

20 Ld SOIC (300MIL)

X9221AUSIZ* (Note)

X9221AUSI Z

-40 to 85

20 Ld SOIC (300MIL) (Pb-Free)

*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

X9221A

FN8163.1

September 14, 2005

PIN DESCRIPTIONS

Host Interface Pins

Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9221A.

Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical val-
ues, refer to the guidelines for calculating typical val-
ues on the bus pull-up resistors graph.

Address
The Address inputs are used to set the least signifi-
cant 4 bits of the 8-bit slave address. A match in the
slave address serial data stream must be made with
the Address input in order to initiate communication
with the X9221A

Potentiometer Pins

-V

), V

-V

)

The V

and V

inputs are equivalent to the ter-

minal connections on either end of a mechanical
potentiometer.

-V

)

The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.

PIN CONFIGURATION

PIN NAMES

PRINCIPLES OF OPERATION

The X9221A is a highly integrated microcircuit incor-
porating two resistor arrays, their associated registers
and counters and the serial interface logic providing
direct communication between the host and the XDCP
potentiometers.

Serial Interface
The X9221A supports a bidirectional bus oriented pro-
tocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers and pro-
vide the clock for both transmit and receive operations.
Therefore, the X9221A will be considered a slave
device in all applications.

Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods (t

LOW

). SDA state changes during

SCL HIGH are reserved for indicating start and stop
conditions.

Start Condition
All commands to the X9221A are preceded by the
start condition, which is a HIGH to LOW transition of
SDA while SCL is HIGH (t

HIGH

). The X9221A continu-

ously monitors the SDA and SCL lines for the start
condition, and will not respond to any command until
this condition is met.

Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA while
SCL is HIGH.

SDA

1
2

3
4

5
6

7
8

20
19

18
17

16
15

14
13

RES

RES
A1

A3
SCL

RES
RES

RES

DIP/SOIC

X9221A

Symbol

Description

SCL

Serial Clock

SDA

Serial Data

A0A3

Address

-V

Potentiometers

(terminal equivalent)

-V

Potentiometers

(wiper equivalent)

RES

Reserved (Do not connect)

X9221A

FN8163.1

September 14, 2005

Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data. See Figure 7.

The X9221A will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the com-
mand byte. If the command is followed by a data byte
the X9221A will respond with a final acknowledge.

Array Description
The X9221A is comprised of two resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V

and V

inputs).

At both ends of each array and between each resistor
segment is a FET switch connected to the wiper
(V

) output. Within each individual array only one

switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
six least significant bits of the WCR are decoded to
select, and enable, one of sixty-four switches.

The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the WCR. These data registers and
the WCR can be read and written by the host system.

Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most signifi-
cant four bits of the slave address are the device type
identifier (refer to Figure 1 below). For the X9221A this
is fixed as 0101[B].

Figure 1. Slave Address

The next four bits of the slave address are the device
address. The physical device address is defined by
the state of the A0-A3 inputs. The X9221A compares
the serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9221A to respond with an acknowledge.

Acknowledge Polling
The disabling of the inputs, during the internal nonvol-
atile write operation, can be used to take advantage of
the typical 5ms EEPROM write cycle time. Once the
stop condition is issued to indicate the end of the non-
volatile write command the X9221A initiates the inter-
nal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition
followed by the device slave address. If the X9221A is
still busy with the write operation no ACK will be
returned. If the X9221A has completed the write oper-
ation an ACK will be returned and the master can then
proceed with the next operation.

Flow 1. ACK Polling Sequence

Device Type

Identifier

Device Address

Nonvolatile Write

Command Completed

Enter ACK Polling

Issue

START

Issue Slave

Address

ACK

Returned?

Further

Operation?

Issue

Instruction

Proceed

Issue STOP

YES

Proceed

Issue STOP

X9221A

FN8163.1

September 14, 2005

Instruction Structure
The next byte sent to the X9221A contains the instruc-
tion and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of two pots and when applicable they
point to one of four associated registers. The format is
shown below in Figure 2.

Figure 2. Instruction Byte Format

The four high order bits define the instruction. The
sixth bit (P0) selects which one of the two potentiome-
ters is to be affected by the instruction. The last two
bits (R1 and R0) select one of the four registers that is
to be acted upon when a register oriented instruction
is issued.

Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is illus-
trated in Figure 3. These two-byte instructions
exchange data between the WCR and one of the data
registers. A transfer from a data register to a WCR is
essentially a write to a static RAM. The response of
the wiper to this action will be delayed t

STPWV

. A

transfer from WCR's current wiper position to a data
register is a write to nonvolatile memory and takes a
minimum of t

to complete. The transfer can occur

between either potentiometer and their associated
registers or it may occur between both of the potenti-
ometers and one of their associated registers.

Four instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9221A; either between the host and
one of the data registers or directly between the host
and the WCR. These instructions are: Read WCR,
read the current wiper position of the selected pot;
Write WCR, change current wiper position of the
selected pot; Read Data Register, read the contents of
the selected nonvolatile register; Write Data Register,
write a new value to the selected data register. The
sequence of operations is shown in Figure 4.

The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9221A has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine
tuning capability to the host. For each SCL clock pulse
(t

HIGH

) while SDA is HIGH, the selected wiper will

move one resistor segment towards the V

termi-

nal. Similarly, for each SCL clock pulse while SDA is
LOW, the selected wiper will move one resistor seg-
ment towards the V

terminal. A detailed illustra-

tion of the sequence and timing for this operation are
shown in Figures 5 and 6 respectively.

Figure 3. Two-Byte Command Sequence

Potentiometer

Select

Instructions

A3 A2 A1 A0

P0 R1 R0

SCL

SDA

X9221A

FN8163.1

September 14, 2005

Table 1. Instruction Set

Note: (7) N/A = Not applicable or don't care; that is, a data register is not involved in the operation and need not be addressed (typical)

Figure 7. Acknowledge Response from Receiver

Instruction

Instruction Format

Operation

Read WCR

1/0 N/A

(7)

N/A Read the contents of the Wiper Counter Register

pointed to by P

Write WCR

1/0

N/A

N/A Write new value to the Wiper Counter Register

pointed to by P

Read Data Register

1/0

Read the contents of the Register pointed to by

and R

Write Data Register

1/0

Write new value to the Register pointed to by P

and R

XFR Data Register to

WCR

1/0

Transfer the contents of the Register pointed to

by P

and R

to its associated WCR

XFR WCR to Data

1/0

Transfer the contents of the WCR pointed to by

to the Register pointed to by R

Global XFR Data

N/A

1/0

Transfer the contents of the Data Registers

pointed to by R

of both pots to their

respective WCR

Global XFR WCR

to Data Register

N/A

1/0

Transfer the contents of all WCRs to their

respective data Registers pointed to by R

of both pots

Increment/Decrement

Wiper

1/0

N/A

N/A Enable Increment/decrement of the WCR point-

ed to by P

SCL from

Data Output

START

Acknowledge

Master

from Transmitter

Data Output

from Receiver

X9221A

FN8163.1

September 14, 2005

DETAILED OPERATION

Both XDCP potentiometers share the serial interface
and share a common architecture. Each potentiometer
is comprised of a resistor array, a wiper counter regis-
ter and four data registers. A detailed discussion of the
register organization and array operation follows.

Wiper Counter Register
The X9221A contains two wiper counter registers
(WCR), one for each XDCP potentiometer. The WCR
can be envisioned as a 6-bit parallel and serial load
counter with its outputs decoded to select one of sixty-
four switches along its resistor array. The contents of
the WCR can be altered in four ways: it may be written
directly by the host via the Write WCR instruction
(serial load); it may be written indirectly by transferring
the contents of one of four associated data registers
via the XFR Data Register instruction (parallel load); it
can be modified one step at a time by the Increment/
Decrement instruction; finally, it is loaded with the con-
tents of its data register zero (R0) upon power-up.

The WCR is a volatile register; that is, its contents are
lost when the X9221A is powered-down. Although the
register is automatically loaded with the value in R0
upon power-up, it should be noted this may be differ-
ent from the value present at power-down.

Data Registers
Each potentiometer has four nonvolatile data regis-
ters. These can be read or written directly by the host
and data can be transferred between any of the four
data registers and the WCR. It should be noted all
operations changing data in one of these registers is a
nonvolatile operation and will take a maximum of
10ms.

If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could possibly
store system parameters or user preference data.

Figure 8. Detailed Potentiometer Block Diagram

Serial Data Path

From Interface

Circuitry

Serial
Bus

Input

Parallel
Bus

Input

Wiper

Counter

INC/DEC

Logic

UP/DN

CLK

Modified SCL

UP/DN

If WCR = 00[H] then V

= V

If WCR = 3F[H] then V

= V

X9221A

FN8163.1

September 14, 2005

ABSOLUTE MAXIMUM RATINGS

Temperature Under Bias ................... -65°C to +135°C
Storage Temperature ........................ -65°C to +150°C
Voltage on SCK, SCL or Any Address

Input With Respect to V

...................... -1V to +7V

Voltage on Any V

, V

or V

Referenced to V

................................. +6V / -4.3V

V = |V

|........................................... 10.3V

Lead Temperature (soldering, 10 seconds)....... 300°C
I

(10s) ..............................................................±6mA

COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
indicated in the operational sections of this specifica-
tion) is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect
device reliability.

ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Symbol

Parameter

Limits

Test Conditions

Min.

Typ.

Max.

Unit

TOTAL

End to End Resistance

-20

+20

Power Rating

25°C, each pot

Wiper Current

-3

Wiper Resistance

130

Wiper Current = ±1mA

TERM

Voltage on any V

, V

-3.0

Noise

120

dBV

Ref: 1V

Resolution 1.6

See

Note

Absolute Linearity

(1)

-1

(3)

w(n)(actual -

w(n)(expected)

Relative Linearity

(2)

-0.2

+0.2

(3)

w(n + 1)

- [V

w(n) + MI

]

Temperature Coefficient

±300

ppm/°C See Note 5

Radiometric Temperature Coefficient

±20

ppm/°C See Note 5

Potentiometer Capacitances

10/10/25

See circuit #3

RECOMMENDED OPERATING CONDITIONS

Temp

Min.

Max.

Commercial

+70

Industrial

-40

+85

Supply Voltage

Limits

X9221A

5V ± 10%

X9221A

FN8163.1

September 14, 2005

D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as

a potentiometer.

(2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potenti-

ometer. It is a measure of the error in step size.

(3) MI = RTOT/63 or (V

)/63, single pot

ENDURANCE AND DATA RETENTION

CAPACITANCE

POWER-UP TIMING

Notes: (5) This parameter is periodically sampled and not 100% tested.

(6) t

PUR

and t

PUW

are the delays required from the time V

is stable until the specified operation can be initiated. These parameters are

periodically sampled and not 100% tested.

Power Up Requirements (Power up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First V

, then the potentiometer pins. It is suggested that V

reach 90% of its final value before power is applied to the potentiometer pins. The V

ramp rate specification should

be met, and any glitches or slope changes in the V

line should be held to <100mV if possible. Also, V

should not

reverse polarity by more than 0.5V.

Symbol

Parameter

Limits

Test Conditions

Min. Typ.

Max.

Unit

Supply Current (Active)

SCL

= 100kHz, SDA = Open, Other Inputs = V

Current (Standby)

200

500

µA

SCL = SDA = V

, Addr. = V

Input Leakage Current

µA

= V

to V

Output Leakage Current

µA

OUT

= V

to V

Input HIGH Voltage

+ 1

Input LOW Voltage

-1

0.8

Output LOW Voltage

0.4

= 3mA

Parameter

Min.

Unit

Minimum endurance

100,000

Data changes per bit per register

Data retention

100

years

Symbol

Parameter

Max.

Unit

Test Conditions

I/O

(5)

Input/output capacitance (SDA)

I/O

= 0V

(5)

Input capacitance (A0, A1, A2, A3 and SCL)

= 0V

Symbol

Parameter

Min.

Max.

Unit

PUR

(6)

Power-up to initiation of read operation

PUW

(6)

Power-up to initiation of write operation

Power-up ramp rate

0.2

V/msec

X9221A

FN8163.1

September 14, 2005

A.C. CONDITIONS OF TEST

SYMBOL TABLE

Equivalent A.C. Test Circuit

Circuit #3 SPICE Macro Model

Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors

Input pulse levels

x 0.1 to V

x 0.9

Input rise and fall times

10ns

Input and output timing levels

x 0.5

WAVEFORM

INPUTS

OUTPUTS

Must be

steady

Will be

steady

May change

from LOW

to HIGH

Will change

from LOW

to HIGH

May change

from HIGH

to LOW

Will change

from HIGH

to LOW

Don't Care:

Changes

Allowed

Changing:

State Not

Known

N/A

Center Line

is High

Impedance

1533

100pF

SDA Output

10pF

TOTAL

25pF

10pF

Macro Model

120

100

20 40 60

80 100 120

Bus Capacitance (pF)

Min.

Resistance

Max.

Resistance

MAX

BUS

MIN

OL MIN

CC MAX

=1.8k

esistan

ce (k

)

X9221A

FN8163.1

September 14, 2005

TIMING DIAGRAMS

Figure 10. Input Bus Timing

Figure 11. Output Bus Timing

A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise stated)

Symbol

Parameter

Limits

Unit

Reference

Figure

Min.

Max.

SCL

SCL clock frequency

100

kHz

LOW

Clock LOW period

4700

HIGH

Clock HIGH period

4000

SCL and SDA rise time

1000

SCL and SDA fall time

300

Noise suppression time constant (glitch filter)

100

SU:STA

Start condition setup time (for a repeated start condition)

4700

10 & 12

HD:STA

Start condition hold time

4000

10 & 12

SU:DAT

Data in setup time

250

HD:DAT

Data in hold time

SCL LOW to SDA data out valid

300

3500

Data out hold time

300

SU:STO

Stop condition setup time

4700

10 & 12

BUF

Bus free time prior to new transmission

4700

Write cycle time (nonvolatile write operation)

STPWV

Wiper response time from stop generation

1000

µs

CLWV

Wiper response from SCL LOW

500

µs

HIGH

SU:STA

HD:STA

HD:DAT

SU:DAT

LOW

SU:STO

BUF

SCL

SDA

(Data in)

SCL

SDA

OUT

(ACK)

SDA

OUT

SDA

OUT

X9221A

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8163.1

September 14, 2005

PACKAGING INFORMATION

0.290 (7.37)

0.299 (7.60)

0.393 (10.00)
0.420 (10.65)

0.014 (0.35)
0.020 (0.50)

Pin 1

Pin 1 Index

0.050 (1.27)

0.496 (12.60)
0.508 (12.90)

0.003 (0.10)
0.012 (0.30)

0.092 (2.35)
0.105 (2.65)

(4X) 7°

20-Lead Plastic Small Outline Gull Wing Package Type S

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

0.420"

0.050" Typical

0.050"

Typical

0.030" Typical

20 Places

FOOTPRINT

0.010 (0.25)
0.020 (0.50)

0.015 (0.40)
0.050 (1.27)

0.007 (0.18)
0.011 (0.28)

0°8°

X 45°

X9221A

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