X9258

Low Noise/Low Power/2-Wire Bus/256 Taps

Quad Digital Controlled Potentiometers

(XDCPTM)

FEATURES

· Four potentiometers in one package
· 256 resistor taps/pot0.4% resolution
· 2-wire serial interface
· Wiper resistance, 40

typical @ V+ = 5V, V- = -5V

· Four nonvolatile data registers for each pot
· Nonvolatile storage of wiper position
· Standby current < 5µA max (total package)
· Power supplies

--V

= 2.7V to 5.5V

--V+ = 2.7V to 5.5V
--V- = -2.7V to -5.5V

· 100k

, 50k

total pot resistance

· High reliability

--Endurance 100,000 data changes per bit per

register

--Register data retention 100 years

· 24-lead SOIC, 24-lead TSSOP
· Dual supply version of X9259

DESCRIPTION

The X9258 integrates 4 digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated circuit.

The digitally controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
2-wire bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and 4 nonvolatile Data Registers (DR0:DR3)
that can be directly written to and read by the user.
The contents of the WCR controls the position of the
wiper on the resistor array though the switches. Power
up recalls the contents of DR0 to the WCR.

The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.

BLOCK DIAGRAM

Interface

and

Control

Circuitry

SCL

SDA

A0
A1
A2
A3

Wiper

Counter

(WCR)

Resistor

Array
Pot 1

Wiper

Counter

(WCR)

Data

Resistor

Array

Resistor

Array

Wiper

Counter

(WCR)

Wiper

Counter

(WCR)

Pot 3

Pot 2

Pot 0

V+
V-

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-352-6832

Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Data Sheet

FN8168.1

May 6, 2005

FN8168.1

May 6, 2005

PIN DESCRIPTIONS

Host Interface Pins

ERIAL

LOCK

(SCL)

The SCL input is used to clock data into and out of the
X9258.

ERIAL

ATA

(SDA)

SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical
values on the bus pull-up resistors graph.

EVICE

DDRESS

- A

)

The Address inputs are used to set the least
significant 4 bits of the 8-bit slave address. A match in
the slave address serial data stream must be made
with the address input in order to initiate
communication with the X9258. A maximum of 16
devices may occupy the 2-wire serial bus.

Potentiometer Pins

- V

), V

)

The V

and V

inputs are equivalent to the

terminal connections on either end of a mechanical
potentiometer.

- V

)

The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.

Hardware Write Protect Input (WP)

The WP pin when low prevents nonvolatile writes to
the Data Registers.

Analog Supplies V+, V-

The Analog Supplies V+, V- are the supply voltages for
the DCP analog section.

PIN CONFIGURATION

PIN NAMES

PRINCIPLES OF OPERATION

The X9258 is a highly integrated microcircuit
incorporating four resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the DCP potentiometers.

Serial Interface--2-Wire

The X9258 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers

Symbol

Description

SCL

Serial Clock

SDA

Serial Data

A0-A3

Device Address

- V

Potentiometer Pins
(terminal equivalent)

- V

Potentiometers Pins
(wiper equivalent)

Hardware Write Protection

V+,V-

Analog Supplies

System Supply Voltage

System Ground

No Connection (Allowed)

V+

SCL

SOIC/TSSOP

X9258

SDA

X9258

FN8168.1

May 6, 2005

and provide the clock for both transmit and receive
operations. Therefore, the X9258 will be considered a
slave device in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during
SCL LOW periods (t

LOW

). SDA state changes during

SCL HIGH are reserved for indicating start and stop
conditions.

Start Condition

All commands to the X9258 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (t

HIGH

). The X9258 continuously

monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.

Stop Condition

All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.

Acknowledge

Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.

The X9258 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9258 will respond with a final acknowledge.

Array Description

The X9258 is comprised of four resistor arrays. Each
array contains 255 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V

and V

inputs).

At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(V

) output. Within each individual array only one

switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
8 bits of the WCR are decoded to select, and enable,
one of 256 switches.

The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the WCR. These data registers and
the WCR can be read and written by the host system.

Device Addressing

Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier (refer to Figure 1 below). For the X9258
this is fixed as 0101[B].

Figure 1. Slave Address

The next four bits of the slave address are the device
address. The physical device address is defined by the
state of the A0 - A3 inputs. The X9258 compares the
serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9258 to respond with an acknowledge. The A

- A

inputs can be actively driven by CMOS input

signals or tied to V

or V

Acknowledge Polling

The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms nonvolatile write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9258
initiates the internal write cycle. ACK polling can be
initiated immediately. This involves issuing the start
condition followed by the device slave address. If the
X9258 is still busy with the write operation no ACK will
be returned. If the X9258 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.

Device Type

Identifier

Device Address

X9258

FN8168.1

May 6, 2005

ACK Polling Sequence

Instruction Structure

The next byte sent to the X9258 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the two pots and when applicable
they point to one of four associated registers. The
format is shown below in Figure 2.

Figure 2. Instruction Byte Format

The four high order bits define the instruction. The next
two bits (R1 and R0) select one of the four registers
that is to be acted upon when a register oriented
instruction is issued. The last bits (P1, P0) select
which one of the four potentiometers is to be affected
by the instruction.

Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is
illustrated in Figure 3. These two-byte instructions
exchange data between the Wiper Counter Register
and one of the data registers. A transfer from a Data
Register to a Wiper Counter Register is essentially a
write to a static RAM. The response of the wiper to this
action will be delayed t

WRL

. A transfer from the Wiper

Counter Register (current wiper position), to a data
register is a write to nonvolatile memory and takes a
minimum of t

to complete. The transfer can occur

between one of the four potentiometers and one of its
associated registers; or it may occur globally, wherein
the transfer occurs between all of the potentiometers
and one of their associated registers.

Four instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9258; either between the host and
one of the data registers or directly between the host
and the Wiper Counter Register. These instructions
are: Read Wiper Counter Register (read the current
wiper position of the selected pot), Write Wiper
Counter Register (change current wiper position of the
selected pot), Read Data Register (read the contents
of the selected nonvolatile register) and Write Data
Register (write a new value to the selected data
register). The sequence of operations is shown in
Figure 4.

Nonvolatile Write

Command Completed

EnterACK Polling

Issue

START

Issue Slave

Address

ACK

Returned?

Further

Operation?

Issue

Instruction

Issue STOP

Yes

Proceed

Issue STOP

Proceed

Wiper Counter

Select

Instructions

X9258

FN8168.1

May 6, 2005

Figure 3. Two-Byte Instruction Sequence

The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9258 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine
tuning capability to the host. For each SCL clock pulse
(t

HIGH

) while SDA is HIGH, the selected wiper will

move one resistor segment towards the V

terminal.

Similarly, for each SCL clock pulse while SDA is LOW,
the selected wiper will move one resistor segment
towards the V

terminal. A detailed illustration of

the sequence and timing for this operation are shown
in Figures 5 and 6 respectively.

Table 1. Instruction Set

Note:

(1) 1/0 = data is one or zero

S
T
A
R
T

A
C
K

P1 P0

A
C
K

SCL

SDA

S
T
O
P

Instruction

Instruction Set

Operation

Read Wiper Counter
Register

1/0

Read the contents of the Wiper Counter Register
pointed to by P

- P

Write Wiper Counter
Register

1/0

Write new value to the Wiper Counter Register
pointed to by P

- P

Read Data Register

1/0

Read the contents of the Data Register pointed
to by P

- P

and R

- R

Write Data Register

1/0

Write new value to the Data Register pointed to
by P

- P

and R

- R

XFR Data Register to
Wiper Counter Register

1/0

Transfer the contents of the Data Register pointed
to by P

- P

and R

- R

to its associated Wiper

Counter Register

XFR Wiper Counter
Register to Data
Register

1/0

Transfer the contents of the Wiper Counter Reg-
ister pointed to by P

- P

to the Data Register

pointed to by R

- R

Global XFR Data
Registers to Wiper
Counter Registers

1/0

Transfer the contents of the Data Registers
pointed to by R

- R

of all four pots to their re-

spective Wiper Counter Registers

Global XFR Wiper
Counter Registers
to Data Register

1/0

Transfer the contents of both Wiper Counter
Registers to their respective data Registers
pointed to by R

- R

of all four pots

Increment/Decrement
Wiper Counter Register

1/0

Enable Increment/decrement of the Control Latch
pointed to by P

- P

X9258

FN8168.1

May 6, 2005

Figure 7. Acknowledge Response from Receiver

Figure 8. Detailed Potentiometer Block Diagram Detailed Operation

All DCP potentiometers share the serial interface and
share a common architecture. Each potentiometer has
a Wiper Counter Register and four Data Registers. A
detailed discussion of the register organization and
array operation follows.

Wiper Counter Register

The X9258 contains four Wiper Counter Registers,
one for each DCP potentiometer. The Wiper Counter
Register can be envisioned as a 8-bit parallel and
serial load counter with its outputs decoded to select

one of 256 switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated Data Registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/Decrement
instruction. Finally, it is loaded with the contents of its
data register zero (R0) upon power-up.

SCL from

Data Output

START

Acknowledge

Master

from Transmitter

Data Output

from Receiver

Serial Data Path

From Interface

Circuitry

Serial
BUS
Input

Parallel

BUS
Input

Wiper

Counter

INC/DEC

Logic

UP/DN

CLK

Modified SCL

UP/DN

If WCR = 00[H] then V

= V

If WCR = FF[H] then V

= V

o
u
n

o
d
e

(WCR)

X9258

FN8168.1

May 6, 2005

The WCR is a volatile register; that is, its contents are
lost when the X9258 is powered-down. Although the
register is automatically loaded with the value in R0
upon power-up, it should be noted this may be
different from the value present at power-down.

Data Registers

Each potentiometer has four nonvolatile Data
Registers. These can be read or written directly by the
host and data can be transferred between any of the
four Data Registers and the WCR. It should be noted
all operations changing data in one of these registers
is a nonvolatile operation and will take a maximum of
10ms.

If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could possibly
store system parameters or user preference data.

REGISTER DESCRIPTIONS

Data Registers, (8-Bit), Nonvolatile

Four 8-bit Data Registers for each DCP. (sixteen 8-bit
registers in total).

{D7~D0}: These bits are for general purpose not

volatile data storage or for storage of up to four
different wiper values. The contents of Data Register
0 are automatically moved to the wiper counter
register on power-up.

Wiper Counter Register, (8-Bit), Volatile

Instruction Format

Notes: (1) "MACK"/"SACK": stands for the acknowledge sent by the master/slave.

(2) "A3 ~ A0": stands for the device addresses sent by the master.
(3) "X": indicates that it is a "0" for testing purpose but physically it is a "don't care" condition.
(4) "I": stands for the increment operation, SDA held high during active SCL phase (high).
(5) "D": stands for the decrement operation, SDA held low during active SCL phase (high).

Read Wiper Counter Register (WCR)

Write Wiper Counter Register (WCR)

Read Data Register (DR)

WP7

WP6

WP5

WP4

WP3

WP2

WP1

WP0

(MSB)

(LSB)

WP7

WP6

WP5

WP4

WP3

WP2

WP1

WP0

A
R

device type

identifier

device

addresses

S
A

instruction

opcode

WCR

addresses

S
A
C
K

wiper position

(sent by slave on SDA)

A
C
K

S
T

A
R

device type

identifier

device

addresses

S
A

instruction

opcode

WCR

addresses

S
A
C
K

Data Byte

(sent by master on SDA)

S
A
C
K

S
T

A
R

device type

identifier

device

addresses

S
A
C
K

instruction

opcode

DR and WCR

addresses

S
A
C
K

Data Byte

(sent by slave on SDA)

A
C
K

S
T

X9258

FN8168.1

May 6, 2005

Write Data Register (WR)

XFR Data Register (DR) to Wiper Counter Register (WCR)

XFR Wiper Counter Register (WCR) to Data Register (DR)

Increment/Decrement Wiper Counter Register (WCR)

Global XFR Data Register (DR) to Wiper Counter Register (WCR)

Global XFR Wiper Counter Register (WCR) to Data Register (DR)

A
R

device type

identifier

device

addresses

S
A
C
K

instruction

opcode

DR and WCR

addresses

S
A
C
K

Data Byte

(sent by master on SDA)

S
A

HIGH-VOLTAGE

WRITE CYCLE

0 1 0 1

1 1 0 0

A
R

device type

identifier

device

addresses

S
A

instruction

opcode

DR and WCR

addresses

S
A
C
K

0 1 0 1

1 1 0 1

S
T
A
R
T

device type

identifier

device

addresses

S
A
C
K

instruction

opcode

DR and WCR

addresses

S
A
C
K

HIGH-VOLTAGE

WRITE CYCLE

0 1 0

1 1

S
T
A

device type

identifier

device

addresses

S
A
C
K

instruction

opcode

WCR

addresses

S
A
C
K

increment/decrement

(sent by master on SDA)

S
T

A
R

device type

identifier

device

addresses

S
A
C
K

instruction

opcode

addresses

S
A
C
K

S
T

S
T
A

device type

identifier

device

addresses

S
A

instruction

opcode

addresses

S
A

S
T

HIGH-VOLTAGE

WRITE CYCLE

0 1 0 1

1 0 0 0

0 0

X9258

FN8168.1

May 6, 2005

ABSOLUTE MAXIMUM RATINGS

Temperature under bias..................... -65

C to +135

Storage temperature ......................... -65

C to +150

Voltage on SDA, SCL or any address input

with respect to V

................................. -1V to +7V

Voltage on V+ (referenced to V

) ........................ 10V

Voltage on V- (referenced to V

) ........................-10V

(V+) - (V-)............................................................... 12V
Any V

...............................................................V+

Any V

................................................................. V-

Lead temperature (soldering, 10 seconds) ........ 300

(10 seconds)................................................±15mA

COMMENT

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

ANALOG CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)

Symbol

Parameter

Limits

Test Conditions

Min.

Typ.

Max.

Unit

End to end resistance tolerance

±20

Power rating

25°C, each pot

Wiper current

±7.5

Wiper current =

1mA

Wiper resistance

150

250

1mA @ V+ = 3V, V- = -3V

Wiper resistance

100

1mA @ V+ = 5V, V- = -5V

V+

Voltage on V+ Pin

X9258

+4.5

+5.5

X9258-2.7

+2.7

+5.5

V-

Voltage on V- Pin

X9258

-5.5

-4.5

X9258 -2.7

-5.5

-2.7

TERM

Voltage on any V

or V

V-

V+

Noise

-120

dBV

Ref: 1kHz

Resolution

(4)

0.6

Absolute linearity

(1)

±1

(3)

w(n)(actual)

- V

w(n)(expected)

Relative linearity

(2)

±0.6

(3)

w(n + 1)

- [V

w(n) + MI

]

Temperature coefficient of R

TOTAL

300

ppm/

Ratiometric Temperature Coefficient

±20

ppm/°C

Potentiometer Capacitance

10/10/25

See Circuit #3

RECOMMENDED OPERATING CONDITIONS

Temp

Min.

Max.

Commercial

+70

Industrial

-40

+85

Device

Supply Voltage (V

) Limits

X9258

10%

X9258-2.7

2.7V to 5.5V

X9258

FN8168.1

May 6, 2005

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a

potentiometer.

(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiom-

eter. It is a measure of the error in step size.

(3) MI = RTOT/255 or (V

--V

)/255, single pot

(4) Max. = all four arrays cascaded together, Typical = individual array resolutions.

ENDURANCE AND DATA RETENTION

CAPACITANCE

POWER-UP TIMING

POWER UP AND DOWN REQUIREMENT

The are no restrictions on the sequencing of the bias supplies V

, V+, and V- provided that all three supplies reach

their final values within 1msec of each other. At all times, the voltages on the potentiometer pins must be less than V+
and more than V-. The recall of the wiper position from nonvolatile memory is not in effect until all supplies reach their
final value. The V

ramp rate spec is always in effect.

Notes: (5) This parameter is periodically sampled and not 100% tested.

(6) t

PUR

and t

PUW

are the delays required from the time the third (last) power supply (V

, V+ or V-) is stable until the specific

instruction can be issued. These parameters are periodically sampled and not 100% tested.

(7) Sample tested only.

Symbol

Parameter

Limits

Test Conditions

Min.

Typ.

Max.

Unit

CC1

supply current (Nonvol-

atile Write)

SCL

= 400kHz, SDA = Open,

Other Inputs = V

CC2

supply current (move

wiper, write, read)

100

µA

SCL

= 400kHz, SDA = Open,

Other Inputs = V

current (standby)

µA

SCL = SDA = V

, Addr. = V

Input leakage current

µA

= V

to V

Output leakage current

µA

OUT

= V

to V

Input HIGH voltage

x 0.7

+ 0.1

Input LOW voltage

-0.5

x 0.3

Output LOW voltage

0.4

= 3mA

Parameter

Min.

Unit

Minimum endurance

100,000

Data changes per bit per register

Data retention

100

years

Symbol

Test

Max.

Unit

Test Conditions

I/O

(5)

Input/output capacitance (SDA)

I/O

= 0V

(5)

Input capacitance (A0, A1, A2, A3, and SCL)

= 0V

Symbol

Parameter Min.

Max.

Unit

PUR

(6)

Power-up to initiation of read operation

PUW

(6)

Power-up to initiation of write operation

(7)

Power up ramp

0.2

V/msec

X9258

FN8168.1

May 6, 2005

A.C. TEST CONDITIONS

EQUIVALENT A.C. LOAD CIRCUIT

Test Circuit #3 SPICE Macro Model

AC TIMING (Over recommended operating condition)

HIGH-VOLTAGE WRITE CYCLE TIMING

Input pulse levels

x 0.1 to V

x 0.9

Input rise and fall times

10ns

Input and output timing level

x 0.5

1533

100pF

SDA Output

2.7V

100pF

10pF

TOTAL

25pF

10pF

Macro Model

Symbol

Parameter

Min.

Max.

Unit

SCL

Clock frequency

400

kHz

CYC

Clock cycle time

2500

HIGH

Clock high time

600

LOW

Clock low time

1300

SU:STA

Start setup time

600

HD:STA

Start hold time

600

SU:STO

Stop setup time

600

SU:DAT

SDA data input setup time

100

HD:DAT

SDA data input hold time

SCL and SDA rise time

300

SCL and SDA fall time

300

SCL low to SDA data output valid time

900

SDA data output hold time

Noise suppression time constant at SCL and SDA inputs

BUF

Bus free rime (prior to any transmission)

1300

SU:WPA

WP, A0, A1, A2 and A3 setup time

HD:WPA

WP, A0, A1, A2 and A3 hold time

Symbol

Parameter

Typ.

Max.

Unit

High-voltage write cycle time (store instructions)

X9258

FN8168.1

May 6, 2005

DCP TIMING

Note:

(8) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling

edge of SCL.

TIMING DIAGRAMS 2-WIRE INTERFACE

START and STOP Timing

Input Timing

Output Timing

Symbol

Parameter

Min.

Max.

Unit

WRPO

Wiper response time after the third (last) power supply is stable

µs

WRL

Wiper response time after instruction issued (all load instructions)

µs

WRID

Wiper response time from an active SCL/SCK edge (increment/decrement instruction)

µs

SU:STA

HD:STA

SU:STO

SCL

SDA

(START)

(STOP)

SCL

SDA

HIGH

LOW

CYC

HD:DAT

SU:DAT

BUF

SCL

SDA

X9258

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Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8168.1

May 6, 2005

Ordering Information

Device

Limits

Blank = 5V

10%

-2.7 = 2.7 to 5.5V

Temperature Range
Blank = Commercial = 0

C to +70

I = Industrial = -40

C to +85

Package
S24 = 24-Lead SOIC
V24 = 24-Lead TSSOP

Potentiometer Organization
T =

100K

50k

X9258

S & V Package Marking

Line #1

(Blank)

Line #2

(Part Number)

Line #3

(Date Code) (*)

Line #4

(Blank)

= F

2.7V 0 to 70°C

G 2.7V -40 to +85°C
I

-40 to +85°C

X9258

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X9258US24

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: X9258US24